JPH0531945B2 - - Google Patents

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Publication number
JPH0531945B2
JPH0531945B2 JP62072271A JP7227187A JPH0531945B2 JP H0531945 B2 JPH0531945 B2 JP H0531945B2 JP 62072271 A JP62072271 A JP 62072271A JP 7227187 A JP7227187 A JP 7227187A JP H0531945 B2 JPH0531945 B2 JP H0531945B2
Authority
JP
Japan
Prior art keywords
signal
frequency
ddl
output
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP62072271A
Other languages
Japanese (ja)
Other versions
JPS63238483A (en
Inventor
Seiichi Kanegae
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62072271A priority Critical patent/JPS63238483A/en
Publication of JPS63238483A publication Critical patent/JPS63238483A/en
Publication of JPH0531945B2 publication Critical patent/JPH0531945B2/ja
Granted legal-status Critical Current

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  • Radar Systems Or Details Thereof (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、パルスレーダ装置に関するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pulse radar device.

〔従来の技術〕[Conventional technology]

従来技術の例として、よく用いられるレーダ装
置のブロツク図を第2図に示す。図において、1
はアンテナ、2は送受切換器、3は第2の周波数
変換器、4はIF増幅器、5は第2のDDL(chirp
方向:up chirp)、6は検波器、7は信号処理器、
8は局部信号発生器、9は電力増幅器、10は第
1の周波数変換器、11はゲート回路、12は第
1のDDL(chirp方向:up chirp)、13はインパ
ルス信号発生器、14は送信パルス発生器、15
は基準信号発生器、17は第3の周波数変換器で
ある。
As an example of the prior art, a block diagram of a commonly used radar device is shown in FIG. In the figure, 1
is the antenna, 2 is the transmitter/receiver, 3 is the second frequency converter, 4 is the IF amplifier, 5 is the second DDL (chirp
Direction: up chirp), 6 is the detector, 7 is the signal processor,
8 is a local signal generator, 9 is a power amplifier, 10 is a first frequency converter, 11 is a gate circuit, 12 is a first DDL (chirp direction: up chirp), 13 is an impulse signal generator, 14 is a transmission pulse generator, 15
is a reference signal generator, and 17 is a third frequency converter.

基準信号発生器15よりIF信号と同じ周波数
(fI)の信号をインパルス信号発生器13へ送り、
送信パルスパ発生器14より送られたインパルス
タイミング信号によりインパルス信号として、
chirp方向がupである第1のDDL12へ入力し、
周波数変調伸張パルス信号を出力する。上記周波
数変調伸張パルス信号は、前記送信パルス発生器
14より送られる送信タイミング信号によりゲー
ト回路11にて送信パルス幅分のみ通過し、第1
の周波数変換器10へ送られる。同時に、局部信
号発生器8より送られた局部信号(L)と、前記
基準信号発生器15より送られた中間周波数の2
倍に相当する周波数(2fI)の信号の周波数加算
fL+2fI)を第3の周波数変換器17にて行ない、
第1の周波数変換器10にて、前記送信パルス信
号と周波数変換(減算/fL+2fI−fI=fL+fI=fR
を行ないchirp方向をdown chirpとした送信周波
数とし、電力増幅器9にて電力増幅し、送受切換
器2及びアンテナ1を通して空中へ放射される。
目標に当たり反射信号となつた信号は受信信号と
してアンテナ1及び送受切換器2を通り、第2の
周波数変換器3にて、局部発振器8からの信号に
より周波数変換されIF信号となる。このIF信号
はIF増幅器4で増幅されchirp方向が、up chirp
である第2のDDL5でパルス圧縮処理を受け、
検波器6で検波されビデオ信号となつて信号処理
器7へ送られる。
A signal with the same frequency (f I ) as the IF signal is sent from the reference signal generator 15 to the impulse signal generator 13,
As an impulse signal by the impulse timing signal sent from the transmission pulse generator 14,
input to the first DDL 12 whose chirp direction is up,
Outputs a frequency modulated expanded pulse signal. The frequency modulated expanded pulse signal is passed through the gate circuit 11 by the transmission pulse width in response to the transmission timing signal sent from the transmission pulse generator 14, and the first
is sent to the frequency converter 10 of. At the same time, the local signal ( L ) sent from the local signal generator 8 and the intermediate frequency signal sent from the reference signal generator 15 are
A third frequency converter 17 performs frequency addition ( fL + 2f I ) of signals with a frequency (2f I ) corresponding to twice the frequency,
The first frequency converter 10 converts the transmission pulse signal and frequency (subtraction/f L +2f I −f I = f L + f I = f R )
The transmission frequency is set to down chirp in the chirp direction, the power is amplified by the power amplifier 9, and the signal is radiated into the air through the transmitter/receiver switch 2 and the antenna 1.
The signal that hits the target and becomes a reflected signal passes through the antenna 1 and the transmitter/receiver switch 2 as a received signal, and is frequency-converted by the signal from the local oscillator 8 at the second frequency converter 3 to become an IF signal. This IF signal is amplified by IF amplifier 4, and the chirp direction is up chirp.
undergoes pulse compression processing in the second DDL5, which is
The signal is detected by a detector 6 and sent to a signal processor 7 as a video signal.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

このような従来のレーダ装置では、IF周波数
帯fIにおけるパルス圧縮機能の評価を行なうため
には、必ずRF周波数帯(送受信を行なう周波数
帯、fR)を通す以外に方法はない。理由は、周波
数変調伸張信号を発生する第1のDDLと、パル
ス圧縮処理を行なう第2のDDLが、共に同一の
chirp方向を用いているためである。
In such a conventional radar device, the only way to evaluate the pulse compression function in the IF frequency band f I is to pass through the RF frequency band (frequency band for transmitting and receiving, f R ). The reason is that the first DDL that generates the frequency modulation expansion signal and the second DDL that performs pulse compression processing are both the same.
This is because the chirp direction is used.

これは、受信系のウエイライングフイルタを別
に考えるならば、chirp方向を同一にすれば、第
1と第2のDDLは、全く同じ物を使用できるメ
リツトがあるためである。
This is because, considering the receiving system's waylining filter separately, if the chirp direction is made the same, there is an advantage that the first and second DDLs can use exactly the same thing.

しかしながら、試験の容易性という観点から
は、IF周波数帯の試験信号が使えないのは問題
である。
However, from the viewpoint of ease of testing, it is a problem that test signals in the IF frequency band cannot be used.

同時に、第3の周波数変換器17を設けること
により第1の周波数変換器10にてchirp方向を
up chirpからdown chirpへ変換する操作を行な
う必要が生じ、ハードウエアが増大するという問
題もある。
At the same time, by providing the third frequency converter 17, the chirp direction can be changed by the first frequency converter 10.
There is also the problem that it becomes necessary to perform an operation of converting an up chirp to a down chirp, which increases the amount of hardware.

本発明は、従来技術の問題点を解消しようとす
るものである。
The present invention seeks to overcome the problems of the prior art.

〔問題点を解決するための手段〕 周波数変調伸張信号を発生する第1のDDLと
パルス圧縮処理を行なう第2のDDLのchirp方向
をそれぞれup chirp,down chirpとすると同時
に、ゲート回路の出力に分配器を設け、IF周波
数帯の試験信号をとり出すことができるようにし
た。
[Means for solving the problem] The chirp directions of the first DDL that generates the frequency modulation expansion signal and the second DDL that performs pulse compression processing are made up chirp and down chirp, respectively, and at the same time, the output of the gate circuit is A splitter was installed to make it possible to extract test signals in the IF frequency band.

〔作用〕[Effect]

上記の手段により、IF周波数帯の試験信号を、
IF増幅器の入力又は、第2のDDLの入力に入れ
ることにより、RF帯を経由しないでパルス圧縮
の試験を行なうことができる。
By the above means, the test signal in the IF frequency band is
By inputting it to the input of the IF amplifier or the input of the second DDL, pulse compression tests can be performed without passing through the RF band.

同時に、第1の周波数変換器にてchirp方向を
反転させる必要がなくなるため、第3の周波数変
換器は不要となり、ハードウエアの削減ができ
る。
At the same time, since it is no longer necessary to invert the chirp direction in the first frequency converter, the third frequency converter is no longer necessary, and hardware can be reduced.

〔実施例〕〔Example〕

以下、この発明の一実施例を図を用いて説明す
る。第1図は、ブロツク図であり、1〜15は従
来の装置と全く同一のものであり(但し、5の第
2のDDLのchirp方向はdown chirpである。)、1
6は分配器である。
An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram, in which 1 to 15 are exactly the same as the conventional device (however, the chirp direction of the second DDL of 5 is down chirp), and 1
6 is a distributor.

基準信号発生器15よりIF信号と同じ周波数
(fI)の信号をインパルス信号発生器13へ送り、
送信パルス発生器14より送られたインパルスタ
イミング信号によりインパルス信号としてchirp
方向がupである第1のDDL12へ入力し、周波
数変調伸張パルス信号を出力する。上記周波数変
調伸長パルス信号は、前記パルス発生器14より
送られる送信タイミング信号によりゲート回路1
1にて送信パルス幅分のみ通過し、分配器16を
通つて第1の周波数変換器10へ送られる。局部
信号発生器8より送られる局部信号にて送信周波
数へ周波数変換(加算/fL+fI=fR)され、電力
増幅器9にて電力増幅し、送受切換器2及びアン
テナ1を通して空中へ放射される。目標に当たり
反射信号となつた信号は受信信号としてアンテナ
11及び送受切換器2を通り、第2の周波数変換
器3にて、局部信号発生器8からの信号により周
波数変換されIF信号となる。このIF信号はIF増
幅器4で増幅されchirp方向がdown chirpである
第2のDDL5でパルス圧縮処理を受け、検波器
6で検波されビデオ信号となつて信号処理器7へ
送られる。
A signal with the same frequency (f I ) as the IF signal is sent from the reference signal generator 15 to the impulse signal generator 13,
chirp as an impulse signal by the impulse timing signal sent from the transmission pulse generator 14
The signal is input to the first DDL 12 whose direction is up, and a frequency modulated expanded pulse signal is output. The frequency modulated expanded pulse signal is transmitted to the gate circuit 1 by a transmission timing signal sent from the pulse generator 14.
1, the signal passes through only the width of the transmission pulse, and is sent to the first frequency converter 10 through the distributor 16. The local signal sent from the local signal generator 8 is frequency-converted to the transmission frequency (addition/f L + f I = f R ), power amplified by the power amplifier 9, and radiated into the air through the transmitter/receiver switch 2 and antenna 1. be done. The signal that hits the target and becomes a reflected signal passes through the antenna 11 and the transmitter/receiver switch 2 as a received signal, and is frequency-converted by the signal from the local signal generator 8 at the second frequency converter 3 to become an IF signal. This IF signal is amplified by an IF amplifier 4, subjected to pulse compression processing by a second DDL 5 whose chirp direction is down chirp, detected by a detector 6, and sent to a signal processor 7 as a video signal.

試験時には、分配器16の他方の出力信号を
IF帯の試験信号として、IF増幅器4又は第2の
DDL5の入力に加えることができる。
During testing, the other output signal of the distributor 16 is
IF amplifier 4 or the second
It can be added to the input of DDL5.

〔発明の効果〕〔Effect of the invention〕

この発明は、以上に示したように、IF周波数
帯の試験時には、分配器16の他方の出力信号を
試験信号としてIF増幅器4又は第2のDDL5へ
入力することができる。
In the present invention, as described above, when testing the IF frequency band, the other output signal of the divider 16 can be input to the IF amplifier 4 or the second DDL 5 as a test signal.

同時に、第1の周波数変換器10へ、局部信号
発生器8の信号を使用することができるので従来
の構成にあるような、第3の周波数変換器17は
不要となり、ハードウエアが削減できる。
At the same time, since the signal from the local signal generator 8 can be used for the first frequency converter 10, the third frequency converter 17, which is in the conventional configuration, is not required, and the hardware can be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、この発明の一実施例を示すレーダ装
置のブロツク図、第2図は、従来のレーダ装置の
ブロツク図である。 1はアンテナ、2は送受切換器、3は第2の周
波数変換器、4はIF増幅器、5は第2のDDL、
6は検波器、7は信号処理器、8は局部信号発生
器、9は電力増幅器、10は第1の周波数変換
器、11はゲート回路、12は第1のDDL、1
3はインパルス信号発生器、14は送信パルス発
生器、15は基準信号発生器、16は分配器、1
7は第3の周波数変換器である。なお、図中同一
あるいは相当部分には同一符号を示してある。
FIG. 1 is a block diagram of a radar device showing an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional radar device. 1 is an antenna, 2 is a transmission/reception switch, 3 is a second frequency converter, 4 is an IF amplifier, 5 is a second DDL,
6 is a wave detector, 7 is a signal processor, 8 is a local signal generator, 9 is a power amplifier, 10 is a first frequency converter, 11 is a gate circuit, 12 is a first DDL, 1
3 is an impulse signal generator, 14 is a transmission pulse generator, 15 is a reference signal generator, 16 is a distributor, 1
7 is a third frequency converter. Note that the same or corresponding parts in the figures are indicated by the same reference numerals.

Claims (1)

【特許請求の範囲】[Claims] 1 レーダのIF信号と同じ周波数を発生する基
準信号発生器と、送信タイミング及びインパルス
タイミングパルスを発生する送信パルス発生器
と、上記基準信号及びインパルスタイミング信号
を受けて、インパルス信号を発生するインパルス
信号発生器と、上記インパルス信号発生器の出力
信号を受けて、周波数変調伸張パルス信号を発生
する、チヤープ方向がアツプチヤープである第1
のDDL(分散遅延線の略:Dispersive Delay
Line)と、上記第1のDDLの出力信号を前記送
信パルス信号にてゲートをかけて送信パルス信号
のパルス幅を与えるゲート信号と、上記ゲート回
路の出力信号を分配器を介して入力し、上記ゲー
ト回路の出力信号を局部信号発生器よりの信号に
よつて送信周波数へ変換する第1の周波数変換器
と、上記第1の周波数変換器の出力を電力増幅す
る電力増幅器と、送信信号と受信信号を切替える
送受切換器と、送信信号を放射し、受信信号を受
けるアンテナと、上記局部信号発生器からの信号
を受けて受信信号を周波数変換する第2の周波数
変換器と、上記第2の周波数変換器の出力を増幅
するIF増幅器と、このIF増幅器で増幅された受
信信号をパルス圧縮するための、チヤープ方向が
ダウンチヤープである第2のDDLと、この第2
のDDLの出力を検波しビデオ信号とする検波器
と、上記ビデオ信号を受けて信号処理を行なう信
号処理器と、上記ゲート回路の出力信号を上記第
1の周波数変換回路へ入力させる一方、試験用
IF信号として上記IF増幅器又は第2のDDLへ入
力させる分配器とを具備したことを特徴とするレ
ーダ装置。
1. A reference signal generator that generates the same frequency as the radar IF signal, a transmission pulse generator that generates transmission timing and impulse timing pulses, and an impulse signal that receives the above reference signal and impulse timing signal and generates an impulse signal. a first pulse signal whose chirp direction is up-chip, which receives the output signal of the impulse signal generator and generates a frequency-modulated expanded pulse signal;
DDL (abbreviation for Dispersive Delay)
Line), a gate signal that gates the output signal of the first DDL with the transmission pulse signal to give the pulse width of the transmission pulse signal, and inputs the output signal of the gate circuit through a distributor, a first frequency converter that converts the output signal of the gate circuit to a transmission frequency using a signal from a local signal generator; a power amplifier that power amplifies the output of the first frequency converter; a transmitting/receiving switch that switches the received signal; an antenna that emits the transmitted signal and receives the received signal; a second frequency converter that receives the signal from the local signal generator and converts the frequency of the received signal; an IF amplifier that amplifies the output of the frequency converter; a second DDL whose chirp direction is down chirp for pulse-compressing the received signal amplified by this IF amplifier;
a detector that detects the output of the DDL and converts it into a video signal; a signal processor that receives the video signal and performs signal processing; and inputs the output signal of the gate circuit to the first frequency conversion circuit; for
A radar device comprising a distributor for inputting an IF signal to the IF amplifier or the second DDL.
JP62072271A 1987-03-26 1987-03-26 Radar equipment Granted JPS63238483A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62072271A JPS63238483A (en) 1987-03-26 1987-03-26 Radar equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62072271A JPS63238483A (en) 1987-03-26 1987-03-26 Radar equipment

Publications (2)

Publication Number Publication Date
JPS63238483A JPS63238483A (en) 1988-10-04
JPH0531945B2 true JPH0531945B2 (en) 1993-05-13

Family

ID=13484450

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62072271A Granted JPS63238483A (en) 1987-03-26 1987-03-26 Radar equipment

Country Status (1)

Country Link
JP (1) JPS63238483A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0825613A (en) * 1994-07-12 1996-01-30 Shinei Kiko Kk Paint supplying device of pad printing machine for ceramics

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11067666B2 (en) * 2018-05-29 2021-07-20 The Boeing Company Self-compensating radar system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0825613A (en) * 1994-07-12 1996-01-30 Shinei Kiko Kk Paint supplying device of pad printing machine for ceramics

Also Published As

Publication number Publication date
JPS63238483A (en) 1988-10-04

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