JPH0531820B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for forming contact holes necessary for wiring aluminum or the like in a stepped portion in a semiconductor manufacturing process.

[Conventional technology]

Conventionally, there is a method shown in FIG. 2 as this type of forming method. In the figure, 1 is a semiconductor substrate, 2 is an ion implantation region implanted with ions of the opposite conductivity type to the substrate 1, 3 is a gate oxide film, 4 is a gate electrode, and 5 is a gate electrode.
PSG ( Phosphorous Silicate Glass ), 6
Resist for flattening the PSG step, 7
This is a patterning resist for forming contact holes in PSG.

Next, the contact hole formation process will be explained with reference to FIG. A gate oxide film 3, a gate electrode 4, and an ion implantation region 2 are formed on a semiconductor substrate 1, and PSG 5 is deposited. Furthermore, in order to flatten the resulting step difference, a thick resist 6 is applied. Next, the PSG 5 is flattened by RIE (Reactive Ion Etching ) using hydrofluoric acid gas and oxygen gas, a patterning resist 7 is applied, and patterning is performed by photolithography. Using the patterned resist 7 as a mask, a contact hole is formed in the PSG 5 by RIE using a hydrofluoric acid gas.

[Problem that the invention seeks to solve]

Since the conventional contact hole forming method is as described above, the high portion of the stepped portion is overetched by the RIE performed when forming the contact hole in the PSG 5. for that,
There is a possibility that the gate electrode 4 is etched unnecessarily, and furthermore, the etching may penetrate through the gate electrode. After forming a contact hole in this state,
If the wiring is made of aluminum, sufficient contact cannot be made between the aluminum and the gate electrode 4, resulting in a serious defect in the operation of the semiconductor device.

This invention was made to solve the above-mentioned problems, and it is possible to flatten the insulating film and prevent over-etching when forming contact holes in areas with high steps. The object of the present invention is to provide a contact hole forming method that allows stable contact between a wiring layer and a gate electrode 4.

[Means for solving problems]

The method for manufacturing a semiconductor device according to the present invention includes a step of forming a conductive layer 4 on a semiconductor substrate 1, a step of forming an insulating film 5 on the semiconductor substrate having a step portion formed by the conductive layer, and a step of forming a conductive layer 4 on the insulating film. The first surface is flat.
Step 8 of forming a layer, selectively etching the first layer and the insulating film to form a contact hole at least on the conductive layer, and forming a second layer with a flat surface on the insulating film by filling the contact hole. 8, a step of etching the second layer and the insulating film to planarize the insulating film, and a step of removing the second layer filled in the contact hole of the insulating film.

[Effect]

When forming a contact hole, the insulating film has approximately the same thickness at the top and bottom of the step, so that etching proceeds in the same manner and no overetching occurs.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is a semiconductor substrate, 2 is an ion implantation region implanted with ions of the opposite conductivity type to the substrate 1, 3 is a gate oxide film, 4 is a gate electrode, and 5 is a gate electrode.
PSG, and these are similar to those shown in FIG. 8 is a thick polymer material (polymer) for flattening the steps of PSG, 9 is an inorganic thin film layer,
10 is a patterning resist for forming contact holes in PSG.

Next, the process of forming contact holes will be explained with reference to FIG. A gate oxide film 3, a gate electrode 4, and an ion implantation region 2 are formed on a semiconductor substrate 1, and PSG 5 is deposited. Next, a thick polymer 8 is applied to flatten the resulting step difference in the PSG 5, and then an inorganic thin film layer 9 and a resist 10 for patterning contact holes are applied (FIG. 1a). The resist 10 is patterned by photolithography (FIG. 1b), and the inorganic thin film layer 9 is patterned by RIE using hydrofluoric acid gas using the patterned resist 10 as a mask (FIG. 1c). Furthermore, using this patterned inorganic thin film layer 9 as a mask, the thick polymer 8 is patterned by RIE using oxygen gas (FIG. 1d). RIE using hydrofluoric acid gas using patterned polymer 8 as a mask
A contact hole is formed in the PSG 5 by (Fig. 1e). At this time, since the film thickness of PSG5 is the same in both the high and low parts of the step,
Over-etching of the gate electrode through the PSG can be prevented.

Next, the polymer 8 is thermally flowed and flattened by re-baking (FIG. 1f). Next, the PSG 5 is flattened by RIE using hydrofluoric acid gas and oxygen gas (Fig. 1g), and finally the polymer 8 buried in the contact hole is removed by plasma using oxygen gas (Fig. 1). h).
In this way, the PSG 5 can be planarized and contact holes can be formed without overetching.

The above embodiment is an example of a process for forming a contact hole at a step between a gate electrode (word line) and an ion implantation region in a MOS type semiconductor manufacturing process. Needless to say, the present invention can also be applied as a process for forming contact holes in various stepped portions in a bipolar semiconductor manufacturing process.

〔Effect of the invention〕

As described above, according to the present invention, since the insulating film is flattened after forming a contact hole in the insulating film such as PSG, over-etching that penetrates the insulating film at the high part of the stepped portion is prevented. This has the effect of making it possible to obtain stable contact between a wiring layer such as aluminum and various step portions such as a lower conductive layer such as a gate electrode, a cell plate, or an ion-implanted region of a source/drain.

[Brief explanation of the drawing]

FIG. 1 is a process sectional view showing an embodiment of the present invention;
FIG. 2 is a process sectional view showing a conventional example. 1...Semiconductor substrate, 2...Ion implantation region, 3
...Gate oxide film, 4...Gate electrode, 5...
PSG (insulating film), 8... Thick polymer for flattening the stepped portion, 9... Inorganic thin film layer, 10... Resist for patterning by photolithography.

Claims (1)

[Claims] 1. A step of forming a conductive layer on a semiconductor substrate, a step of forming an insulating film on the semiconductor substrate having a stepped portion due to the conductive layer, and a step of forming a layer with a flat surface on the insulating film. a step of forming a first layer, a step of selectively etching this first layer and the insulating film to form a contact hole at least on the conductive layer, and a step of filling the contact hole to form a flat surface on the insulating film. A semiconductor device comprising at least the steps of forming a second layer, etching the second layer and the insulating film to planarize the insulating film, and removing the second layer buried in the contact hole of the insulating film. Method of manufacturing the device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the second layer is formed by coating a polymer material on the insulating film, and the surface thereof is flattened by thermal flow. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the etching in the step of planarizing the insulating film is anisotropic etching.