JPH0531593Y2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to an automobile watch, and more particularly to a brightness adjustment circuit for an electronic timepiece with a light emitting display that is attached to an instrument panel of an automobile.

(Prior art) Today, electronic timepieces with luminescent displays reduce the luminous brightness of the time display when the surroundings become dark and the lamps on the instrument panel are turned on. There are devices that allow adjustment of the luminance and luminance of the time display, thereby making the displayed time easier to see and preventing the driver's eyes from getting tired.

For this brightness adjustment, means is used to change the duty ratio of a control signal that drives the display element in the time display section to emit light, and this means includes:
By providing a dimming oscillation circuit with a constant frequency and adjusting the pulse width, and using the output signal of the dimming oscillation circuit as a lighting signal for the instrument panel, the time display section of the instrument panel and other lights can be used. This allows the brightness of each meter lamp to be adjusted. (For example, Utsukai Showa 56-16089
issue).

In order to reduce the luminance of the time display section in conjunction with the lighting of the lights on the instrument panel, a normal pulse-shaped By superimposing a frequency-divided signal with a short period from a clock circuit on the light lighting signal (FIG. 3, d and d'), the duty ratio is reduced and the luminance is lowered to a certain level.

(Problems to be Solved by the Invention) Dimming that harmonizes the brightness of the instrument panel lamp with the brightness of the time display and that varies the pulse width in order to adjust the brightness of the instrument panel lamp and the time display. An automobile watch equipped with an oscillation circuit reduces the average current value by narrowing the pulse width, which determines the brightness of the instrument panel lamp and also determines the brightness of the time display in the automobile watch. Although the brightness of the display element in the time display is reduced when the instrument panel lamp is lit, the brightness of the time display pulsates when the instrument panel lamp is lit, and this slight change in brightness may cause the display to appear to waver. The displayed time was difficult to read, which caused driver fatigue.

The reason why the brightness of the time display section fluctuates is due to the discrepancy between the pulse period of the lighting signal output from the dimming oscillation circuit and the pulse period of the superimposed signal, which is a pulse signal extracted from the clock circuit. This causes interference with the superimposed signal, and due to the slight synchronization difference between the pulse signal in the clock circuit and the pulse signal output from the dimming oscillation circuit, the duty ratio of the brightness signal changes, causing This is thought to be because the average current value of the luminance signal pulsates.

(Means for solving the problem) A clock circuit that measures time and a pulse signal with a duty ratio set by external operation when the instrument panel lamp lighting switch is turned on are output as lamp lighting signals. An automobile clock comprising a dimming oscillation circuit and a time display section that displays the time based on a time signal from the clock circuit and whose luminous brightness is controlled by a duty ratio of the lamp lighting signal, an inverter that inverts the lamp lighting signal; a pulse generator that outputs a first pulse signal having a shorter period than the lamp lighting signal; and a second pulse signal having an even shorter period than the first pulse signal; a first preset circuit that outputs a first load signal and a reset signal in synchronization with the generation of the pulse signal when the lighting signal is a pulse signal; and a first preset circuit that up-counts the first pulse signal until the count value becomes a full count value. an up counter that outputs a full count signal when a load signal is generated and whose count value is cleared in response to the generation of the first reset signal; a down counter that loads and counts down its count value using the second pulse signal and outputs a borrow signal when the count value reaches "0"; a gate circuit that supplies an inverted lamp lighting signal to the time display section; a detection holding circuit that detects generation of a full count signal from the up counter and holds the lamp lighting signal until a pulse is generated; A second load signal that loads the count value of the up counter into the down counter only when the up counter reaches a certain count value smaller than the full count value and the up counter is activated only when a detection signal of the holding circuit is generated. a second preset circuit that outputs a second reset signal to be cleared; and a second preset circuit that outputs a second reset signal to be cleared; and a pulse non-generating period of the lamp lighting signal is counted by the pulse signal from the pulse generator, and when the count value is equal to or greater than a certain value, the time display is and a high-intensity signal output circuit that supplies a 100% duty lamp lighting signal to the section.

(Embodiment) FIG. 1 is a circuit diagram according to an embodiment of the present invention, and FIGS. 2 and 3 are time charts thereof. In the figure, 2 is a pulse generation circuit, which includes an oscillator 4. This frequency dividing circuit 6 is included. The frequency divided output Q ₃ of this frequency dividing circuit 6 is the first pulse signal φ ₁ (approximately
5KHz), the output Q ₂ is the second pulse signal φ ₂ (approx.
20KHz), the output Q ₁ is the third pulse signal φ ₃ (approx.
40KHz) is being output. These outputs φ ₂ and φ ₃ are input to a switching gate consisting of AND gates 8 and 10 and an OR gate 12, and depending on the opening and closing of SW1 and SW2 connected to this switching gate, one of the signals is output from the OR gate 12. Output.

On the other hand, 14 is an instrument panel lamp lighting switch, and when this switch 14 is off, the output signal of the dimming oscillation circuit 16 becomes "H". This "H"
The signal is input to the reset input R of the counter 24 in the high brightness signal output circuit 20 via the inverter 18, so the counter 24 is reset and input to the clock input φ via the AND gate 22. It becomes possible to count the output signals from. After a certain period of time after starting this count, the output _Qo of the counter 24 becomes H level,
AND gate 22 is closed. For this reason, the output _Qo of the counter 22 remains "H" until it is reset.
This "H" signal is sent to the clock circuit 28 via the OR gate 26 as a luminance signal.
input to the time display section 30 connected to. At this time, the duty of the luminance signal is 100%, and the luminance of the time display section 30 is maximum.

When the switch 14 is turned on here, the output signal of the dimming oscillation circuit 16 becomes a pulse signal, and the duty ratio of this pulse signal can be varied by the variable resistor 32. At this time, the output signal A of the inverter 18 becomes an inverted pulse signal as shown in FIG. This pulse signal is used by the down counter 3.
4 is input to AND gate 36. The AND gate 36 also receives the borrow signal H of the counter 38 and the signal φ ₂ or φ ₃ from the OR gate 12 . Since the borrow signal H is "L" at this time, the signal φ ₂ or φ ₃ can be input to the counter 38 only when the output signal A becomes “H”.

On the other hand, the up counter 40 counts the first pulse signal _φ1 . Further, the counter 44 in the first preset circuit 42 detects that the output signal A is "L".
When this happens, the reset is released, the first pulse signal φ ₁ is counted, and the output Q ₁ and then Q ₂ become “H” in that order. This "H" signal of output _Q1 is the first
The count value of the up counter 40 is loaded into the counter 38 as the load signal I. Thereafter, when the "H" signal of the output _Q2 is outputted as the first reset signal J, the up counter 40 and the frequency dividing circuit 6 are reset. For this reason, the up counter 4
0 is 0, and the counter 44 stops as it is. After that, when the output signal A becomes "H", the counter 4
4 is reset and the output _Q2 returns to "L", so the frequency divider circuit 6 and up counter 40 start operating again, and when the output signal A falls to "L", the first load signal I returns to "L". Then, a reset signal J is generated and the above-described operation is repeated. As a result, the up counter 40 counts the first pulse signal φ ₁ for the period during which the output signal A is “H” and loads the count value into the counter 38 .

When the output signal A becomes "H" after being loaded into the counter 38, the counter 38 counts down the loaded count value by the signal φ ₂ or φ ₃ from the AND gate 38. At this time, the output φ ₂ has a period of 1/4 of φ ₁ , and the output φ ₃ has a period of 1/8, so the time for the count value to count up to 0 is 1/4 for the signal φ ₂ , φ In case of ₃ , it will take 1/8. When this count value reaches 0, the borrow signal H rises to "H" and the AND gate 36
Close and stop counting. The output signal K of the gate circuit 48 to which the inverted signal of the borrow signal H and the output signal A are input is "H" only during the period when the output signal A is "H" and the borrow signal H is "L", that is, the counter 38 is counting. This signal is supplied to the time display unit 30 as a luminance signal.

When the instrument panel lamp is turned on in this manner, the lighting signal becomes pulse-like, so the display brightness decreases. Furthermore, since only the signal from the pulse generation circuit 2 is used as the signal that determines the duty ratio, each signal is synchronized, so that the display brightness does not fluctuate like a beat and flicker.

FIG. 3 is a time chart showing the operation when the variable resistor 32 is adjusted to make the pulse non-generating state, that is, the signal A is in the "H" state.

In this case, since the output signal A is "H", the counters 24 and 44 are reset, and the high brightness signal, the first load signal I, and the reset signal J are not generated. Therefore, the up counter 40 is always counted, and when the count value reaches the full count state, that is, the output Q ₁ ~
A load signal and a reset signal are output in response to the fall of the output _Q8 when all _Q8 go to "H" and then return to "L". Then, by this signal, the full count value of the up counter 40 is loaded into the down counter 34, and if this is down counted by the signal φ ₂ or φ ₃ , the gate circuit 48
If the signal φ ₂ is the output signal K, the duty ratio is 25.
%, if the signal _φ3 , a luminance signal with a duty ratio of 12.5% can be obtained. However, the up counter 40 is 8.
This brightness signal is 5KHz/ ₂₈ ≒20Hz
It will have a frequency signal of . At this frequency, it appears as flickering to the human eye.

In the present invention, in order to prevent such flickering, the full count signal C of the up counter 40 is
A detection holding circuit 50 holds the detection signal until a pulse signal is generated in the output signal A when the occurrence of the detection signal A is detected, and an up counter 40 outputs a constant count value smaller than the full count value only when this detection signal is held. A second preset circuit 52 is added that outputs a second load signal for loading the count value of the up counter 40 into the down counter 34 and a second reset signal for resetting the up counter 40 and the frequency dividing circuit 6 when the up counter 40 reaches the down counter 34. did.

In this embodiment, the detection holding circuit 50 sets its output Q to "H" in synchronization with the fall of the output _Q8 as the full count signal C, and is reset in synchronization with the output signal A becoming "L". Consists of FF54. Further, the second preset circuit 52 combines the output Q signal of the FF 54 with the up counter 40.
an AND gate 56 into which the outputs _Q4 to _Q7 of
The AND gate 58 receives the output signal E of the AND gate 56 and the output _Q1 of the up counter 40.
, an OR gate 60 to which the output signal F of the AND gate 58 and the first load signal I are input, an AND gate 62 to which the output signal E and the output _Q2 of the up counter 40 are input;
The output signal G and the first reset signal J are input to an OR gate 64.

Therefore, when the output signal A remains in the "H" state for a certain period of time or more, the output _Q8 of the up counter 40
is in full count state and its output _Q8 falls. In synchronization with this falling edge, the output Q of FF54
becomes "H", and the output from the subsequent count
Due to the simultaneous output of "H" signals from _Q4 to _Q7 , the output signal E of the AND gate 56 becomes "H" and the AND gates 58 and 62 are opened. After this, output Q ₁ becomes “H”
Then, the output signal F of the AND gate 58 as the second load signal also becomes "H", and thereby the count value of the up counter 40 is loaded into the counter 38. Further, as the output Q ₂ becomes "H" after this, the output signal G of the AND gate 62 as the second reset signal becomes "H", and the frequency dividing circuit 6 and up counter 40 are temporarily reset. , start counting again from the beginning.

On the other hand, the down counter 38 loaded with the count value of the up counter 40 performs down counting by the signal φ ₂ or φ ₃ until the borrow signal H becomes “H”. Then, a signal that becomes "H" only during the period when the counter 38 is counting appears as a luminance signal in the gate circuit 48. Since this loaded count value is when the output _Q7 becomes "H", it is about 1/2 of the full count value, and the frequency of the luminance signal becomes about 40 Hz, which is about twice the previous frequency, and flickering disappears.

Furthermore, if the oscillator 4 is configured with a CR oscillator or the like, the oscillation frequency will change by nearly ±20% due to temperature changes, but even in this case, the lowest frequency of the luminance signal will only drop to about 30Hz, which is not noticeable to the human eye. I don't feel any flickering.

(Effects of the invention) As described above, according to the invention, there is no flickering caused by the synchronization difference between the clock signal and the pulse signal for lighting the light, or flickering when the brightness is set to the minimum, as in the past, and it is possible to The luminance of the clock display can be changed to match the luminance of the lamp.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an automobile watch according to an embodiment of the present invention. 2 and 3 are time charts showing the operation of the circuit shown in FIG. 1. 2... Pulse generator, 16... Dimming oscillation circuit, 20... High brightness signal output circuit, 28... Clock circuit, 30... Time display section, 34... Down counter, 40... Up counter, 42...first preset circuit, 50...detection holding circuit, 52...
Second preset circuit.

Claims (1)

[Claim for Utility Model Registration] A clock circuit that measures time and a dimming device that outputs a pulse signal with a duty ratio set by external operation as a lamp lighting signal when the instrument panel lamp lighting switch is turned on. and a time display section that displays the time based on a time signal from the clock circuit and whose light emission brightness is controlled by the duty ratio of the lamp lighting signal, comprising: an inverter that inverts a lighting signal; a pulse generator that outputs a first pulse signal having a shorter period than the lamp lighting signal; and a second pulse signal having an even shorter period than the first pulse signal; and the lamp lighting signal. a first preset circuit that outputs a first load signal and a reset signal in synchronization with the generation of a pulse signal when the pulse signal is a pulse signal; and a first preset circuit that up-counts the first pulse signal and when the count value reaches a full count value. an up counter that outputs a full count signal to the counter and whose count value is cleared in response to the generation of the first reset signal; and a count value of the up counter that is loaded in response to the generation of the first load signal. a down counter that counts down its count value using the second pulse signal and outputs a borrow signal when the count value reaches "0"; a gate circuit that supplies the lamp lighting signal to the time display section; a detection and holding circuit that detects generation of a full count signal from the up counter and holds the lamp lighting signal until a pulse is generated; and this detection and holding circuit. a second load signal that loads the count value of the up counter into the down counter when the up counter reaches a certain count value smaller than the full count value; and a second load signal that clears the up counter. a second preset circuit that outputs a second reset signal; and a second preset circuit that outputs a second reset signal; and a second preset circuit that outputs a second reset signal; An automobile clock comprising: a high-intensity signal output circuit that supplies a 100% lamp lighting signal;