JPH05313893A - Arithmetic bypassing circuit - Google Patents

Abstract

PURPOSE:To bypass arithmetic results at a high speed when processing time at an operation stage is short, for example, when executing an operation instruction with '0' relating to the arithmetic bypassing circuit in a pipeline processing computer provided with a function guaranteeing a data-dependence relation. CONSTITUTION:The circuit is provided with a means for suppressing the interlock of a D stage and validating the interlock of an E stage when the data dependence relation is present between a preceding instruction and a succeeding instruction and the succeeding operation instruction with '0' is detected, the means for detecting timing for bypassing the data of the preceding instruction and a circuit for detecting '0' of the load data of the preceding instruction. The operation instruction with '0' is supplied to the D stage, the next E stage is interlocked, the load data of the preceding instruction is bypassed by the bypass control signal of the bypass timing detection means just prior to a W stage and thereafter the condition code of the operation instruction with '0' is set in a condition code register (CC) based on the decision signal of the '0' detection circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operation bypass circuit in a pipeline processing computer having a function of guaranteeing data dependency.

A cache memory is used in order to increase the processing speed of a computer, and particularly to increase the average speed of memory access. FIG. 9 is a diagram showing the basic configuration of the cache memory. One of the options when configuring the cache memory (CACHE) is the number of ways (WAY). this is,
Holds the data for any address
The number of cache memory entries that can be (cached). Generally, 2-way-set-associative, 4-way-set-associative, all-set-associative, direct-mapping, etc. are often adopted. ..

It is generally known that if the cache memories have the same capacity, the hit rate is improved and the performance is improved by increasing the number of ways. However, when the number of ways (WAY) becomes large, when reading the cache memory, it is necessary to select the target data from more elements that may be held, so the increase in hardware, and However, this leads to an increase in delay time.

Here, one configuration and processing when a cache memory is adopted will be described with reference to FIG. The cache memory 15 has a data memory that holds data.
150 and the tag memory 151 used for hit judgment
And a decision circuit for making a hit decision 152 {selecting way (W
AY)} and a way selection circuit 153 that selects data (WAY select) according to the result of the hit judgment. If there is target data in any way (WAY), hit judgment is made. The cached data is read along with the signal.

As shown in this figure, if all sets are associative, the outputs of the data memory 150 and the tag memory 151 can be expected to be very large. Therefore, in general, like the whole set-associative, the way (W
AY) Use associative memory for large numbers.

As can be seen from this figure, generally, in the cache memory 15, the path that requires the largest propagation time is searched from the address holding circuit 155 to the tag memory 151 to determine the hit (WAY). , Way (WAY) is selected and the path to output data.

FIGS. 10 and 11 are views showing the concept of a pipeline computer including a cache memory. Although two general-purpose registers (GR) 11 are shown in this figure, there is only one. The general-purpose register (GR) 11 is used for reading the source operand in the decode stage (D) and used for writing the operation result in the write stage (W).

In the figure, the processing of the cache memory 15 is performed in one stage (C). Also, as shown in this figure,
The times required for the D, E, C, and W stages are not necessarily the same.

The most time consuming stage determines the cycle time of this pipeline. Conventionally, the C stage requires a large amount of time and has been a factor that determines the cycle time of the pipeline.

Further, in recent years, since the speed of the logic circuit portion has been increased, the C stage may be divided into two to shorten the cycle time of the pipeline. FIG. 11 shows the processing of the cache memory 15 shown in FIG. 10 divided into two stages (C1, C2). In the C1 stage, data memory (DATA) 150, tag memory (TAG) 15
Refer to 1 and judge the hit (HIT) and the way (WAY) select (way-sel) at the C2 stage.

FIG. 12 is a diagram showing an operation bypass in a conventional pipeline computer. That is, in the pipeline computer having the stages D, E, C1, C2, W as shown in FIG. 11, the operation bypass when the data read from the cache memory 15 is used in the subsequent operation instruction. Is shown.

Even if such an arithmetic bypass technique is used, when there is a data dependency relationship, that is, register interference between the preceding instruction and the succeeding instruction, the interlocking means 20, 21 shown in the figure cause The subsequent instruction is interlocked in the D stage, and is waited for 2τ before data is obtained.

In such a pipeline computer, due to the data dependency, the pipeline is stopped and the performance is degraded. 2. Description of the Related Art In recent years, in order to speed up the processing in a computer, a technology of parallel execution of instructions, which is represented by, for example, a super color system and a very long instruction word (VLIW) system, has been put into practical use.

The super color system is a main memory device.
The instruction on (MSU) is arranged for one instruction like an ordinary computer, but at the stage of reading and executing the instruction, the instruction is scheduled for two instructions and the instructions are executed in parallel. In the computer system, an instruction register, a decoder, an arithmetic unit (A
LU) and the like are implemented in parallel, but since only one cache memory 15 is provided, a load instruction or the like is scheduled as one instruction.

In a very long instruction word (VLIW) system, when compiling a source program written in a high-level language, for example, every two instructions are scheduled to execute instructions (operations) in parallel. Also in this case, the load instruction and the like are scheduled as one instruction.

By executing the instructions in parallel in this way, the execution timings of the preceding instruction and the succeeding instruction having the above-mentioned data dependency are close to each other, and
Since the rate of decrease in performance due to the suspension of the pipeline due to the data dependency is large, a circuit capable of effective operation bypass is required for the operation bypass processing when there is the data dependency.

[0017]

2. Description of the Related Art FIG. 12 described above is a diagram showing an arithmetic bypass in a conventional pipeline computer, and FIG. 13 is a diagram explaining a problem of a conventional arithmetic bypass circuit.
FIG. 13A shows a subroutine of a string copy function which is often used in a source program written in C language in a pseudo assembler language, and FIG. 13B shows
The execution state of the string copy function is shown.

In the pseudo assembler language shown in FIG. 13 (a), the operations described side by side are executed in parallel at one time. FIG. 13B shows the execution state of the string copy function, and the portion indicated by the first broken line is the data dependency relationship between the preceding instruction and the succeeding instruction as described in FIG. 12 above. That is, the pipeline is interlocked by the conventional interlock mechanism when there is so-called register interference, and in this example, in the comparison instruction (CMP), the preceding load (LD) Instruction-based cache memory 1
Waiting for data to be read from 5, there is a waiting time of 2τ.

The portion indicated by the second broken line is a branch instruction (BN
To execute E) and read the branch destination, the result of the preceding comparison instruction (CMP) is the comparison instruction (CMP).
The branch instruction (BNE) refers to the condition code set in the condition register (CC) at the W stage of
This is an interlock that occurs when the instruction at the branch destination address generated in the E stage is read.

[0020]

This waiting time can be eliminated by performing the read-ahead by using, for example, a well-known branch prediction mechanism. In this case, the loop portion of the string copy function can be executed by 6τ → 5τ shown in FIG. If there is no waiting for reading the cache memory 15, the loop part of the string copy function can be executed in 3τ.

In other words, in the loop portion of the string copy function, waiting for the reading of the cache memory causes a decrease in performance of up to 40%. Therefore, the conventional operation bypass circuit has a problem that when the data read from the cache memory is used as an operand, there is a waiting time and the hardware performance cannot be maximized.

In view of the above-mentioned conventional drawbacks, the present invention is a pipeline processing computer having a function of guaranteeing data dependency, and a read stage (C1) of a cache memory.
When the cache hit determination stage (C2) is independent, when the subsequent instruction immediately uses the data read from the cache memory, aggressive bypass processing is performed at a faster timing. By sending the read data to the subsequent instruction, the performance of the pipeline computer is improved, and for the processing performed in the arithmetic stage, for example, "0" is added and "0" is added to the normal arithmetic processing that requires an arithmetic time. By providing a dedicated arithmetic circuit like the arithmetic with "0" such as "comparison with", the arithmetic time can be shortened, and there is a processing with a short arithmetic processing time,
If the arithmetic processing can be shortened, paying attention to the fact that even if the input data is input at a late timing, a sufficient result can be obtained even in the same arithmetic cycle. It is an object of the present invention to provide an arithmetic bypass circuit capable of bypassing the arithmetic result of a preceding instruction when executing an instruction at high speed.

[0023]

FIG. 1 is a block diagram showing the principle of the present invention. The above problem is solved by the bypass arithmetic circuit configured as follows.

At least the decode stage (D), the operation stage (E), and the operand fetch stage (C1, C
2) and the write stage (W), detect the data dependency between the instruction to be executed first and the instruction to be executed subsequently, and interlock the D stage or E stage. Means 20 to 22, a register write of the preceding instruction to be executed, or an operation bypass means for bypassing operation data to a subsequent instruction at a timing immediately before the register write, and a condition code generated by the operation result. A pipeline processing computer having a generation circuit 32 and means for decoding an instruction and detecting that the instruction is an “arithmetic operation with“ 0 ”” 4
When 0 and the "operation with" 0 "" instruction are detected, the D stage interlock means 22 suppresses the D stage interlock, and the E stage interlock means 22 controls the E stage. Interlock control means 20a, 22a for enabling the interlock, means 23 for detecting the timing to bypass the data of the preceding instruction, a "0" detection circuit 50 for the load data of the preceding instruction, and "0" for the load data. The "0" judgment signal of the "detection circuit 50", the "condition code generation circuit" 31 for generating the condition code by inputting the sign bit of the load data, and the condition code generation circuit 32 are generated by a normal operation. The condition code to be input and the condition code generated by the above-mentioned “condition code generation circuit” 31 are input and a “condition code selection circuit” 30 for selecting one of them is provided and executed. When the instruction is an "arithmetic operation with" 0 "" and a "data dependency" is detected with the preceding instruction, the "arithmetic operation with" 0 "instruction is interlock-controlled. Means 2
At 0a and 22a, the interlock of the D stage is suppressed, the interlock is performed at the next E stage, and the load data of the preceding instruction is used as the bypass control signal of the bypass timing detection means 23 immediately before the W stage. Based on the above, after bypassing to the operation stage (E) of the “operation with“ 0 ”” instruction, the determination signal is sent to the above-mentioned “0” detection circuit (50) without performing the operation with the “0”. The "condition code selection circuit" 31 is used to select and set the condition code register (CC) of the operation result of the "operation with" 0 "" instruction.

[0025]

That is, in the present invention, it is noted that the comparison operation with "0" can be realized at high speed by providing a dedicated "0" detection circuit. After selecting the way (WAY), without using the arithmetic unit (ALU) used in the general comparison instruction, perform the "0" comparison by the dedicated "0" detection circuit, and the condition code of the comparison instruction. To reduce the subsequent latency.

Further, in the present invention, when the interlock is applied in the D stage, the interlock due to the data dependency relationship is noticed, focusing on the fact that the subsequent instruction is delayed in the pipeline and the processing is delayed. Is performed at a stage as late as possible, for example, the E stage, so that the interlock of the D stage, which has been performed in the conventional pipeline computer of the subsequent instruction “0” comparison instruction, is suppressed.
By interlocking on the stage, the "0"
It is possible to speed up the start of processing of the comparison instruction and speed up the injection of the instruction following the “0” comparison instruction into the pipeline.

The outline of the processing in each stage will be described below. First, an instruction decode stage (D): an instruction is decoded to detect that it is a "comparison with" 0 "" instruction, and it is input to a pipeline tag (not shown) (see FIG. 11).

In many computers, the 0th general-purpose register is the 0 register (the read data is always "0" regardless of the written value),
The “comparison with“ 0 ”” is performed by comparing with the 0th register.

Also, in the comparison instruction, the write destination of the result of the subtraction instruction is often substituted with the subtraction instruction designating the 0th register. Therefore, the instruction decoder simply decodes the instruction and decodes, for example, that all of the operands 2 are “0”, without checking the value of the operand read from the register. The "compare with 0""instruction can be detected. The detected result is held in the pipeline tag and used in a predetermined stage.

Operation stage (E): The above-mentioned hit judgment / way (WAY) selection stage (C) of the preceding load (LD) instruction
It is detected from the tag set in the D stage and flowing in the pipeline tag that the data processed in 1) is the data to be compared with "0", and in that case, the way (WAY) is selected. The converted data is converted into the special “0” of the present invention.
When it is “0” by inputting to the detection circuit and judging “0”, the prepared fixed pattern (condition code) is used as a flag to set the condition code (CC) flag (Z = 0). If it is not "0", the prepared fixed pattern (condition code) is set as a flag in the condition code (CC) flag (Z = 1) in advance.

Write stage (W): Writes the flag obtained in the arithmetic stage (E) to the condition code register (CC). As described above, the comparison process with “0” is as follows.
In the program written in C language, it is very often used in the case of performing the character string detection processing for detecting the end of the character string. Therefore, the speeding up of the ““ 0 ”detection” command as described above is The pipeline computer has a great effect of contributing to speeding up the character string detection processing.

[0032]

Embodiments of the present invention will now be described in detail with reference to the drawings. The above-mentioned FIG. 1 is a principle configuration diagram of the present invention, and FIG.
FIG. 5 is a diagram showing an embodiment of the present invention, which is shown in FIG.
(A2) to (a2) show an example of the structure of the "detect" 0 "" command.
FIG. 4 shows a configuration example of "data dependency detection means" for detecting the data dependency between the preceding instruction and the subsequent instruction and generating an interlock signal, and FIG. 5 (a) shows an example of the format of the condition flag. FIG. 5B shows an example of the configuration in the case of generating the condition flag of the ““ 0 ”detection” instruction, and FIG. 6 is a diagram for explaining the effect of the present invention. 6A shows the state of conventional pipeline execution, FIG. 6B shows the state of pipeline execution by the arithmetic pipeline circuit of the present invention, and FIGS. 7 and 8 show other aspects of the present invention. FIG. 7 is a diagram showing an embodiment, FIG. 7 shows a configuration example of a scoreboard, and FIG. 8 shows a concept of operation bypass when a scoreboard is used.

According to the present invention, there is provided an operation bypass circuit in a pipeline processing computer having a function of guaranteeing a data dependency, at least a decode stage.
(D), operation stage (E), operand fetch stage (C1, C2), and write stage (W). Data dependency "(register interference)
Means for interlocking the D stage or the E stage, and when the "comparison with" 0 "" instruction is detected, the interlock of the D stage is suppressed, and E
Means for enabling stage interlock 22 20a-22
a and a load data "0" detection circuit 50 of the preceding instruction are provided, the operation instruction with the "0" is input to the D stage, the next E stage is interlocked, and the load data of the preceding instruction is loaded. Immediately before the W stage, after being bypassed to the E stage of the subsequent instruction, without performing the operation with the “0”, the “0” is determined based on the determination signal of the “0” detection circuit 50. The means for setting the condition code of the calculation result of is the means necessary for implementing the present invention. The same reference numerals denote the same objects throughout the drawings.

The configuration and operation of the arithmetic bypass circuit of the present invention will be described below with reference to FIGS. First, the instruction format of the pipeline computer related to the present invention forms, for example, the format shown in FIG. 2 (a1), and the "" 0 "comparison" instruction related to the present invention is
It has the bit configuration shown in FIG. 2 (a2).
The "0" comparison "instruction is a subtraction instruction (SUB, SUBi), and the read operand 2 is" 0 "and the write register number is" 0 ". Obviously, the D stage decoder
In (DEC), bits 0-16 are "0100 0000 0000 000
0 0 "or" 0 100 0000 0000 0000 1 "and bit 22 to
You just need to decode that 31 is "00 0000 0000".

Next, FIG. 3 shows an example of the configuration of the "data dependency relationship detection" circuit of the present invention. As is apparent from FIG. 3, the basic configuration of the “data dependency relationship detection” circuit is a write register of the preceding instruction by using the register number information of the pipeline tag of the preceding instruction E stage or C1 stage. Number (E-WR-REG-ID, C1-WR-REG-ID) and
Read register number (DR
If the D-REG-ID1,2) are equal and the read register is used (D-RD-REG-1-USED, D-RD-REG-2-USED), the subsequent instruction is It is configured to interlock at the D stage.

Specifically, the E stage and C1 stage in the pipeline tag are valid (EV
ALID, C1-VALID) and the preceding instruction are
The load instruction (E-LD-OP, C1-LD-OP) is required.

Further, in the present invention, the above interlock is applied when the subsequent instruction in the D stage is the above-mentioned "0" compare "instruction (D-CMP0-OP).
The interlock at the stage is suppressed, the "0" comparison "instruction (D-CMP0-OP) is input to the pipeline, and, for example, the interlock is performed at the E stage.

Therefore, in the present invention, in addition to the interlock mechanism described above, as shown in FIG. 4 (a), the E stage of the subsequent instruction and the C1 stage of the preceding instruction are also provided. An interlock circuit similar to the above is provided.

As shown in the figure, the interlock condition of this interlock circuit is such that the write register number (C1-WR-REG-ID) of the C1 stage of the preceding instruction and the read register of the E stage of the following instruction. Number (E-RD-REG-
ID1) is equal, and further, the preceding instruction of the C1 stage must be valid (C1-VALID), and the preceding instruction must be a load instruction (C1-LD-OP), Further, in the case of the present invention, the subsequent instruction is the "" 0 "compare" instruction (E
-CMP0-OP), configure to interlock.

By providing such an interlock mechanism, as shown in FIG. 1, the "0" comparison "is performed.
The instruction is input to the pipeline at the D stage, interlocked at the E stage, and preceded, for example, when the load instruction enters the C2 stage, the interlock is released and the operation of the present invention is performed. Bypass will be performed.

Next, a method of generating a condition code (CC) for the operation result when the "0" comparison "instruction is executed will be described. As shown in FIG. 1, in the present invention, the preceding C
The two-stage instruction is, for example, a load (LD) instruction, and the subsequent instruction executed in the E stage is the above “0” comparison ”instruction, and the write register number of the C2 stage load (LD) instruction is , If it is equal to the read register number of the “Compare“ 0 ”” instruction in the E stage,
The read data (the output of the way (WAY) selection circuit (way-sel) in the cache memory 15 of the load (LD) instruction is input to the dedicated “0” detection circuit 50 by bypassing the read data. A flag is created using the judgment result and the sign bit of the read data, and the flag register (CC)
Set to.

The condition of the bypass is that the subsequent instruction executed in the E stage is the "0" comparison "instruction, the preceding C2 stage instruction is the load (LD) instruction, and the C2 stage This means that the write register number of the load (LD) instruction is equal to the read register number of the "Compare" 0 "" instruction of the E stage.

An embodiment of this bypass control circuit (bypass timing detecting means) 23 is shown in FIG. 4 (b). As shown in the figure, the bypass condition of this bypass control circuit 23 is such that the write register number (C2-WR-REG-ID) of the C2 stage of the preceding instruction and the read register number (E of the E stage of the following instruction -RD-REG-ID) is the same, and the preceding instruction of the C2 stage is valid (C2-VA
In the LID), the preceding instruction must be a load-type instruction (C2-LD-OP), and in the case of the present invention, the subsequent instruction is the “0” comparison ”instruction ( If it is E-CMP0-OP), configure it to bypass (E-CMPO-BYPASS).

An example of the format of the condition flag is shown in FIG. 5 (a). The condition flag is composed of 3 bits, and in the case of a comparison instruction, it is defined as follows. ..
In FIG. 5 (a), Z flag: two operands (OP1, O
"1" when P2) are equal, and "0" otherwise.
And

N flag: Sign of the result of subtraction (most significant)
Set the bit. C flag: When the operand 1 (OP1) is smaller than the operand 2 (OP2), the value is "1" when the operand 1 (OP1) is smaller than the operand 2 (OP2) and is "0" otherwise.

Therefore, the "" 0 "comparison" relevant to the present invention.
When the operand 2 (OP2) is "0" like an instruction, the generation of the condition flag is simplified as follows. Z flag: "1" when operand 1 (OP1) is "0"
Otherwise, "0" N flag: The sign (most significant bit = MSB) bit of the operand 1 (OP1) is set.

C flag: Always set to "0". Therefore,
The "0" detection circuit 50 for the "0" comparison "command is as shown in FIG. 5 (b). However, since the condition code of the operation result is set in the flag register (CC), the condition shown in FIG.
As shown in FIG.
The selector (SEL) 30 sets the set value from 0 and the set value of the flag from the arithmetic circuit to the bypass control signal (output signal of the bypass control circuit 23) shown in FIG. 4 (b).
It is necessary to select with (E-CMPO-BYPASS).

6A and 6B are views for explaining the effect of the present invention. FIG. 6A shows a state of conventional pipeline execution, and FIG. 6B shows an operation pipeline circuit of the present invention. The state of pipeline execution is shown.

As described above, FIG. 6 shows an operation time chart in the case where the parallel processing which is often performed in the pipeline computer is already adopted. The program example shown in this figure is an example of the above-mentioned string copy function that is often used in a program written in C language.

For comparison, FIG. 6 (a) shows an example of a case where a conventional operation bypass circuit is used, and the following "0" comparison "instruction is executed until the C2 stage of the preceding load (LD) instruction. (SUBi instruction) waits for the load data by the preceding load (LD) instruction and interlocks with the D stage, so at least 5 cycles are required for one loop.

Therefore, in the case of the present invention, the preceding load
At the C2 stage of the (LD) instruction, the flag of the subsequent “0” comparison instruction (SUBi instruction) can be generated, so that one loop has 4 cycles, and the character string handled by the string copy function is long. Is about 20% faster.

In the above embodiment, the preceding load (L
D) For the instruction only, the explanation has been given with the example of accelerating the subsequent "" 0 "comparison" instruction, but the invention is not limited to this.
Similar to the load (LD) instruction, for example, an instruction in which data is output in the fourth stage, and an instruction (instruction X that has a small delay time with respect to the machine cycle) for the operation in the final stage It is clear that the subsequent "" 0 "compare" instruction can be speeded up as well.

Particularly, when the instruction X uses the same register write port (Y) as the load (LD) instruction,
It suffices to compare the write register number of the C2 stage for the port (Y) of the register with the read number of the E stage of the subsequent instruction, decode the instruction X, and output the result of the instruction X to the dedicated By selecting by the detection circuit and selecting the sign bit (most significant bit) of the result of the instruction X,
The condition code for the instruction X can be set in the flag register (CC), and the subsequent instruction can be speeded up.

The above instruction X is generally the above load.
It cannot always be executed in the same number of cycles as the (LD) instruction. The simplest extension of the above discussion is that in the Cn stage, in order for the subsequent instruction to bypass the operation result, the subsequent instruction must interlock in the E stage until the Cn-1 stage. That is, the read register number of the E stage of the succeeding instruction and the write register numbers of all the stages from the C1 stage to the Cn-1 (n ≧ 2) stage of the preceding instruction are used by using the information of the pipeline tag. You should make a comparison.

The condition "E-CMP0-BYPASS" for controlling the bypass of the operation result is that the read register number of the E stage of the "compare" 0 "" instruction and the C of the preceding instruction.
It suffices to compare it with the tag of the write register number of the n-1 stage.

However, in this method, when n becomes large, the number of the comparison circuits becomes large, which is not realistic. Therefore, in the present invention, it is considered to solve this problem by using a known scoreboard technique.

FIG. 7 illustrates the concept of the scoreboard. The scoreboard is a method for efficiently managing resources such as registers and arithmetic units. When the subsequent instruction waits for the completion of the writing of the preceding instruction to the register (that is,
An example of a case where a register writing interlock) is realized by using the scoreboard technique will be described below with reference to FIGS. 7 and 8.

The example of FIG. 7 shows a configuration example of the scoreboard when the number of registers is 16. Corresponding to the 16 registers, at least as shown,
A memory circuit 60 for each bit is provided.

When an instruction to write to a register like the load (LD) instruction is decoded, the number of the register written by the load (LD) instruction (provisionally i)
The i-th storage circuit 60i corresponding to the above is set.

When the succeeding instruction reads the j-th register, the memory circuit 60j of the scoreboard corresponding to the j is read, and if the corresponding memory circuit 60j is set, it is rewritten by the preceding instruction. I was able to recognize that it would be done, for example, interlock at the E stage,
Wait for completion of writing of the preceding instruction.

If the read operation is performed, the memory circuit 6
If 0j is reset, it recognizes that it will not be rewritten by the preceding instruction and moves to the next stage without interlocking.

The preceding, for example, load (LD) instruction resets the memory circuit 60i corresponding to the i-th position of the scoreboard when writing to the i-th register. Therefore, if there is a subsequent instruction that interlocks to read the i-th register,
When the memory circuit 60i of the second scoreboard is reset, the interlock is released and the subsequent instruction is
The processing is restarted using the data written by the preceding instruction.

The above description shows the case of interlock control using the conventional scoreboard, but in this conventional method, the preceding instruction actually writes to the register and the correspondence of the scoreboard is made. When the register 60i is reset, the interlock is released for the first time, and there is a problem that the interlock is released by 1τ in comparison with the case where the dedicated “0” detection circuit 50 described above is used. Remain. Therefore, in the present invention, as shown schematically in FIG. 8 for interlock control by the scoreboard, bypassing of the operation result of the preceding instruction to the E stage of the succeeding instruction is prevented. , There is the above-mentioned "0" comparison "instruction in the E stage of the following instruction,
When the storage circuit 60i of the scoreboard provided corresponding to the register is "1" and at least the write enable (WE) to the register is "1", that is, the storage circuit 60i of the scoreboard. Is configured to be performed in the cycle before being reset to "0", the same "0" comparison "instruction as in the case of using the dedicated" 0 "detection circuit 50 can be speeded up. You will be able to do it.

In the above embodiment, "" 0 "comparison"
Although the instruction has been described as an example, the same applies to the preceding instruction, for example, “addition with“ 0 ”” and “logical operation with“ 0 ”” with bypass data of the operation result of the load (LD) instruction. Needless to say, the generation of the condition code for the operation bypass data can be speeded up. However, in this case, a process of writing the bypass data in the register is required in the next W stage.

As described above, the present invention comprises at least the decode stage (D), the operation stage (E), the operand fetch stages (C1 and C2), and the write stage (W). In the pipeline computer having means for interlocking the D stage or the E stage by detecting the above, there is an interlock between the preceding instruction and the succeeding instruction, and the operation instruction with the subsequent "0" Means for suppressing the D-stage interlock and enabling the E-stage interlock,
A means for detecting the timing of bypassing the data of the preceding instruction and a “0” detection circuit for the load data of the preceding instruction are provided, and the arithmetic instruction with the “0” is input to the D stage and the next E stage. , And the load data of the preceding instruction is bypassed to the E stage of the subsequent instruction immediately before the W stage based on the bypass control signal of the bypass timing detecting means, and then to the “0”.
The feature is that the condition code register (CC) is set with the condition code (Z, N, C) of the operation result with "0" based on the determination signal of the detection circuit.

[0066]

As described above in detail, the operation bypass circuit of the present invention is provided with at least the decode stage.
(D), operation stage (E), operand fetch stage (C1, C2), and write stage (W), and detects the data dependency to detect the D stage or E
In a pipeline computer having means for interlocking stages, when there is an interlock between a preceding instruction and a succeeding instruction and an operation instruction with the subsequent "0" is detected, the D stage interlock is suppressed. And a means for enabling the E-stage interlock, and a means for detecting the timing of bypassing the data of the preceding instruction,
A load data "0" detection circuit for the preceding instruction is provided, an operation instruction with "0" is input to the D stage, the next E stage is interlocked, and the load data of the preceding instruction is transferred to the W Immediately before the stage, after bypassing to the E stage of the subsequent instruction based on the bypass control signal of the bypass timing detection means, based on the determination signal of the "0" detection circuit, the bypass control signal of the bypass timing detection means. On the basis of the above, the condition code of the operation result with "0" is set in the condition code register (CC). Therefore, for example, in a program written in C language, the above "" 0 comparison Since the "instruction" is very often used in the case of performing the character string detection processing for detecting the end of the character string, the speeding up of the "" 0 "comparison" instruction increases the processing speed in the pipeline computer. Greatly contributes to speeding up.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention (No. 1).

FIG. 3 is a diagram showing an embodiment of the present invention (part 2).

FIG. 4 is a diagram showing an embodiment of the present invention (part 3).

FIG. 5 is a diagram showing an embodiment of the present invention (No. 4).

FIG. 6 is a diagram for explaining the effect of the present invention.

FIG. 7 is a diagram showing another embodiment of the present invention (No. 1).

FIG. 8 is a diagram showing another embodiment of the present invention (No. 2).

FIG. 9 is a diagram showing a basic configuration of a cache memory.

FIG. 10 is a diagram (1) showing the concept of a pipeline computer including a cache memory.

FIG. 11 is a diagram showing a concept of a pipeline computer including a cache memory (No. 1).

FIG. 12 is a diagram showing operation bypass in a conventional pipeline computer.

FIG. 13 is a diagram illustrating a problem of a conventional arithmetic bypass circuit.

[Explanation of symbols]

11 register or general-purpose register (GR) 12 arithmetic unit (ALU) 15 cache memory (CACHE) 150 data memory 151 tag memory 152 hit judgment circuit 153 data (WA
Y) Selection circuit 20,21,22 Interlock means 23 Bypass control circuit (Bypass timing detection means) 50 “0” detection circuit 60i Scoreboard memory circuit D Decode stage E Operation stage C, C1, C2 Cache memory access stage W Write stage Preceding instruction Subsequent instruction Operation bypass path or operation bypass judgment signal Write enable signal

Claims (2)

[Claims] 1. A decode stage (D), an operation stage (E), and an operand fetch stage (C1, C).
2) and a write stage (W), and detects the data dependency between the instruction () to be executed first and the instruction () to be executed subsequently to detect the D stage or E. Means to interlock the stage (20 ~
22), a register write of the instruction () to be executed earlier, or an operation bypass means () for bypassing operation data to a subsequent instruction () at a timing immediately before the register write, and an operation result generated by an operation result. A pipeline processing computer equipped with a conditional code generation circuit (32), and a means (4) for detecting that the instruction is an operation instruction with "0".
0) and the operation instruction of "0", the D stage interlock means (20) is prevented from interfering with the D stage interlock means and the E stage interlock means
The interlock control means (20a, 22a) for enabling the E-stage interlock in (22), the means (23) for detecting the timing of bypassing the data of the preceding instruction, and the "0" of the load data of the preceding instruction. "Detection circuit (50), condition code generation circuit for generating condition code by inputting" 0 "judgment signal () of load data" 0 "detection circuit (50) and sign bit of the load data ( 31) and the condition code generated by the above condition code generation circuit (31) and the condition code generated by the above condition code generation circuit (31) are input, and a condition for selecting one of them is input. When the code selection circuit (30) is provided and the executing instruction () is an operation instruction with "0" and a "data dependency" is detected with the preceding instruction (). , The operation command with "0" is given to the interlock control means (20a, 22a). Then, the interlock of the D stage is suppressed, the interlock is performed at the next E stage, and the load data of the preceding instruction () is transferred to the bypass control signal of the bypass timing detection means (23) immediately before the W stage. On the basis of the above, by bypassing to the operation stage (E) of the operation instruction () with the “0”, the judgment signal is obtained by the “0” detection circuit (50) without performing the operation with the “0”.
() Is selected by the condition code selection circuit (31), and the condition code register (C
Operation bypass circuit characterized by setting to C). 2. A scoreboard memory circuit (60i) as means for detecting a data dependency between the preceding instruction and the succeeding instruction by the succeeding instruction in the arithmetic bypass circuit.
Based on the write enable signal () of the operation result data of the preceding instruction to the register (11), the operation result data of the preceding instruction is bypassed () to the E stage of the subsequent instruction, and the corresponding scoreboard The operation bypass circuit according to claim 1, wherein the memory circuit (60i) is reset.