JPH0531101B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a processing circuit for discriminating defects such as streak-like scratches existing on the surface of an object to be inspected.

[Conventional technology]

Various surface inspection devices are known for detecting defects on the surface of sheets of film, paper, etc., metal objects, and other products. Product quality control is performed by detecting defects, etc.

Such a measuring device detects not only simple scratches and pinholes but also streaky scratches. For example, FIG. 5 shows a surface inspection device (first conventional example) for a sheet-like object (web).
This apparatus is irradiated with a light spot from a light source 2 via a scanning mechanism 3 in a direction perpendicular to the flow direction of the web 1. Then, the reflected light from the web 1 is received by a light receiver 4, and as shown in the figure, an area (data cell) P is divided into a plurality of lanes and frames in the width direction and flow (length) direction. Detection of streak defects is performed every time.

That is, the inspection light from the scanning mechanism 3
Scanning is performed from one end to the other end, and scanning is performed multiple times in one frame length. In this case, the defect signal is integrated by a counter circuit in the data cell P each time it is scanned, and this integrated signal is When the value is larger than the threshold value, it is determined that there is a streak defect. For example, the streak 100 in FIG. 5 is determined to be a streak defect by counting four defect signals in four scans.

In addition, in another conventional processing circuit (second conventional example), instead of simply integrating defective signals, when a defective signal is obtained using an up-down counter, "1" is added, and the defective signal is An integration method is used in which ``1'' is subtracted when ``1'' is not obtained, and it is also used to distinguish between simple scratches and streaks.

Furthermore, as shown in Japanese Patent Publication No. 52-437128 (third conventional example), shift registers corresponding to the number of lanes divided in the width direction are connected, and the detection signal for each lane is scanned in a plurality of predetermined scans. Memorize only the minutes. Then, in each scan, the detection signals for the predetermined scan are added for each lane, and this is used as the detection signal for the lane.

Therefore, according to this, it is possible to discriminate between a signal having defect information and randomly generated noise, and to effectively discriminate a streaky defect.

[Problem that the invention seeks to solve]

However, in the first and second conventional examples described above, since streak defects are detected frame by frame, it is not possible to accurately grasp the actual length of streaks spanning between frames, and There is a problem that accuracy deteriorates. That is, the integration counter only integrates the detection signal within one data cell P, and the counter value is reset to 0 at the end of one frame, making it impossible to detect streak defects existing between frames.

Further, in the first conventional example, there is a problem in that a streaky defect signal with a small S/N ratio cannot be optically distinguished from a noise signal. In order to accurately detect shallow streak defects and narrow streak defects, it is necessary to discriminate defect signals with a small S/N ratio. It is necessary to set the threshold value of the integration counter low. In the first conventional example,
Since defect signals and randomly generated noise signals are integrated in the same way, the probability of erroneously detecting noise as a defect signal increases, making accurate measurement impossible.

Furthermore, although the third conventional example can detect some streak defects between frames and detects streak defects better than the first and second conventional examples, this example also has intermittent defects. However, there is a problem in that it is not possible to detect streak defects that exist.

In other words, streaky defects may appear with intermittent strength and weakness in the length direction, but if defect signals are detected intermittently in this way, for example, as shown in Figure 6, the above-mentioned up-down In the case of using a counter or the like, the integrated value cannot exceed the threshold value due to the disappearance of streak defects, and such streak defects cannot be discriminated.

[Purpose of the invention]

The present invention has been made to solve the above problems, and is capable of accurately detecting random defects, random noise, and streak defects, and detecting streak defects that exist between frames and streak defects that occur intermittently. It is an object of the present invention to provide a streak defect discrimination processing circuit that can satisfactorily discriminate various streak defects such as the following.

[Means for solving problems]

In order to achieve the above object, the streaky defect discrimination processing circuit according to the present invention first includes a temporary storage circuit that temporarily stores binary detected data, and a temporary storage circuit that temporarily stores the detected data that is stored in this temporary storage circuit. It is equipped with an addition/subtraction control circuit that converts it into weighted detection data, and the temporary storage circuit stores the detection data for each small data cell set by subdividing the width direction and length direction into a predetermined number, and performs addition/subtraction control. The circuit reads out this detected data for each small data cell in the length direction,
It is converted into weighted detection data that is weighted with a predetermined addition value x when there is a defect, and weighted with a predetermined subtraction value y when there is no defect.

Then, there is a lane number counter circuit that outputs an address signal corresponding to the lane number of the data cell from the divided signal output for each lane divided in the width direction, and an integrated value that sequentially stores the integrated value of the weighted detection data. A storage circuit, an adder/subtractor, and a comparator are used, and the integrated value storage circuit stores integrated values that are sequentially added for each lane number, and the adder/subtractor stores the integrated value that is added sequentially for each lane number, and the adder/subtractor outputs the output from the addition/subtraction control circuit and the integrated value storage circuit. Then, the detected data and the integrated value are adjusted. When the output thus obtained exceeds a reference value set in the comparator, the comparator provides a streak defect output.

[Effect]

According to the above configuration, first, a value obtained by multiplying the detection signal by weighting for detecting a streak defect is output, and if it is defect data, an increase value
However, if the data is normal, the reduction value Y will be added or subtracted. The increase value x and decrease value y are values that change depending on the streak defect to be measured. For example, when detecting continuous defects, set x<y, and when detecting intermittent defects, set x> It is set appropriately as y.

The weighted detection data obtained in this way is accumulated sequentially, and this data accumulation value serves as the standard for determining whether or not the defect is streak-like. A streak defect is determined by exceeding a predetermined comparison value set in , that is, a threshold value that is an index of a streak defect.

Preferred embodiments of the present invention will be described below with reference to the drawings.

〔Example〕

FIG. 1 shows the entire block of the streak defect discrimination processing circuit, including a photoreceiver 4, filter circuits 5 and 2.
The configuration of the value conversion circuit 6 is the same as the conventional one.

A feature of the present invention is that various streak defects can be accurately discriminated by adding and subtracting weights to the detection signals measured in subdivided data cells. For this reason, in the illustrated embodiment, a temporary storage circuit 7 that temporarily stores the binarized data, an addition/subtraction control circuit 9 that weights the binarized data outputted via the gate circuit 8, and a weighting control circuit 9 that weights the binarized data for each divided lane. an adder/subtractor 12 that integrates the detected data, and an integrated value storage circuit 1 that stores the output of the adder/subtractor 12.
3. A comparator 14 is used to determine streak defects. The comparator 14 is provided with a comparison value setting switch 17, whereby a comparison value serving as a comparison standard is set in the comparator 14. Note that the integrated value storage circuit 13 includes:
RAM and shift registers are used.

The addition/subtraction control circuit 9 is provided with a "+x" setting switch 10 and a "-y" setting switch 11. When the binary data output from the temporary storage circuit 7 is a defective signal "1", an addition value x is associated with it, and when it is a normal signal "0", a subtraction value y is associated with it. Further, in order to output a length measurement signal in the length direction of the data cell to the gate circuit 8, a length measurement pulse frequency divider 1 is provided.
5 is provided. This length measurement pulse frequency divider 15
inputs, for example, a line length measurement pulse output from a feeding mechanism for the object to be measured.

Further, the scanning mechanism 3 shown in FIG. 5 outputs a lane mark pulse for dividing one scanning line of the inspection light into a plurality of lanes, and this lane mark pulse is input to the lane number counter 16. . Based on the lane mark pulse, the lane number counter 16 sends different address signals to the integrated value storage circuit 1 in accordance with the number of divided lanes.
Output to 3. Further, the output from the comparator 14 is inverted and inputted to the integrated value storage circuit 13 via a negative circuit 18 and an integrated value clear circuit 19.

The embodiment has the above configuration, and its operation will be explained below based on FIG. 2. Figure 2 shows signal processing waveforms in each block. If the output from the photoreceiver 4 is as shown in Figure A, the output of the filter circuit 5 is either defect-free ("0") or defective as shown in Figure B. Binarized data indicating whether it is present (“1”) is output.

The binarized data thus output is temporarily stored in the temporary storage circuit 7. A lane mark pulse for dividing the object to be measured in the width direction is supplied to this temporary storage circuit 7, and the binary data is temporarily stored together with the position of the object to be measured in the width direction. In this way, scanning in the width direction is repeated a certain number of times (or even once), and the length measurement pulse frequency divider 1 determines that the object to be measured has advanced by one small data cell in the flow direction.
5, the binary data stored in the temporary storage circuit 7 is output to the addition/subtraction control circuit 9 via the gate circuit 8 in synchronization with the lane mark pulse shown in FIG.

The addition/subtraction control circuit 9 weights the binary data supplied from the temporary storage circuit 7 with "+x" and "-y" as shown in FIG. In this embodiment, in order to detect continuous streak defects, for example, the +x setting switch 10
=3, -y Since y is set to 5 by the setting switch 11, "+3" is assigned to the defective data whose binary data becomes "1", and the binary data becomes "0". "-5" is assigned to normal data. Note that when attempting to detect intermittent streak defects, the +x setting switch 10, -y
The weighting data is set by the setting switch 11 so that x>y, the details of which will be described later.

The detection data outputted from the addition/subtraction control circuit 9 is added/subtracted for each lane by an adder/subtractor 12 and stored in an integrated value storage circuit 13 . A lane number address outputted by a lane number counter 16 corresponding to the number of lane mark pulses is input to this integrated value storage circuit 13, and the detection data is stored for each lane number address.
That is, the values are accumulated and stored for each lane in which the object to be measured is divided in the width direction.

The adder/subtractor 12 further adds or subtracts the detection data from the addition/subtraction control circuit 9 to the integrated value of FIG. 2 G fed back from the integrated value storage circuit 13, and outputs integrated detection data as shown in FIG. do. This integrated detection data is input to the comparator 14 and compared with a comparison value (threshold value) set by the comparison value setting switch 17, for example "30". And in either lane,
When the integrated detection data exceeds the comparison value "30", the comparator 14 provides the streak defect output shown in FIG. 2I.

FIGS. 3a and 3b show an example of a streaky defect and its measurement results. As shown in the figure, the streaks occurring in the third lane are interrupted at two points along the way, and these interrupted portions are shorter than the streaked portions, and random defects are present in the other lanes. Therefore, as shown in FIG. 3b, the streak in the third lane exceeds the comparison value "30" and is determined to be a streak defect. However, since the defects existing in other lanes do not exceed the comparison value "30" and are not detected as streaky defects, it becomes possible to clearly distinguish and detect streaky defects. Of course, even if intermittent noise enters the receiver 4,
Similarly, this is not detected as a streaky defect and is less likely to be affected by noise. In addition, comparator 1
When a streaky defect output is output from 4, this output is supplied as a reset signal to the integrated value clearing circuit 19 via the NOT circuit 18, and the address corresponding to the lane where the streaky defect existed in the integrated value storage circuit 13 is sent. The data is cleared to "0" and new detection data is integrated again.

In the above embodiment, the detection data is weighted under the condition of x<y, which is suitable for detecting relatively long streaks, but the weighting ratio is changed when detecting short streaks. Do it like this.

In other words, as shown in FIG. 4a, in the case of continuous streak defects (stripe length is greater than the inter-stripe interval length), even if the defect is small, by setting x<y as in the example, Even if it is accompanied by noise,
Since the integrated detection data does not exceed the comparison value, streak defects are detected separately from these.

On the other hand, in the case of intermittent streak-like defects (muscle spacing is larger than streak length), the +x setting switch 1
0 and -y setting switch 11 to set x>y. As a result, defect data is weighted more heavily than normal data, and even small defects that occur randomly can be detected. In other words, continuous streaks are created by making the weighted addition value of defect detection data smaller than the weighted subtraction value of normal detection data, and intermittent streaks are created by making the weighted addition value of defect detection data smaller than the weighted subtraction value of normal detection data. Detection is possible by making the value larger than the weighted subtraction value.

〔Effect of the invention〕

As explained above, in the present invention, the object to be measured is subdivided into data cells by lane division and frame division, and the binarized signals detected from within the data cells are added and subtracted while being weighted and integrated. ing. Therefore, it becomes possible to accurately discriminate and detect streaky defects, which are the most problematic in practice, from intermittent defects and noise. Moreover, since the defect/normality evaluation information is accumulated for each data cell and is not reset for each frame, it is possible to correctly detect long streak defects that span frames.
In addition, by changing the weighting values, it is possible to distinguish whether the detected defect is continuous or intermittent, so it can be applied not only to surface inspection equipment but also to various types of defect detection and measurement. It is possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a preferred embodiment of a streak defect discrimination processing circuit according to the present invention. FIG. 2 is an output waveform diagram of each part in the block diagram of FIG. 1. FIG. 3 is an explanatory diagram showing the defect state of the object to be measured and the measurement results. FIG. 4 is an explanatory diagram comparing the measurement results of continuous and intermittent streak defects. FIG. 5 is a schematic diagram of a conventional surface inspection apparatus using a streak defect discrimination processing circuit.
FIG. 6 is an explanatory diagram showing measurement results when using a conventional streak defect discrimination processing circuit. 4... Light receiver, 6... Binarization circuit, 7... Temporary memory circuit, 9... Addition/subtraction control circuit, 10... +X
Setting switch, 11...-Y setting switch, 12
...Adder/subtractor, 13... Integrated value storage circuit, 14...
…comparator.

Claims (1)

[Scope of Claims] 1. In a streak defect discrimination processing circuit for converting a detection signal from the surface of an object to be measured into a binary signal and measuring a streak defect using the binary signal, comprising: A temporary storage circuit that temporarily stores the binarized detection data for each data cell set by subdividing the object in the width direction and length direction, and a temporary storage circuit that temporarily stores the detection data stored in this temporary storage circuit. An addition/subtraction control circuit that converts each data cell in the length direction into weighted detection data that is weighted with a predetermined addition value x when there is a read defect and a predetermined subtraction value y when there is no defect; A lane number counter circuit secures an address area for storing data for each lane number from the division signal output for each divided lane, and the data is accumulated for each data cell on the same lane in accordance with the lane number. an integrated value storage circuit that sequentially stores integrated data of weighted detection data; an adder/subtractor that adds/subtracts the output of the addition/subtraction control circuit and the integrated value storage circuit; and an adder/subtractor that adds/subtracts the output of the addition/subtraction control circuit and the integrated value storage circuit, and compares the output of the adder/subtractor with a predetermined comparison value to perform data integration. A streak defect discrimination processing circuit comprising a comparator that determines a streak defect when the value exceeds the comparison value. 2 The above addition value x and subtraction value y are determined by weighting detection data under the condition that x < y when detecting continuous streak defects, and x > y when detecting intermittent streak defects. 2. The streaky defect discrimination processing circuit according to claim 1, wherein the processing circuit converts into data.