JPH0530548A - Line terminating equipment - Google Patents

Abstract

PURPOSE:To output a stable timing signal by detecting only a pulse signal with a pattern prevented from being influenced by a timing shift 7 in an output pulse signal outputted from a detection part by means of a pattern detecting circuit, inputting the detected signal to a digital phase synchronizing circuit and inputting a timing signal to a bridged tap equalizer. CONSTITUTION:This line terminating equipment is provided with the bridged tap equalizer 1, the digital phase synchronizing circuit 2, a line equalizer 3, the detection part 4, and the pattern detecting circuit 5. The circuit 5 detects only a pulse signal with a pattern prevented from being influenced by a timing shift in an output pulse signal outputted from the detection part 4, i.e., only '1' immediately after '0', and a timing signal is inputted from the circuit 2 to the equalizer 1. Since signals excluding a signal with a large timing shift can be inputted from the circuit 5 to the circuit 2, a stable timing signal can be outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a subscriber line line terminating device including a bridged tap. When laying a subscriber line, the location of a new subscriber cannot be determined, so branching from the middle and laying it in a different area in advance and connecting the new subscriber to one of the branch destinations will result in branching. The other end is an open end. That is, the subscriber line includes a bridged tap. In a subscriber line line terminating device including such a bridged tap, a line equalizer for equalizing line loss and a bridged tap equalizer for canceling echo due to the bridged tap are provided. Has been.

[0002]

2. Description of the Related Art FIG. 4 is an explanatory diagram of an echo by a bridged tap, in which a station side line terminating device 41 and a terminal side line terminating device 42 connecting a terminal 43 are connected by a subscriber line 44, and the subscriber When the line 44 includes the bridged tap 44a, the tip of the bridged tap 44a is in an open state, and for example, when the pulse signal 45 synchronized with the timing signal T is transmitted from the station side line termination device 41, The signal A traveling straight on the subscriber line 44 and the signal B returned by being reflected at the open end of the bridged tap 44a are transmitted to the terminal side line termination device 42, and the signal B is the signal A. Is delayed by a time t corresponding to the time when it is turned back by the bridged tap, and is attenuated.
Therefore, as shown by 46, the signal A and B are input to the terminal side line terminating device 42 as a combined signal.
That is, the signal B is superposed on the signal A as an echo component.

In order to cancel such an echo component and equalize the line loss, the station side line termination device 41 and the terminal side line termination device 42 are provided with a bridged tap equalizer and a line equalizer. To be FIG. 5 is a block diagram of a conventional example,
Reference numeral 51 is a bridged tap equalizer, 52 is a digital phase synchronization circuit, 53 is a line equalizer, 54 is a detector, 55 is a tank circuit, 56 is a subscriber line including a bridged tap, 5
Reference numeral 7 is a transformer, and 58 and 59 are comparators.

The detector 54 comprises a plurality of comparators 58 and 59, and compares the equalized output signal of the line equalizer 53 with the discrimination level L1 of ± 50% of the set peak value by the comparator 58, for example. The received data 60 is used as the received data 60, and is compared by the comparator 59 at the discrimination level L2 of ± α% (eg, α = 50% when used in the LC tank circuit) of the set peak value,
Α% comparison data 6 corresponding to the peak position of the equalized output signal
1, the α% comparison data 61 is input to the tank circuit 55 having a resonance circuit including a coil and a capacitor, the resonance output signal 62 is input to the digital phase synchronization circuit 52, and the timing is phase-synchronized with the resonance output signal 62. Signal 6
3 is input to the bridged tap equalizer 51 to detect an echo component.

Further, in the detection unit 54, for example, a value obtained by comparing and integrating at a discrimination level of ± 100% of a set peak value is converted into an impedance to be a feedback signal 65, which is input to the line equalizer 53 to be a line loss. Of the set peak value in the detection unit 54 and the signal 64 compared with the discrimination level of ± 50% and the discrimination level of ± 0% is input to the bridged tap equalizer 51, and the timing is input. The echo component is identified by the signal 63 and the echo replica 66
Is formed and input to the line equalizer 53, the echo component due to the bridged tap is canceled.

FIG. 4A shows a received signal 46 containing an echo component by the bridged tap 44a, and the echo replica 66 shown in FIG. 4B in the bridged tap equalizer 51 of FIG. By forming this echo replica 66 and inputting it to the line equalizer 53 and subtracting it from the received signal 46, a received signal in which the echo component is canceled is obtained as shown in FIG. It is possible to output the identification data of "1" and "0" by recognizing that the received signal is at any level of +1, -1, and 0 without error by the level identification timing shown.

FIG. 4 (d) shows a received signal of "1" after "0", and when the peak position of this received signal is timing T1, as shown in FIG. 4 (e), When "1" continues, the received signal corresponds to the signal shown by the solid line which is the combination of the positive and negative signals of -1 and +1 shown by the dotted line, so the timing of the peak position is shown at T2. . That is, the phase of the peak position of the received signal is shifted. Timing signal 6 due to such a phase shift
In order to prevent the phase shift of No. 3, a tank circuit 55 composed of a resonance circuit including a coil and a capacitor is provided, and the resonance frequency of this tank circuit 55 is made to match the frequency of the timing signal 63. By ± α
Since the phase shift of the% comparison data 61 can be absorbed, the stable timing signal 63 can be output from the digital phase synchronization circuit 52.

[0008]

Problems to be Solved by the Invention The tank circuit 5 described above.
Since 5 has a configuration including a coil and a capacitor, it is almost impossible to achieve miniaturization by forming an integrated circuit. Further, the coil and the capacitor are selected so that the resonance frequency corresponding to the transmission speed of the subscriber line 44 can be obtained. Therefore, in order to obtain a configuration applicable to a plurality of types of transmission speeds, a plurality of coils and a plurality of coils are required. Since a configuration for switching the combination with the capacitor is required, there is a drawback that the number of parts is increased. Further, since the tank circuit 55 uses analog circuit parts, there is a drawback that the characteristics and characteristics of the parts are affected by aging and variations, which complicates design and adjustment. It is an object of the present invention to reduce the size and stabilize the digital circuit.

[0009]

The line terminating device of the present invention will be described with reference to FIG. 1. In a subscriber line terminating device including a bridged tap, an echo component generated by the bridged tap is eliminated. A bridged tap equalizer 1 that generates an echo replica to cancel, a digital phase synchronization circuit 2 that outputs a timing signal that determines the detection timing of an echo component of the bridged tap equalizer 1, and a line loss of a subscriber line A line equalizer 3 that equalizes and cancels an echo component by an echo replica from the bridged tap equalizer 1, a detection unit 4 that discriminates the level of an equalized output signal from the line equalizer 3, The output pulse signal from the detection unit 4 detects only the pulse signal having a pattern that is not affected by the timing deviation and inputs it to the digital phase synchronization circuit 2. It is obtained by a chromatography down detection circuit 5.

In the pattern detection circuit 5, the "1" next to the bit number "0" which is not affected by the timing shift of "1" in the output pulse signal due to the predetermined level from the detection unit 4 is next.
Only the output is made.

[0011]

The pattern detection circuit 5 detects only the pulse signal of the pattern which is not affected by the timing shift in the output pulse signal from the detection section 4. For example, since "1" after "1" has a timing shift as shown in FIG. 4 (e), "1" after "1" is not input to the digital phase locked loop 2. . As a result, only the output pulse signal from the detection unit 4 in which the timing deviation does not matter is input to the digital phase synchronization circuit 2, so that a stable timing signal can be output.
Further, since the pattern detection circuit 5 can be configured by a digital circuit, it is possible to reduce the size.

Further, the pattern detection circuit 5 adds "+" to the received signal.
When the signal of the level of "1" or "-1" is included,
Only "1" is output after a signal of "0" with the number of bits until the influence of the echo of the received signal disappears. For example, the number of "0" after "1" is counted. However, only “1” after the set number of “0” is added to the digital phase locked loop 2.

[0013]

EXAMPLE FIG. 2 is an explanatory view of an example of the present invention.
Is a bridged tap equalizer (BTEQL), 12 is a digital phase synchronization circuit (DPLL), 13 is a line equalizer (LEQL), 14 is a detection unit, 15 is a pattern detection circuit, and 16 is a subscription including a bridged tap. Power line, 17 is a transformer, 18 is an operational amplifier, 20 is a flip-flop,
21 is an inhibit circuit, 22 is a comparator, R1 to R12
Is a resistor, C1 to C5 are capacitors, and Q1 to Q5 are transistors. Further, the bridged tap equalizer 11 can use, for example, a known configuration in which an echo replica is formed by charging / discharging a capacitor based on the comparison output data from the detection unit 14. The digital phase synchronization circuit 12 can also use various configurations including the already known phase comparison section, loop filter, voltage controlled oscillator and the like.

Further, the detecting section 14 is provided with a plurality of comparators 22 for discriminating the equalized output signals from the line equalizer 13 at different discrimination levels, and comparing them at discrimination levels of ± 50% of the set peak value. The received data 31 is also used as the signal 32 to be added to the bridged tap equalizer 11 by comparing the discrimination levels of ± 50% and ± 0% of the set peak value, and ± α% (eg α = 90) of the set peak value. ), The α% signal 33 to be added to the pattern detection circuit 15 is compared, and the discrimination level ± 100% of the set peak value is compared to be the field back signal 34 to be added to the line equalizer 13.

A line equalizer 13 to which a received signal is applied from a subscriber line 16 including a bridged tap through a transformer 17 receives a feedback signal 34 from a transistor Q1 and a low pass filter including a resistor R11 and a capacitor C4. A current converter for converting into a current and a capacitor C
1 and a resistor R1 to form a current-voltage converter, a first voltage impedance converter including transistors Q2 and Q3, a second voltage impedance converter including transistors Q4 and Q5, and an amplifier including an operational amplifier 18. Etc. are included.

Feedback signal 34 from detector 14
Is "0" when the equalized output signal from the line equalizer 13 exceeds ± 100%, whereby the charging current of the capacitor C1 flows through the transistor Q1 due to the + V power supply voltage. The capacitor C1 is a resistor R1
, The terminal voltage of the capacitor C1 is determined according to the appearance frequency of the time width of the feedback signal 34, and when the equalized output signal level is large, the feedback signal 34 of "0" is output. Either or both of the time width and the appearance frequency increase the terminal voltage of the capacitor C1. On the contrary, when the equalized output signal level is low, the terminal voltage of the capacitor C1 is low.

The terminal voltage of this capacitor C1 is
If the terminal voltage of the capacitor C1 is large within a range in which the transistors Q2 to Q5 are not saturated, the voltage is applied to the bases of the transistors Q2 and Q4 forming the second voltage impedance converter via the resistors R3 and R5. , Q4 increases. That is, the resistance R
The impedances of the transistors Q3 and Q5 which are diode-connected by connecting 4, R6 between the collector and the base are small. On the contrary, when the terminal voltage of the capacitor C1 is small, the impedance becomes large. Therefore, an attenuator can be configured by the second voltage impedance converter and the resistor R10 to increase the amount of attenuation when the equalized output signal level is high, and by the first voltage impedance converter and the capacitor C2, The amplification frequency characteristic of the operational amplifier 18 can be controlled.

Further, since the echo replica 38 from the bridged tap equalizer 11 is input to the inverting terminal of the operational amplifier 18, the echo replica 38 is subtracted from the received signal input to the non-inverting terminal, and the echo component Is canceled and the equalized output signal is added from the operational amplifier 18 to the detection unit 14.

The pattern detection circuit 15 comprises a flip-flop 20 and an inhibit circuit 21. The inhibit circuit 21 prohibits "1" after "1",
Only "1" after "0" is digital phase synchronization circuit 12
Of the flip-flop 20. The α% signal 33 is input to the data terminal D of the flip-flop 20, and the clock terminal C
Timing signal 3 from the bridged tap equalizer 11
7 or the timing signal 36 from the digital phase synchronization circuit 12 is input, and the α% signal 3 is input to the inhibit circuit 21.
3 and the output signal from the output terminal Q of the flip-flop 20 is input as an inhibit signal.

FIG. 3 is an operation explanatory view of the embodiment of the present invention, (a) is a received signal, (b) is a timing signal 37,
(C) is an α% signal, (d) is a digital phase synchronization circuit 3
5 shows an example of the input signal 35, (e) the output signal of the flip-flop 20, and (f) shows an example of the output signal of the inhibit circuit 21.

Comparing the received signal of "110101110" shown in (a) with the discrimination levels of + α% and -α%,
The α% signal shown in (c) is obtained. Since "1" immediately after "1" has the phase of the peak position shifted as described above, except for "1" immediately after such "1",
A pattern of "1" immediately after "0" is detected, and only the "1", that is, only the signal shown in (d) is input to the digital phase synchronization circuit 12. Therefore, since only the α% signal in which the phase at the peak position is almost not shifted can be input to the digital phase synchronization circuit 12, the stable timing signal 36 can be output as in the conventional example using the tank circuit.

Further, the digital phase synchronizing circuit 12 has a timing signal 36 synchronized with the rising phase of the input signal 35.
, The pattern detection circuit 15 can be configured by the flip-flop 20 and the inhibit circuit 21 as shown in the figure, and the timing signal of FIG. By inputting and inputting the α% signal of (c) to the data terminal D of the flip-flop 20,
The output signal from the output terminal Q of 0 is as shown in (e). That is, the pattern of "1" immediately after "0" is detected, and only the "1" is input from the inhibit circuit 21 to the digital phase synchronization circuit 12. Since the pattern detection circuit 15 is composed of a digital circuit including the flip-flop 20 and the inhibit circuit 21, it is possible to reduce the size by integrating the circuit.

In the pattern detection circuit 15 described above, when the influence of "1" extends to 1 bit, that is, when there is 1 bit of "0", "1" immediately after that is the phase shift of the peak position. An example of a pattern in which there is no influence is shown. When the influence of "1" extends up to 2 bits later, "0" is counted and "1" after 2 bits of "0" continues. ”Is the input signal 35 of the digital phase synchronization circuit 12
And such a configuration is, for example,
This can be easily realized by adding one flip-flop to the pattern detection circuit 15 including the flip-flop 20 and the inhibit circuit 21. Further, when the influence of "1" extends to a large number of bits, by adding a configuration that counts "0" corresponding to the number of bits, a pattern that becomes "1" after a predetermined number of "0" consecutive Can be detected.

[0024]

As described above, according to the present invention, the bridged tap equalizer 1, the digital phase synchronization circuit 2,
A line terminating device including a line equalizer 3, a detection unit 4, and a pattern detection circuit 5. The pattern detection circuit 5 allows a pattern not affected by a timing shift in an output pulse signal of the detection unit 4. Only pulse signals, for example,
Only the "1" immediately after the "0" is detected and input to the digital phase synchronizing circuit 2, and the timing signal is input from the digital phase synchronizing circuit 2 to the bridged tap equalizer 1. 2 can be input from the pattern detection circuit 5 excluding a signal with a large timing deviation, so that a stable timing signal can be output. Further, unlike the conventional tank circuit, the pattern detection circuit 5 is composed of a digital circuit, so that there is no change in characteristics due to aging, and the pattern detection circuit 5 can be integrated into an integrated circuit so that it can be miniaturized. There is. Further, when the transmission speeds of the subscriber lines are different and the detection pattern is not changed, the pattern detection circuit 5 has an advantage that it can be used without changing the configuration shown in FIG. 2, for example.

Further, the pattern detection section 5 counts the number of bits "0" which is not affected by the timing shift of "1" by a flip-flop, a counter or the like, and then "1" after the number of bits is continued. By outputting only the signal, only a signal with a small timing shift can be input to the digital phase locked loop 2, so that a stable timing signal can be output and the bridged tap equalizer 1 can be output. There is an advantage that the echo component in the echo can be detected without error and an echo replica can be generated.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is an explanatory diagram of an example of the present invention.

FIG. 3 is an operation explanatory diagram of the embodiment of the present invention.

FIG. 4 is an explanatory diagram of echo by a bridged tap.

FIG. 5 is a block diagram of a conventional example.

[Explanation of symbols]

1 Bridged tap equalizer 2 Digital phase synchronization circuit 3 line equalizer 4 detector 5 pattern detection circuit

Claims (2)

[Claims] 1. A subscriber line line terminating device including a bridged tap, a bridged tap equalizer (1) for generating an echo replica for canceling an echo component generated by the bridged tap, and the bridge. A digital phase synchronization circuit (2) for outputting a timing signal that determines the detection timing of the echo component of the tap-tap equalizer (1), the line loss of the subscriber line, and the bridged tap equalizer A line equalizer (3) for canceling the echo component by the echo replica from (1), and a detection unit (4) for identifying the level of the equalized output signal from the line equalizer (3); A pattern for detecting only a pulse signal having a pattern in which the timing deviation in the output pulse signal from the detection unit (4) does not affect and inputting it to the digital phase synchronization circuit (2). Down detection circuit (5) and the line termination device characterized by comprising a. 2. The pattern detection circuit (5) is arranged so that the output pulse signal of a predetermined level from the detection section (4) is next to the bit number "0" which is not affected by the timing shift of "1". The line terminating device according to claim 1, further comprising a configuration for outputting only "1".