JPH05304601A - Image information converter - Google Patents

Abstract

PURPOSE:To reduce a memory capacity, and to attain a high speed conversion by providing a decoding circuit, enlarging/reducing circuit, and encoding circuit, and attaining a pipe line operation. CONSTITUTION:A decoding circuit 21 which is controlled by the first control means of a DMA controller 25 decodes encoded data. The decoded image data are reduced or enlarged by a main scanning direction enlarging/reducing circuit 22, and a subscanning direction enlarging/reducing circuit 23 which are controlled by the second control means of the DMA controller 25, and encoded by an encoding circuit 24 which is controlled by the third control means of the DMA controller 25. Thus, it is not necessary to provide circuits of plural systems by the pipe line operation which allows the first-third control means to synchronously operate in parallel, so that the memory capacity can be reduced, and the high speed image information conversion can be attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image information conversion device for converting image size and encoding method in MH, MR or MMR encoding method in which monochrome image information is compressed.

[0002]

In the field of electronic filing systems,
There is a big problem in the enlargement or reduction display on the CRT display device, the enlargement or reduction print, the image enlargement processing time or the image reduction processing time in the transmission to the facsimile device.

As an image enlarging or reducing means, for example, one utilizing a mapping pattern (product name: Logical Image Controller MN8617) or an apparatus developed by the present applicant (see JP-A-60-20632). ). The device developed by the present applicant uses a carry signal (carry signal) output from a P-bit adder to output source data bit by bit, which is a parallel / serial conversion circuit (hereinafter referred to as P / S conversion circuit). And the serial / parallel conversion circuit (hereinafter referred to as S / P conversion circuit) that takes in the output of this P / S conversion circuit bit by bit and uses it as the destination data, and expands or reduces the clock given to each conversion circuit. By changing according to the rate, 1/2 ^P
It is possible to enlarge or reduce from 2 times to 2 ^P times.

[0004]

By the way, as a coding system of the facsimile apparatus, the MR system is generally used in the G3 machine, whereas the MMR system is standardized in the G4 machine. Also, the maximum image size is generally B4 size.

Therefore, the procedure for transmitting an A3 size image encoded and stored in an electronic file is as shown in FIG. That is, first, the encoded data is decoded, and the decoded first image data is temporarily stored in the memory. Next, the first image data stored in the memory is enlarged or reduced, and the enlarged or reduced second image data is once stored in the memory. Then, the second image data stored in the memory is encoded.

As described above, the procedure of the decoding process, the enlargement or reduction process, and the encoding process is performed via the memory, and it takes time, and at the same time, the memory for decoding and the enlarged or reduced second image data are stored. A memory for storing is required. Also, if this communication is to be run as a back job of the system, a dedicated memory is required.

Furthermore, since the G3 machine generally does not support the MMR system, it is necessary to convert the MMR code into an MR code or the like, and in that case, a memory is also required.

The present invention is for decoding encoded data, enlarging or reducing encoded first image data,
Another object of the present invention is to provide an image information conversion device that can shorten the time required for a series of data processing such as encoding of enlarged or reduced second image data and can reduce the memory.

[0009]

An image information conversion apparatus according to the present invention is a decoding circuit for decoding encoded data, and one system for expanding the decoded first image data. An encoding circuit, an encoding circuit for encoding the enlarged second image data, and a first inputting the encoded data to the decoding circuit for decoding
Control means, second control means for sequentially inputting the first image data to the enlargement circuit to enlarge the image data, and third control means for sequentially inputting the second image data to the encoding circuit to encode the second image data. And the means for operating the first, second, and third control means in parallel in synchronization.

Further, the image information conversion circuit according to the present invention is a decoding circuit for decoding encoded data, and a plurality of systems of scaling for scaling up or down the decoded first image data. Encoding circuit, encoding circuit for encoding the enlarged or reduced second image data, first control means for inputting the encoded data to the decoding circuit and decoding it, the first Second control means for sequentially inputting the image data of 1) to the enlargement / reduction circuit to enlarge or reduce it, and third control means for successively inputting the second image data to the encoding circuit to encode the second image data. , And means for operating the first, second, and third control means in parallel in synchronization.

[0011]

In the first embodiment of the present invention, the first control means for inputting the encoded data to the decoding circuit and decoding it.
Second control means for inputting the first image data to the sequential expansion circuit to enlarge the image data and third control means for inputting the second image data to the sequential encoding circuit to encode the data are synchronized in parallel. Be operated by.

In the second embodiment of the present invention, the first control means for inputting the encoded data to the decoding circuit for decoding and the first image data for inputting to the successive enlargement / reduction circuit are enlarged. The second control means for converting or reducing the size and the third control means for sequentially inputting and encoding the second image data to the encoding circuit are operated in parallel in synchronization.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is an overall block diagram of an image size conversion apparatus according to an embodiment of the present invention.

In FIG. 1, 1 is a main control unit, 2 is an image memory, 3 is an image size / encoding system conversion unit, 4 is an image scanner, 5 is a laser printer, 6 is an input / output control unit,
7 is an interface, 8 is an optical disk drive, 9 is a communication control unit, 10 is a compression / decompression unit, 11 is a display control unit, 1
Reference numeral 2 is a display memory, and 13 is a CRT.

The main controller 1 is composed of a CPU, a keyboard and the like and controls the whole. The image memory 2 temporarily stores digitized image data representing a monochrome binary image, encoded data obtained by encoding the image data, and the like. The image size / encoding system conversion unit 3 consistently performs image size conversion and encoding system conversion. The image scanner 4 reads the image and outputs the digitized image data to the image memory 2 via the input / output control unit 6. The laser printer 5 inputs the image data stored in the image memory 2 through the input / output control unit 6 and prints it out. The compression / decompression unit 10 encodes image data or decodes encoded data. For encoding, the image data in the image memory 2 is sent to the compression / expansion unit 10, and the encoded data output is written in the image memory 2. The encoded data is written to the optical disk mounted in the optical disk drive 8 via the interface 7. Decryption is
The coded data written on the optical disk is read out to the image memory 2 via the interface 7, the read coded data is decoded into image data by a procedure reverse to the coding, and is written in the image memory 2 again. .. 11
Is a display control unit, which generates a synchronization signal to the CRT 13, reads the display memory 12, and outputs it to the CRT 13. The display control unit 11 also transfers data between the image memory 2 and the display memory 12. A communication unit 9 outputs the contents of the image memory 2 to the communication circuit or receives information from the communication circuit and writes the information in the image memory 2.

FIG. 2 is a circuit block diagram of the image size / encoding system converter 3. In FIG. 2, reference numeral 21 is a decoding circuit, 22 is a main scanning direction enlargement / reduction circuit, 23 is a sub scanning direction enlargement / reduction circuit, 24 is an encoding circuit, and 25 is a DMA controller (hereinafter referred to as DMAC).

The DMAC 25 includes a decoding circuit 21, a main scanning direction enlargement / reduction circuit 22, a sub-scanning direction enlargement / reduction circuit 23,
The encoding circuit 24 issues a transfer request to the DMAC 25 to execute data transfer. In addition, the signal name in the figure is *
Those marked are active low level signals.

When the main control unit 1 sets the operation of each unit and then activates the unit, the decoding circuit 21 first causes the DMAC 25 to operate.
The transfer request DREQ0 is output to. When the DMAC 25 accepts the request, it outputs the data write signal WR * to the decoding circuit 21 together with the response signal DACK0 *. The address signal SYSADR is output to the image memory 2 via the bus driver 29 and the memory read signal MEMR * is output via the bus driver 26. As a result, the encoded data read from the image memory 2 is transferred to the bus driver 2
8 to the local bus DT33, and the decoding circuit 2
It is input to the in side of 1. When the output of the decoded first image data is ready, the decoding circuit 21 outputs the data transfer request signal a to the AND gate 30. AND
The other input b of the gate 30 is a data request from the enlargement / reduction circuit 22 in the main scanning direction. That is, AND gate 30
DMAC2 when the first image data is completed and the main scanning direction enlargement / reduction circuit 22 is ready for input.
The transfer request signal DREQ1 is output to the terminal 5. In this way, the decoding circuit 21 and the main scanning direction scaling circuit 22 are synchronized. When the DMAC 25 receives the request, the response signal DACK
1 * outputs a data read signal RD * to the decoding circuit 21, and outputs a data write signal W to the main scanning direction scaling circuit 22 together with the response signal DACK1 *.
By outputting R *, the first image data is output from the out side of the decoding circuit 21 and directly input to the in side of the main scanning direction scaling circuit 22.

FIG. 3 shows a block diagram of the enlargement / reduction circuit 22 in the main scanning direction. In FIG. 3, 41 is a P / S conversion circuit,
42 is an OR gate, 43 is an S / P conversion circuit, 44 is a flip-flop, and 45 is a clock control unit.

The P / S conversion circuit 41 decomposes the input first image data into bit units, and inputs the bit data to the OR gate 42 in synchronization with the clock A.
The flip-flop 44 latches the bit data output from the OR gate 42 in synchronism with the clock A, and again outputs O.
Input to the R gate 42. The bit data sent from the P / S conversion circuit 41 is ORed by a predetermined bit by the OR gate 42 and the flip-flop 44, and then input to the S / P conversion circuit 43 in synchronization with the clock B. The image data is output as first image data (hereinafter referred to as first image data X) that is enlarged or reduced in the main scanning direction. The clock control unit 45 generates a clock A and a clock B and controls enlargement or reduction in the main scanning direction. For example, the clock B has a waveform obtained by dividing the clock A by 3, and the clock A has a waveform obtained by dividing the clock B by 3 when the image is enlarged 3 times in the main scanning direction. A clock A generated by the clock control unit 45,
FIG. 4 shows a case where the clock B and the P / S conversion output and the S / P conversion output are reduced by 1/3 in the main scanning direction.
FIG. 5 shows a case where the magnification is 3 times. P / S conversion circuit 41, S / P conversion circuit 43, flip-flop 44
Operates at the rising edge of the clock.

Input / output to / from the enlargement / reduction circuit 22 in the main scanning direction is performed as follows. The main scanning direction enlarging / reducing circuit 22 performs the enlarging or reducing process with the magnification set by the main control unit 1 through the data bus DT33 in advance, and when the output of the first image data X is ready, the AND gate. The data transfer request signal c is output to 31. The other input of the AND gate 31 is a signal d indicating that the first image data X can be input to the sub-scanning direction enlargement / reduction circuit 23, and the signals c and d are output to the AND gate 31. When the DMAC2
5 to output the transfer request signal DREQ2. Thus, the main scanning direction scaling circuit 22 and the sub-scanning direction scaling circuit 23
Synchronize. When the DMAC 25 receives the request, it outputs a data read signal RD * to the main scanning direction enlargement / reduction circuit 22 together with the response signal DACK2 *, and the response signal D
By outputting the data write signal WR * and the address signal ADRS indicating the address of the line memory existing in the sub-scanning direction scaling circuit 23 to the sub-scanning direction scaling circuit 23 together with the ACK2 *, the first image data is output. X is output from the out side of the main scanning direction scaling circuit 22 and directly input to the in side of the sub scanning direction scaling circuit 23.

FIG. 6 shows one system of enlargement / reduction circuit 2 in the sub-scanning direction.
3 shows a block diagram of 3. In FIG. 6, reference numeral 51 is a memory control unit, 52 is a sub-scanning direction enlargement / reduction control unit, 53 is a dynamic random access memory (DRAM), 54 is a flip-flop, 55 is an OR gate, and 56, 57 and 58.
Is a bus driver. As a result, the first line worth of the first line enlarged or reduced by the main scanning direction enlargement / reduction circuit 22 is obtained.
A sub-scanning direction enlargement / reduction circuit 23 for processing the image data X is constructed.

The memory control unit 51 is connected to the main scanning direction enlargement / reduction circuit 22 on the A port side and to the encoding circuit 24 on the B port side, and generates control signals to the DRAM 53 in response to requests from the respective units. ..

The operation of reducing the magnification in the sub-scanning direction by 1/3 will be described. In this case, the operation is performed by taking the logical sum of three lines of the input first image data X and generating one line of the second image data. This first
The three lines of the image data X are referred to as first image data X1, first image data X2, and first image data X3, respectively. FIG. 7 shows the timing of signals output from the memory control unit 51 when the first image data X1 is input. FIG. 8 shows the timing of signals output from the memory control unit 51 when the first image data X2 and X3 are input.

The read-modify-write operation is possible on the A port side of the memory control section 51. If the input first image data X is the first image data X1, the sub-scanning direction enlargement / reduction control unit 52 outputs an OR signal.
L ', and the memory control unit 51 makes a REP in a normal cycle.
If LACE writing is performed and the image data is not the first image data X1, the sub-scanning direction enlargement / reduction control unit 52 sets the OR signal to “H”, the memory control unit 51 performs the read modify write operation, and the first image Second image data is generated by ORing the data X1, the first image data X2, and the first image data X3. O here
The R (logical sum) process is performed in order to prevent thinning and blurring of the reduced image. The operation on the A port side will be described. The memory control unit 51 is activated by the data transfer signal DACK2 * from the DMAC 25 and the data write signal WR *, and the DRAM 53 is provided with RAS *, CAS *, WE *, OE.
Output * and MA. Here, the MA signal is DMA
The address signal ADRS from C25 is multiplexed. The DRAM 53 is divided into two areas according to addresses, and when OR = “L”, the bus driver 57 outputs O from the memory control unit 51 as shown in FIG.
The first image data X1 is enabled at the falling edge of the EA * signal, and the first image data X1 is written in one area (area A) of the DRAM 53. The operation when OR = "H" is as follows, as shown in FIG. The flip-flop 54 receives the LAT signal from the memory control unit 51 at the rising timing and outputs the OE * signal to the DRAM 5.
The first image data X1 read from 3 is latched. The latched first image data X1 is O
First image data X input by the R circuit 55
2 is logically ORed with DR via the bus driver 56
It is written in the area A of AM53. Next, similarly, the logical sum of the first image data X2 and the first image data X3 is obtained, and the DRAM 53 is used as the second image data.
Is written in the area A. When the second image data reduced in this way is created, the area of the DRAM 53 is replaced, and the next first image data X1 is input to the other area (area B), and the same reduction is performed.

The B port side of the memory control unit 51 is DMA
The reduced second image data stored in the area A of the DRAM 53 is read and read at the same time as the input processing of the area B of the DRAM 53 is started by the response signal DACK3 * from the C25 and the data read signal RD *. The second image data is output to the encoding circuit 24 via the bus driver 58. When both the input processing and the output processing are completed, the areas are exchanged. Although not shown, an input request signal and an output request signal are output for data transfer control with the outside of the data. In this description,
Although the refresh operation of the DRAM 53 is omitted,
This can be easily achieved by using the C25 empty channel.

The operation of enlarging the magnification in the sub-scanning direction by 3 times will be described. The OR signal output from the sub-scanning direction enlargement / reduction control unit is fixed to “L”, and the first image data X which has been enlarged three times in the main scanning direction via the bus driver 57 remains in the area A of the DRAM 53. Written.
In the case of the enlargement processing, the first image data X becomes the second image data as it is. After that, the areas A and B are exchanged. The memory control unit 51 is the area B of the DRAM 53.
While writing the next first image data X to the
By repeatedly outputting the second image data stored in the area A of the AM 53 to the encoding circuit 24 three times, the magnification is tripled in the sub-scanning direction.

Input / output to / from the sub-scanning direction enlargement / reduction circuit 23 is performed as follows. The sub-scanning direction enlargement / reduction circuit 23 is ready to output the second image data enlarged or reduced by one line, and the AND gate 32.
The data transfer request signal e is output to. AND gate 32
The other input of is a signal f indicating that it is possible to input the second image data to the encoding circuit 24. When the signal e and the signal f are output to the AND gate 32, they are input to the DMAC 25. The transfer request signal DREQ3 is output. In this way, the sub-scanning direction enlargement / reduction circuit 23 and the encoding circuit 24 are synchronized. When the DMAC 25 receives a request, the enlargement / reduction circuit 2 in the sub-scanning direction together with the response signal DACK3 *
3 for outputting the data read signal RD * and the address signal ADRS indicating the address of the line memory existing in the sub-scanning direction enlargement / reduction circuit 23, and the data write signal WR to the encoding circuit 24 together with the response signal DACK3 *.
By outputting *, the second image data is output from the out side of the sub-scanning direction enlargement / reduction circuit 23 and directly input to the in side of the encoding circuit 24.

The encoding circuit 24 encodes the input second image data line by line. When the encoded data is completed to some extent, the encoding circuit 24 DMs
The transfer request signal DREQ4 is output to the AC25. DMA
When C25 receives the request, it outputs the data read signal RD * to the encoding circuit 24 together with the response signal DACK4 *, and outputs the address signal SYSADR to the image memory 2 via the bus driver 29. The encoded data output from the encoding circuit 24 via 28 is written in the image memory 2. In addition, the bus driver 29
Is the address signal ADRS output from the DMAC 25.
Is output to the system bus, and AND gate 3
3 to DMAC25 to DACK0 * or DACK4 *
Is enabled when is output. Bus driver 2
8 is the same, but the data flow direction is DACK0 *
Is output in the direction from SYSDT to DT, DA
When CK4 * is output, the direction is from DT to SYSDT.

As described above, the decoding circuit 21, the main scanning direction enlargement / reduction circuit 22, the sub-scanning direction enlargement / reduction circuit 23, and the encoding circuit 24 synchronize the two adjacent circuits when transmitting / receiving data. On the other hand, as soon as each circuit outputs data, the next data is input and pipeline parallel data processing for processing is performed.

Next, a second embodiment of the present invention will be described with reference to FIGS. Since only the sub-scanning direction enlargement / reduction circuit 23 is different from the first embodiment of the present invention, only the operation of the sub-scanning direction enlargement / reduction circuit 23 will be described. Although the sub-scanning direction enlargement / reduction circuit 23 has two systems in the second embodiment of the present invention, it may have three or more systems.

FIG. 9 shows two systems of enlargement / reduction circuit 2 in the sub-scanning direction.
3 shows a block diagram of 3. In FIG. 9, 61 is an input control unit, 62 is a memory control unit, 63 is an output control unit, and 64 and 7
1 is a flip-flop, 65 and 72 are multiplexers,
66 and 73 are OR gates, 67, 68, 70, 74 and 7
Reference numerals 5 and 77 are bus drivers, and 69 and 76 are DRAMs.

The sub-scanning direction enlargement / reduction circuit 23 is provided with two systems of blocks A and B for processing the one line of the first image data X enlarged or reduced by the main scanning direction enlargement / reduction circuit 22 and set. The memory control unit 62 outputs a signal P / Q * for managing the blocks A and B and instructing the operation of the input control unit 61 and the output control unit 63 according to the magnification, and alternately switches these blocks A and B. By using it, the enlargement / reduction processing in the sub-scanning direction and the output processing to the encoding circuit 24 are performed independently and in parallel in time.

The operation of reducing the magnification in the sub-scanning direction by 1/3 will be described. When the signal P / Q * output from the memory control unit 62 is'H ', for example, the block A is under the control of the input control unit 61 and the first image data X flows in. The block B is under the control of the output control unit 63, and the second image data enlarged or reduced in the sub-scanning direction is output from the block B to the encoding circuit 24. on the other hand,
The opposite is true when P / Q * is'L '. P / Q * is'
In the case of H ', the operation is to take the logical sum of three lines of the input first image data X and generate one line of the second image data. These three lines of the first image data X are respectively converted into the first image data X
1, the first image data X2, and the first image data X3. Bus driver 7 because P / Q * is'H '
4 and the bus driver 75 are disabled, and the first image data X reduced in the main scanning direction is the block A.
Flowing to the side. In this way, the block A is placed under the control of the input control unit 61. The input first image data X is the first
In the case of the image data X1, the data transfer control signal DACK2 * from the DMAC 25 and the data write signal WR
When * becomes active, the input control unit 61 enables the bus driver 68 and outputs the address signal MAA, the memory control signals RASA *, CASA *, and the memory write signal WEA * based on the address signal ADRS input from the DMAC 25. To do. These signals are input to the DRAM 69 via the multiplexer 65, and the first image data X1 is written in the DRAM 69. This operation is performed for all the first image data X1.
Next, when the first image data X2 is input, the input control unit 61 performs a read modify write operation on the DRAM 69. That is, the first image data X1 once stored in the DRAM 69 is read and latched by the flip-flop 64. The OR gate 66 calculates the logical sum of the first image data X2 input from the enlargement / reduction circuit 22 in the main scanning direction, enables the bus driver 67, and writes it in the same address in the DRAM 69 again. By performing this operation on all the input first image data X2, the first image data X1
One line of the first image data X, which is the logical sum of the first image data X2 and the first image data X2, is stored in the DRAM 69. By performing the same processing on the first image data X3 as on the first image data X2, D
The first image data X1, X2, X3 is stored in the RAM 69.
One line of the second image data obtained by taking the logical sum of is completed. The timing of the signal output by the input control unit 61 when inputting the first image data X1 is shown in FIG. 7, and the signal timing output by the input control unit 61 when inputting the first image data X2, X3 is shown in FIG. The timing of is shown. When the second image data reduced to ⅓ is completed as described above, the memory control unit 62 sets the P / Q * signal to "L" to switch the blocks A and B in a circuit manner. That is, the block B is placed under the control of the input control unit 61, and the block A is placed under the control of the output control unit 63. After that, the output control unit outputs DACK3 *, R from the DMAC 25.
When the D * signal becomes active, the address signal MAB, the memory control signals RASB *, CASB *, the memory read signal OE based on the input address signal ADRS.
Output B *. These signals are input to the DRAM 69 via the multiplexer 65, and the second signal from the DRAM 69 is input.
Image data of is read. P / Q * signal is'
Since it is L ', the bus driver 70 is enabled and DR
The second image data read from the AM 69 is output to the encoding circuit 24 via the bus driver 70. On the other hand, at this time, the input control unit 61 performs the reduction in the sub-scanning direction by using the block B under the control. When the reduction processing is completed and the output processing is completed, the memory control unit 62 sets the P / Q * signal to “H” again, and the blocks A and B are exchanged. By repeating the above processing, the reduction processing in the sub-scanning direction and the output processing to the encoding circuit 24 are performed independently and in parallel in time.

The operation of enlarging the magnification in the sub-scanning direction by 3 will be described. If P / Q * is'H ', the block A is placed under the control of the input control unit 61, and the input control unit 61 enlarges the image by 3 times in the main scanning direction via the bus driver 68. The data X is written in the DRAM 69 of the block A as it is. In the case of the enlargement processing, the first image data X becomes the second image data as it is. After that, the memory control unit 62 sets the P / Q * signal to “L”, the blocks A and B are switched in a circuit manner, the block A is under the control of the output control unit 63, and the block B is under the control of the input control 61. Put it in. The input control unit 61 is D in block B
While the next first image data X is written to the RAM 76, the output control unit 63 repeatedly outputs the second image data in the DRAM 69 of the block A to the encoding circuit 24 three times, so that the second scanning direction is performed in the sub-scanning direction. Expand 3 times. By repeating the above processing, the enlargement processing in the sub-scanning direction and the output processing to the encoding circuit 24 are performed independently and in parallel in time.

Input / output to / from the sub-scanning direction enlargement / reduction circuit 23 is performed as follows. The sub-scanning direction enlargement / reduction circuit 23 outputs the data transfer request signal e to the AND gate 32 when the output of the second image data enlarged or reduced by one line is ready. The other input of the AND gate 32 is a signal f indicating that it is possible to input the second image data to the encoding circuit 24. When the signal e and the signal f are output to the AND gate 32, , D
The transfer request signal DREQ3 is output to the MAC 25. In this way, the sub-scanning direction enlargement / reduction circuit 23 and the encoding circuit 24 are synchronized. When the DMAC 25 receives the request, the response signal D
The data read signal RD * and the address signal ADRS indicating the address of the line memory existing in the sub-scanning direction enlargement / reduction circuit 23 are output to the sub-scanning direction enlargement / reduction circuit 23 together with the ACK3 *, and encoded together with the response signal DACK3 *. By outputting the data write signal WR * to the circuit 24, the second image data is output from the out side of the sub-scanning direction enlargement / reduction circuit 23, and the encoding circuit 24 is output.
Is directly input to the in side of.

[0038]

According to the present invention, the decoding circuit, the scaling circuit, and the coding circuit operate in a pipeline manner, so that the speed can be increased and the memory can be significantly reduced. Further, if a plurality of systems of scaling circuits are used, since each system is independent, it is possible to achieve higher speed than when one system of scaling circuits is used. Furthermore, since the system bus is used only for input / output of encoded data, size conversion and encoding method conversion can be performed without increasing the system bus traffic, especially for back jobs of the system such as communication processing. It is most suitable for operation.

[Brief description of drawings]

FIG. 1 is an overall block diagram of an image size conversion device according to an embodiment of the present invention.

FIG. 2 is a block diagram of an image size conversion unit according to an embodiment of the present invention.

FIG. 3 is a block diagram of a main scanning direction enlargement / reduction circuit according to an embodiment of the present invention.

FIG. 4 is a signal waveform diagram of an example of the present invention.

FIG. 5 is a signal waveform diagram of an example of the present invention.

FIG. 6 is a block diagram of one system of enlargement / reduction circuit in the sub-scanning direction according to an embodiment of the present invention.

FIG. 7 is a signal waveform diagram of an example of the present invention.

FIG. 8 is a signal waveform diagram of an example of the present invention.

FIG. 9 is a block diagram of a two-system main-scanning direction enlargement / reduction circuit according to an embodiment of the present invention.

FIG. 10 is a flowchart of a conventional image size / encoding method conversion circuit.

[Explanation of symbols]

 1 Main Control Unit 2 Image Memory 3 Image Size Conversion Unit 4 Image Scanner 5 Laser Printer 6 Input / Output Control Unit 7 Optical Disc Interface 8 Optical Disc Drive 9 Communication Control Unit 10 Compression / Expansion Unit 11 Display Control Unit 12 Display Memory 13 CRT 21 Decoding circuit 22 Main scanning direction scaling circuit 23 Sub scanning direction scaling circuit 24 Encoding circuit 25 DMA controller 26 Bus driver 27 Bus driver 28 Bus driver 29 Bus driver 30 AND gate 31 AND gate 32 AND gate 33 AND Gate 41 P / S conversion circuit 42 OR gate 43 S / P conversion circuit 44 flip-flop 45 clock control unit 51 memory control unit 52 sub-scanning direction enlargement / reduction control unit 53 DRAM 54 flip-flop 55 OR gate 56 bar Driver 57 Bus driver 58 Bus driver 61 Input controller 62 Memory controller 63 Output controller 64 Flip-flop 65 Multiplexer 66 OR gate 67 Bus driver 68 Bus driver 69 DRAM 70 Bus driver 71 Flip-flop 72 Multiplexer 73 OR gate 74 Bus driver 75 bus driver 76 DRAM 77 bus driver

Claims (2)

[Claims] 1. A decoding circuit for decoding encoded data, a one-system enlarging circuit for enlarging the decoded first image data, and an enlarged second image data. Encoding circuit for encoding, first control means for inputting the encoded data to the decoding circuit for decoding, first inputting the first image data to the enlargement circuit for enlargement The second control means, the third control means for successively inputting the second image data to the encoding circuit and encoding the same, and the first, second and third control means are synchronized. Image information conversion circuit having means for operating in parallel. 2. A decoding circuit for decoding encoded data, a plurality of systems of scaling circuits for scaling up or down the decoded first image data, scaled up or down. An encoding circuit for encoding the second image data, first control means for inputting the encoded data to the decoding circuit for decoding, and sequentially enlarging or reducing the first image data. Second control means for inputting to the circuit for enlarging or reducing, third control means for successively inputting the second image data to the encoding circuit for encoding, and the first and second. And an image information conversion circuit having means for operating the third control means in parallel in synchronization.