JPH05304490A - Tuning circuit for electronic tuner - Google Patents

Abstract

PURPOSE:To prevent the higher harmonic of a reference frequency oscillation circuit from diving into the antenna of a receiver and noise from getting mixed with signals during reception by PLL tuning only for a short time at the time of tuning and at appropriate timing thereafter. CONSTITUTION:An electronic tuner is provided with a PLL controller 4 for PLL tuning at the time of the tuning, voltage holding circuit 7 for holding a control voltage controlled by the PLL controller 4 after tuning and comparator 11 for comparing detection output with a reference voltage and detecting that the voltage exceeds the prescribed level. Then, tuning is performed at the prescribed voltage obtained at the voltage holding circuit 7 after tuning and above- mentioned conrol voltage is corrected by the signal obtained at the comparator 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tuning circuit in an electronic tuner such as a radio receiver for electronic tuning.

[0002]

2. Description of the Related Art Generally, a radio receiver or the like that performs electronic tuning often performs tuning by a PLL system. Such a PLL tuning circuit sets the data of the frequency division ratio output from the microcomputer to a programmable counter which is a part of the PLL controller, and outputs the output frequency of the programmable counter and the reference oscillation frequency of the reference frequency oscillation circuit. , The phase comparison circuit that is a part of the PLL controller performs comparison, and controls the oscillation frequency control voltage (V _t ) of the local oscillation circuit through the low-pass filter. The tuning frequency is the reference oscillation. It is controlled at the same level as the frequency accuracy. Since the reference oscillation frequency is oscillated by the crystal, very accurate tuning is possible.

[0003]

However, it is necessary to constantly oscillate the reference oscillation frequency in the reference frequency oscillation circuit, and harmonics of this oscillation jump into the antenna of the receiver,
This often causes noise to be mixed into the signal being received.

[0004]

In order to solve the above problems, the present invention performs PLL tuning at the time of tuning in an electronic tuner which performs tuning by varying a control voltage for controlling a local oscillation circuit. It is characterized by having a PLL control means and a voltage holding means for holding a control voltage controlled by the PLL control means by a voltage holding circuit after tuning.

Further, the PLL control means tunes the tuning voltage applied to the local oscillating circuit at a constant value for a predetermined time after the PLL tuning, and tunes again after a predetermined time.
It is characterized by synchronizing.

Furthermore, in the electronic tuner, the detection output is detected while the signal is being received by the electronic tuner section, and when the detection output becomes a certain level or more as compared with the reference voltage, the PLL control means is used. PL
The L-tuning is performed to correct the control voltage for controlling the local oscillation circuit.

[0007]

In the tuning circuit of the electronic tuner of the present invention, the operation of the PLL control means may be stopped during normal operation of a radio receiver or the like, and noise may be mixed into the receiver due to harmonics of the oscillation frequency of the reference frequency oscillation circuit. Disappear.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a tuning circuit in an electronic tuner according to the present invention will be described with reference to FIG. 1. Reference numeral 1 is a tuning unit for instructing a microcomputer 2 to tune, and 3 is an ON signal from the microcomputer 2.
A reference frequency oscillating circuit which operates by a / OFF signal and outputs a reference oscillating frequency, 4 is a PLL controller which operates by frequency division data of a programmable counter from the microcomputer 2 and outputs a control signal, and 5 is the PLL controller 4 is a low-pass filter that supplies a control voltage from the electronic switch SW1 to the electronic switch SW1, and the electronic switch SW1 is an electronic switch that switches with a signal from the microcomputer 2 and supplies a control voltage to a local oscillation circuit (not shown) of the electronic tuner unit 8. ..

Reference numeral SW3. SW4 is microcomputer 2 respectively
To a set signal and a reset signal, and a voltage holding circuit 7 is constituted by a buffer 6 connected between the electronic switches SW3 and SW4 via a grounding capacitor C. Reference numeral SW2 is an electronic switch for switching the holding output of the control voltage of the buffer 6 with a signal from the microcomputer 2 and supplying it to the local oscillation circuit of the electronic tuner unit 8.

The electronic tuner section 8 is composed of a local oscillation circuit that oscillates when supplied with a control voltage, a mixing circuit connected to the antenna through the front end, a detection circuit, and the like.
The detection output is obtained at the output terminal 9. The output terminal 9 is connected to the microcomputer 2 via a comparator 11 which compares the detection output voltage with the reference voltage supplied to the terminal 10.
Further, a mute transistor TR for muting the detection output by a mute control signal from the microcomputer 2 is connected to the output terminal 9.

In the tuning circuit of the electronic tuner having the above structure, first, when the microcomputer 2 receives the tuning instruction signal S _I from the tuning unit 1 at the time of tuning, the detection output of the electronic tuner unit 8 is muted by the transistor TR. Next, the divided data signal S _D is supplied from the microcomputer 2 to the program counter in the PLL controller, and the counter output and the reference oscillation frequency output of the reference frequency oscillation circuit 3 are obtained by the phase comparator in the PLL controller 4. The control voltage (V _t ) is controlled so that the local oscillation output of the local oscillation circuit in the electronic tuner unit 8 has a specified frequency.

During the PLL tuning, the electronic switch SW1 is turned on (conducting), SW2 is turned off (non-conducting), and the control voltage (V _t ) is supplied to the electronic tuner unit 8. When the PLL loop locks and tuning is completed, P
The LL controller 4 sends the lock completion signal S _L to the microcomputer 2
To complete the tuning by the PLL, and the mute control signal S _M from the microcomputer 2 is supplied to the mute transistor TR.
Is turned off and the muting of the detection output of the electronic tuner unit 8 is released, and the normal reception state is set. Since the detection output is muted at the time of tuning, noise due to the reference oscillation of the reference frequency oscillation circuit 3 cannot be heard.

Here, the control voltage (V _t ) line is shown in FIG.
As shown in (a) and (b), when the electronic switch SW1 is disconnected from the low-pass filter 5, the electronic switch SW2 is connected to the output of the voltage holding circuit 7 for the control voltage (V _t ) instead. There is. Just before the voltage holding circuit 7 switches the electronic switches SW1 and SW2,
As shown in FIG. 2C, the set signal S from the microcomputer 2
_{In S} , the voltage value of the control voltage (V _t ) is charged in the capacitor C and held through the electronic switch SW3. Immediately after that
The control voltage (V
The held output of ( _t ) is supplied to the electronic tuner unit 8, and the PLL
Reception can be performed in the same way as when tuning.

However, as time goes by, the deviation of the frequency due to the constant change of the circuit components of the local oscillation circuit of the electronic tuner section 8 due to the change of the ambient temperature of the receiver, the deviation of the output voltage held by the voltage holding circuit 7, etc. There is a possibility that the synchronization deviation due to

For example, in order to correct the misalignment of the local oscillator circuit, the PLL is set at an appropriate timing every fixed time.
The control voltage (V _t ) is corrected by retuning. P
Retuning by LL is completed in a few milliseconds, but since it is normally performed during reception, noise during PLL tuning may be heard.

In this tuning circuit, the detection output level is detected, for example, by 3 after the PLL tuning shown in FIGS. 3 (a) and 3 (b).
It starts after a lapse of T ₁ hour of about 0 minutes. That is, compared to the level of the reference voltage supplied to the terminal 10 by the comparator 11, when a detection output higher than the reference level, and supplies the re-tuning timing signal S _t shown in FIG. 3 (c) to the microcomputer 2. After the detection output level is detected, for example, 10
If the output of the comparator 11 does not become "High" even after a lapse of T ₂ time of about a minute, PLL tuning is forcibly performed.

The microcomputer 2 switches the electronic switches SW1 and SW2 in accordance with the re-tuning timing signal S _t to switch the PLL.
Synchronize. Further, at this time, and supplies a reset signal S _R to the electronic switch SW4 for voltage holding circuit 7.

[0018]

Since the tuning circuit in the electronic tuner according to the present invention performs the PLL tuning only for a short time at the time of channel selection and at an appropriate timing thereafter, the harmonic of the reference frequency oscillation circuit is transmitted to the antenna of the receiver. There is almost no possibility that noise will be mixed into the signal being received. Further, since re-tuning by the PLL during reception is performed when a large sound with deep modulation is produced, that is, when the detection output is high, noise is masked and is inconspicuous in the sense of hearing.

[Brief description of drawings]

FIG. 1 shows a schematic circuit diagram of a tuning circuit in an electronic tuner of the present invention.

FIG. 2 shows a timing diagram of conduction and non-conduction of an electronic switch in the present tuning circuit.

FIG. 3 shows a timing diagram of correction of a control voltage to an electronic tuner section in the present tuning circuit.

[Explanation of symbols]

 1 tuning unit 2 microcomputer 3 reference frequency oscillation circuit 4 PLL controller 5 low-pass filter 6 buffer 7 control voltage holding circuit 8 electronic tuner unit

Claims (3)

[Claims] 1. An electronic tuner for performing tuning by varying a control voltage for controlling a local oscillation circuit, comprising: PLL control means for performing PLL tuning during tuning; and control voltage controlled by the PLL control means after tuning. And a voltage holding means for holding the voltage by a voltage holding circuit. 2. The P by the PLL control means
2. The tuning circuit for an electronic tuner according to claim 1, wherein tuning is performed while the tuning voltage applied to the local oscillation circuit is kept constant for a predetermined time after the LL tuning, and PLL tuning is performed again after the predetermined time. 3. An electronic tuner section detects a detection output during reception of a signal, and when the detected output exceeds a certain level as compared with a reference voltage of the detection output, PLL tuning is performed by the PLL control means for local oscillation. Tuning circuit in an electronic tuner according to claim 1, characterized in that it modifies the control voltage for controlling the circuit.