JPH05303448A - Signal output processing circuit - Google Patents

Abstract

PURPOSE:To allow this signal output processing circuit to flexibly correspond to any circuit constitution out of a system for holding an output level obtained immediately before resetting a CPU and a system for rejecting an output at the time of resetting the CPU by providing the processing circuit with an output voltage holding selecting data buffer. CONSTITUTION:A signal output circuit module 2 provided with a data buffer 23 for entering output holding selecting data and other parts latches one-bit data in its internal flip flops 25, 26 at the time of inputting the output holding data and self-holds the latched data at the time of entering the output holding data, so that the gate of an output buffer 213 can be held at an active state even when the CPU 11 is reset. When the circuit 2 enters output unholding data, the gate of the buffer 214 is inactivated without self-holding the one-bit date in the flip flops 25, 26. Thus the gate of the buffer 214 can be switched to an active state or an inactive state even at the time of resetting the CPU by setting up selection data to '1' or '0'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal output processing circuit which outputs a digital signal or an analog signal used in combination with a microcomputer.

[0002]

2. Description of the Related Art Generally, in a control device using a microcomputer, a digital signal output processing circuit for outputting pressurization or non-pressurization of an external power source also has an analog signal output processing for outputting positive and negative analog voltage signals. Circuit too
Since the CPU controls the control, the CPU
When is reset, the level of the data bus is in a floating state, that is, neither the "1" level nor the "0" level, and the digital signal output processing circuit for converting and outputting the data of the CPU also performs the analog signal output processing. The circuit also becomes indefinite. Therefore, in order to avoid this, it is necessary to select one of the following two methods according to the system requirements.

(1) When the CPU is reset, the output is cut off.

That is, in the case of digital output, the output is turned off, and in the case of analog output, there is no output voltage (0V).

(2) When the CPU is reset, the output level immediately before the reset is held.

In the conventional signal output processing circuit, the demand for the output level at the time of CPU reset differs depending on the system. Therefore, either method is selected to configure the circuit, or both types of circuits are prepared together. In advance, one of the methods is selectively set by using a switch or the like.

[0007]

However, in such a conventional signal output processing circuit, in the former case, the circuit configuration must be changed in accordance with the above methods (1) and (2), which is flexible. There was a problem that there was no nature. In the latter case, the user has to select one of the methods (1) and (2) by operating the switches provided, so that it is difficult for a beginner to understand and the setting is difficult. ..

The present invention has been made in view of the above conventional problems, and when the CPU is reset, the circuit configuration is either a method of holding the output level immediately before the reset of the CPU or a method of cutting off the output. It is an object of the present invention to provide a signal output processing circuit that can flexibly cope with the above.

[0009]

SUMMARY OF THE INVENTION The present invention provides a CPU for outputting an address and data, and a signal output circuit for taking in the address and data from the CPU and outputting a digital signal or an analog signal held in an output buffer. In the signal output processing circuit including
Address buffer that takes in the address from U and CP
Based on the data buffer that takes in the data from U, the output voltage holding selection data buffer that takes in the output voltage holding selection data indicating whether to hold the output voltage level when the CPU is reset, and the output voltage holding selection data
And a latch circuit that holds the gate of the output buffer active until the power is turned off.

[0010]

In the signal output processing circuit of the present invention, the output voltage level is held when the CPU is reset by providing the output voltage holding selection data buffer in addition to the address buffer and the data buffer for fetching the address and data from the CPU. The output voltage holding selection data indicating whether or not is taken into the output voltage holding selection data buffer, and if the output voltage holding selection data is the selection data that should hold the output voltage level up to that time when the CPU is reset,
If the selection data is such that the gate of the output buffer is kept active with respect to the latch circuit and conversely the output voltage is to be cut off when the CPU is reset, the output of the output buffer is output at the same time as the power is cut off without operating the latch circuit. Set so that the voltage is cut off.

Thus, with one type of circuit configuration, the gate of the output buffer of the signal output circuit can be automatically set to active / inactive at the time of CPU reset based on the output voltage holding selection data from the CPU. It can be made flexible.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows a circuit configuration of an embodiment of the present invention. A CPU module 1 for outputting addresses and data, and a signal output circuit for taking in these addresses and data and outputting a digital signal or an analog signal. It is composed of a module 2 and an address bus 3 and a data bus 4 which connect the modules 1 and 2 to each other.

The CPU module 1 includes a CPU 1
1, the address buffer 12 and the data buffer 13
Is provided.

Further, the signal output circuit module 2 has a CP
An address buffer 21 for fetching an address sent from the U module 1 on the address bus 3 and a CPU
A data buffer 22 for fetching data sent from the module 1 on the data bus 4 and a 1-bit output voltage sent from the CPU module 1 on the data bus 4 and indicating whether or not to hold the output. A data buffer 23 that fetches hold selection data, a decoder 24 that detects a command EN (enable) whether to output from a specific address and a command OHLD that holds an output level at CPU reset, and Flip-flop 2 that self-holds the output output voltage holding command
5, 26, 27 and the gate groups 28 to 21 associated therewith
3, an output buffer 214 having a gate for outputting or disconnecting an output, and a conversion circuit for performing level conversion of an output digital signal or D / A conversion to output a digital signal or an analog signal to the outside. 215 is provided.

Next, the operation of the signal output processing circuit having the above configuration will be described.

The CPU module 1 side gives the following instructions to the signal output circuit module 2 in accordance with the system request.

(A) The CPU module 1 adds one bit of the data bus 4 with output voltage holding selection data "1" or "0" for holding or disconnecting the output when the CPU is reset, and outputs the signal output circuit. Access module 2.

(B) When the signal output circuit module 2 takes in the output holding data, it latches this 1-bit data in the internal flip-flops 25 and 26, and holds it by itself, so that the CPU 11 is reset. The gate of output buffer 214 remains active.

(C) The signal output circuit module 2 does not self-hold the 1-bit data in the internal flip-flops 25 and 26 when it takes in the data of which the output is not held, and when the CPU 11 is reset, the gate of the output buffer 214 is set. Make it inactive.

In this way, by setting "1" or "0" in the output voltage holding selection data from the CPU module 1 side, the gate of the output buffer 214 is switched to be held active or inactive even when the CPU is reset. Automatically.

The above operation will be described in more detail.

(I) When holding output The CPU module 1 sets "1" in 1 bit of the data bus 4.
And the signal output circuit module 2 is accessed, the output SEL of the decoder 24 becomes "1", and the NAN
The output of the D gate 28 becomes "0". Since the flip-flop 25 is reset when the power is turned on and its Q-output is "1", the output of the AND gate 29 is "1", and the D input of the flip-flop 25 via the OR gate 210 is It becomes "1". Immediately after that, at the rising edge of the CLK input, the D input is latched, the Q-output becomes "0", and the output level of the flip-flop 25 is self-held by the OR gate 210.

On the other hand, when the CPU module 1 puts the output data on the data bus 4 to access the signal output circuit module 2 once, the output "1" of the decoder 24 is latched in the flip-flop 27 and the output of the NOR gate 211 is "1". 0 ”, and the output data fetched through the data buffer 22 is transferred from the output buffer 214 to the conversion circuit 215.
Is output to the outside.

Further, since the Q-output of the flip-flop 215 is self-held at "0", when the latch signal EN of the output of the decoder 24 becomes "1", the AND gate 2
The output T of 12 is "1", the output of the OR gate 213 is also "1", the Q-output of the flip-flop 26 is latched to "0" at the rising edge of the CLK input immediately after that, and the OR gate 213 self-holds this. It And at this time,
Since the NOT input of NOR gate 211 is fixed at "0", the gate of output buffer 214 remains active as long as the power supply is alive.

As a result, the flip-flop 27 is reset by the reset input, and the output level immediately before the reset can be held even if the EN signal becomes "0".

(Ii) When no output is held: The CPU module 1 writes "0" in 1 bit of the data bus 4.
When you access the signal output circuit module 2 by writing
The output of the NAND gate 28 becomes “1”, the output of the AND gate 29 becomes “0”, the output of the OR gate 210 becomes “0” via the data buffer 23, and the flip-flop 25
Of the AND gate 212 and the output of the OR gate 213 are both "0", and the Q-output of the flip-flop 26 is also "1".

As a result, when the CPU module 1 once accesses the signal output circuit module 2, the EN signal is latched at "1" and the gate of the output buffer 214 is held active, but when the reset signal is input,
The EN signal becomes "0", the gate of the output buffer 214 becomes inactive, and the output is cut off.

In this way, it is possible to set whether or not the output voltage level is retained at the time of resetting the CPU by software according to the system request while using the common module, and even if the request changes, the circuit It is possible to flexibly deal with software changes without making any changes.

Since both of the methods (1) and (2) are set after the power is turned on, it is possible to prevent problems due to erroneous settings in advance as compared with the setting method using a switch, and the power is turned on. Occasionally, false output can also be prevented by not activating the gate of the output buffer until the first access.

The present invention is not limited to the above embodiment, and the CPU reset signal is used as it is as the output voltage holding selection data for the data buffer 23, and the output buffer 214 is reset when the CPU is reset. It can also be However, in this case, if the signal output circuit module 2 is a positive / negative analog signal output circuit, a negative full voltage output is produced at reset.

[0032]

As described above, according to the present invention, the CPU
By providing an output voltage holding selection data buffer in addition to an address buffer and a data buffer for fetching the address and data from, output voltage holding selection data indicating whether or not to hold the output voltage level at the time of CPU reset is output. Capture to voltage hold selection data buffer,
If this output voltage holding selection data is the selection data that should hold the output voltage level up to that time when the CPU is reset, the latch circuit is made to hold the gate of the output buffer active, and conversely when the CPU is reset. If the selected data is to be disconnected, the latch circuit is not activated and the output voltage of the output buffer is set to be disconnected at the same time when the power is cut off. Therefore, with one common circuit configuration, Only by changing the software, the gate of the output buffer of the signal output circuit can be set to active / inactive automatically when the CPU is reset based on the output voltage holding selection data from the CPU, and the demand changes. However, it is possible to flexibly deal with it by only changing the software without changing the circuit.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of an embodiment of the present invention.

[Explanation of symbols]

 1 CPU module 2 signal output circuit module 11 CPU 12 address buffer 13 data buffer 21 address buffer 22 data buffer 23 data buffer 24 decoder 25-27 flip-flop 28 NAND gate 29 AND gate 210 OR gate 211 NOR gate 212 AND gate 213 OR gate 214 output buffer 215 conversion circuit

Claims (1)

[Claims] 1. A CPU for outputting an address and data
And take in the address and data from this CPU,
In a signal output processing circuit including a signal output circuit that outputs a digital signal or an analog signal held in an output buffer, an address buffer that takes in an address from the CPU, a data buffer that takes in data from the CPU, An output voltage holding selection data buffer that takes in output voltage holding selection data indicating whether or not to hold the output voltage level when the CPU is reset, and an output buffer gate is active based on the output voltage holding selection data until the power is turned off. And a latch circuit for holding the signal output circuit.