JPH0530229B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to an integrated circuit tester for testing an integrated circuit to which a scan-in/out method is applied.

(2) Technical background The scan-in-out method is one of the methods to facilitate the testing of theoretical ICs containing complex sequential circuits.

The scan-in-out method attempts to facilitate testing by operating all flip-flops in the circuit as serial shift registers. This will be explained using a conceptual diagram of the scan-in/out method shown in FIG. In Figure 1, IC is an integrated circuit, L ₁ to _{L 3} are combinational logic circuits, FF _{1, 2} are flip-flops, I ₁ to _{I 5} are input signals, O ₁ to _{O 5} are output signals, and CLK is a System clock, SD is scan data, SP is scan pulse, SDO is scan data output, D is data input terminal, Q is data output terminal, C is system clock input terminal, SC is scan pulse input terminal,
SI is a scan data input terminal, and SO is a scan data output terminal.

In ICs that use the scan-in/out method,
Each flip-flop FF in the circuit is configured to function as a shift register in the scan-in/out mode. For testing,
First, when scan data SD and scan pulse SP are input, each scan data is serially input.
Shift to FF and set each FF in the circuit to an arbitrary state. Next, input a test pattern to I ₁ to _{I 5} and apply the system clock CLK to operate the circuit, and monitor the output O ₁ to O ₅ or the state of each FF by scanning out, thereby checking the IC. A test will be conducted.

(3) Conventional technology and problems The above scan-in/out method was adopted.
An integrated circuit tester that tests an IC uses scan data to set the FFs in the circuit as test data in advance and to inspect the state of the FFs.
It is necessary to store test patterns for operating the circuit.

FIG. 2 is a conceptual diagram showing the storage state of test data in a conventional integrated circuit tester. For the sake of simplicity, only the input signal will be explained as an example. In the diagram
ADD is memory address, SD is scan data,
SP is a scan pulse, and I ₁ to I ₈ are inspection patterns. Note that when SP is "1", a scan pulse is input and the contents of the FF are shifted, and when SP is "0", it indicates that no scan pulse is input.

As is clear from the figure, the number of bits in one word of test data depends on the number of input/output pins of the integrated circuit.
The required memory capacity is the number of scan data,
That is, it largely depends on the number of flip-flops in the circuit. Previously, one address per address.
Therefore, the address where the scan data was stored had an unused memory area indicated by diagonal lines, and the larger the integrated circuit, the lower the memory usage efficiency. . Furthermore, if a sufficiently reliable test was to be performed, a large amount of memory was required.

(4) Purpose of the Invention The purpose of the present invention is to solve the above problems and enable highly reliable testing with a small memory capacity.

(5) Structure of the Invention The above object is to provide an integrated circuit tester that tests an integrated circuit by a scan-in-out method using a flip-flop in the integrated circuit based on test data stored in a memory. The integrated circuit tester generates a test pattern for setting input/output conditions of the integrated circuit at a predetermined address, which is different from the predetermined address, for an area in which a predetermined number of bits are stored corresponding to the address. At the address, n-bit scan data for setting and testing the state of the flip-flop in the integrated circuit is stored, and at each address, a flag bit is stored that determines whether the test data is the scan data or the test pattern. inputting the test pattern read from the memory in a state in which the flag bit indicates the test pattern into the integrated circuit in parallel;
The n-bit scan data read from the memory when the flag bit indicates the scan data;
This is achieved by having means for inputting data to a flip-flop in the integrated circuit at a speed n times the input speed of the test pattern.

(6) Examples of the invention The present invention will be explained in detail using the following figures. Third
The figure is an embodiment of the present invention, and is a diagram showing a storage state of test data on a memory. FB in the figure indicates a flag bit, and other symbols are the same as in FIG.

In this embodiment, as shown in the figure, two bits of scan data are stored in one word, and when scan data SD is input, the cycle is 1/2 of the cycle of inputting inspection patterns _I1 to _I8 . I am trying to input the scan data SD with . Furthermore, Scan Pulse SP
When is “1”, two shift pulses are output,
The contents of FF are shifted by 2. On the other hand, SP is “0”
Shifting is not performed when .

Therefore, even though the reading cycle of data from the memory is the same as the conventional one, since two FFs are set in one reading cycle, the time required to set the scan data SD is halved compared to the conventional one. In addition, conventionally, signals to be set to even-numbered FFs are stored in the area where _I1 was stored, and the flag bit FB is used to determine whether scan data or test patterns are stored. The unused memory area is reduced, and the same tests as in the past can be performed with less memory capacity.

FIG. 4 is a block diagram of an integrated circuit tester according to the present invention, FIG. 5 is a timing diagram for explaining the operation of FIG. 4, and FIG. 6 is a conventional scan data input timing a and a scan data according to the present invention. FIG. 7 is a timing diagram showing the relationship between data input timings b.

In the figure, TG is a timing generator that generates clock signals a at various timings. CS is the clock selector and timing generator
Select one of the clocks output from the TG or use the logic of multiple clocks to create a signal for controlling the timing of inputting the test pattern and scan data. F is a formatter which controls the timing of inputting the test data read from the memory M to the integrated circuit IC in accordance with the output of the clock selector CS.

For example, if the timing signal input to the formatter F ₃ has a waveform like e, and if F ₃ outputs data read out from the memory M, for example "1", at the rising edge of the timing signal e, then in this case, one cycle is generated. "1" is continuously input to _I1 during this period.
On the other hand, if the timing signal f is input to the formatter _F4 and the data in the memory M is "1", "1" is input to _I2 from the middle of one cycle. This is because even when applying signals of the same level, tests may be performed by changing the input timing of the signals.

The operation of FIG. 4 will be explained below in conjunction with FIG. 3.

First, when the data at memory address ADD0 is read, the flag bit FB is "0", so the input of scan data SD from formatter _F1 and scan pulse from formatter _F2 to the IC is prohibited, and the formatter is The test pattern is input to the IC from ₃ , _F4 , and so on. Next, in ADD1-3, the scan data SD is read out and the flip-flops in the IC are set. At this time,
Since FB is “1”, the formats F ₁ and F ₂ are
becomes operational. For Formatsuta F ₁ , signal b,
The timing signal shown in FIG. 5 is created using c, and the scan data SD stored in the 2nd and 3rd bits of the memory M is input to the IC in accordance with this timing signal. On the other hand, the data stored in the 1st bit of memory in Forumatsuta F ₂ is “1”
If so, input the timing signal d to the IC as a shift clock. When the setting of data to each flip-flop is completed in this way, the test pattern at memory address 4 is transferred to the formatters F ₃ , F ₄ , etc.
The signal is input to the IC via the IC and tested.
At this time, since FB is "0", input of scan data SD and scan pulse SP from F ₁ and F ₂ is prohibited. Thereafter, tests using various test patterns are performed in the same manner.

Therefore, in the present invention, the inspection patterns I ₁ to _{I 8}
The input timing is the same as before, but as shown in Figure 6, the time required to set the conventional scan data to each flip-flop is halved.
becomes. Furthermore, as is clear from FIG. 3, memory usage efficiency is also improved.

In addition, in the above embodiment, 2 bits per address
I have memorized the scan data for but it will be tested.
The faster the IC operation speed, the more bits it can store,
It goes without saying that two or more flip-flops may be set in one period.

(7) Effects of the invention As explained above, according to the present invention, highly reliable tests can be performed with a small memory capacity, and scan data can be set in a short time, making it possible to speed up tests. It is.

For example, when a 20 MHz tester is used in the above embodiment, according to the present invention, a test equivalent to a 40 MHz tester can be performed.

[Brief explanation of the drawing]

Fig. 1 is a conceptual diagram for explaining the scan-in/out method, Fig. 2 is a conceptual diagram showing the storage state of test data in a conventional integrated circuit tester, and Fig. 3 is an embodiment of the present invention. A conceptual diagram showing the storage state of test data in memory; FIG. 4 is a block diagram of an integrated circuit tester which is an embodiment of the present invention;
FIG. 5 is a timing diagram for explaining the operation of FIG. 4, and FIG. 6 is a timing diagram showing the relationship between the conventional scan data input timing a and the scan data input timing b according to the present invention. TG...timing generator, CS...clock selector, F...format, M...memory, IC...integrated circuit, ADD...memory address,
SD...Scan data, SP...Scan pulse, _I1 to _I8 ...Inspection pattern.

Claims (1)

[Claims] 1. Based on the test data stored in the memory,
In an integrated circuit tester that tests an integrated circuit by the scan-in-out method using a flip-flop in the integrated circuit, the integrated circuit tester tests an area in which a predetermined number of bits are stored corresponding to an address. a test pattern for setting input/output conditions of the integrated circuit at a predetermined address; n-bit scan data for setting and testing the state of a flip-flop in the integrated circuit at an address different from the predetermined address; and a flag bit for determining whether the test data is the scan data or the test pattern in each address; The test pattern read out from the memory is input into the integrated circuit in parallel, and the n-bit scan data read out from the memory when the flag bit indicates the scan data. an integrated circuit tester comprising: means for inputting the test pattern to a flip-flop in the integrated circuit at a speed n times as high as the input speed of the test pattern.