JPH0530145B2 - - Google Patents

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Publication number
JPH0530145B2
JPH0530145B2 JP63262622A JP26262288A JPH0530145B2 JP H0530145 B2 JPH0530145 B2 JP H0530145B2 JP 63262622 A JP63262622 A JP 63262622A JP 26262288 A JP26262288 A JP 26262288A JP H0530145 B2 JPH0530145 B2 JP H0530145B2
Authority
JP
Japan
Prior art keywords
winding
voltage
capacitor
shielding layer
switching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63262622A
Other languages
Japanese (ja)
Other versions
JPH0295168A (en
Inventor
Seiichi Yamano
Haruo Ogiwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP63262622A priority Critical patent/JPH0295168A/en
Publication of JPH0295168A publication Critical patent/JPH0295168A/en
Publication of JPH0530145B2 publication Critical patent/JPH0530145B2/ja
Granted legal-status Critical Current

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  • Devices For Supply Of Signal Current (AREA)
  • Dc-Dc Converters (AREA)

Description

【発明の詳細な説明】 この発明は直流電力をスイツチングしてトラン
スの1次巻線へ供給し、そのトランスの2次巻線
の出力を整流平滑して直流出力を得るDC−DC変
換回路に関し、特に入出力間を高インピーダンス
で分離し、しかも同相モードスイツチング雑音の
発生が少ない回路に係わる。
[Detailed Description of the Invention] This invention relates to a DC-DC conversion circuit that switches DC power and supplies it to the primary winding of a transformer, rectifies and smoothes the output of the secondary winding of the transformer, and obtains a DC output. In particular, it relates to a circuit that separates input and output with high impedance and generates little common-mode switching noise.

<背景> この種のDC−DC変換回路は例えばデイジタル
加入者線伝送方式における加入者宅内側に設置さ
れるデイジタル回線終端装置の電源として用いら
れる。即ち第1図に示すように、加入者宅内側に
設置されるデイジタル回線終端装置11は一般に
局からの遠方給電によつて動作するように構成さ
れ、デイジタル回線終端装置11に接続された平
衡形ケーブルの加入者線12上にはデイジタル信
号と給電直流電流とが重畳されている。加入者線
12の他端は図に示していないが局内に引込ま
れ、局内側のデイジタル回線終端装置に接続され
る。加入者線12上のデイジタル信号は装置11
との接続点13、トランス14を介してパルス伝
送回路15に入力される。パルス伝送回路15は
等化増幅回路、パルス送信回路などから構成され
る。加入者線12上の給電直流電流は接続点1
3、電力分離フイルタ16a,16bを介して
DC−DC変換回路17の1次側18a,18bに
入力され、これら1次側18a,18b間には例
えば直流電圧30Vが印加される。DC−DC変換回
路17ではDC−DC変換を行い、DC−DC変換回
路17の2次側19a,19b間には、例えば直
流電圧5Vを発生する。デイジタル回線終端装置
11の主要部あるいは全体は、DC−DC変換回路
17の2次側19a,19bの出力によつて動作
する。接続点13及びフイルタ16a,16bの
接続点とトランス14との間に挿入された直流阻
止コンデンサ21はトランス14に給電直流電流
を流さないために設けている。電力分離フイルタ
16a,16bは、直流低インピーダンス、交流
高インピーダンスとなるように例えばコイルで構
成されている。これは、DC−DC変換回路17の
1次側18a,18b間の交流インピーダンスが
低いため、デイジタル信号を短絡することを避け
るためである。
<Background> This type of DC-DC conversion circuit is used, for example, as a power source for a digital line termination device installed inside a subscriber's premises in a digital subscriber line transmission system. That is, as shown in FIG. 1, the digital line termination device 11 installed inside the subscriber's premises is generally configured to operate by distant power supply from the station, and the balanced type connected to the digital line termination device 11 is A digital signal and a feeding direct current are superimposed on the subscriber line 12 of the cable. Although not shown in the figure, the other end of the subscriber line 12 is led into the office and connected to a digital line termination device inside the office. Digital signals on subscriber line 12 are transmitted to equipment 11
The signal is inputted to the pulse transmission circuit 15 via the connection point 13 and the transformer 14. The pulse transmission circuit 15 includes an equalization amplifier circuit, a pulse transmission circuit, and the like. The supply direct current on the subscriber line 12 is connected to the connection point 1.
3. Via power separation filters 16a and 16b
The voltage is input to the primary sides 18a and 18b of the DC-DC conversion circuit 17, and a DC voltage of 30 V, for example, is applied between the primary sides 18a and 18b. The DC-DC conversion circuit 17 performs DC-DC conversion, and generates, for example, a DC voltage of 5 V between the secondary sides 19a and 19b of the DC-DC conversion circuit 17. The main part or the whole of the digital line termination device 11 is operated by the outputs of the secondary sides 19a and 19b of the DC-DC conversion circuit 17. A DC blocking capacitor 21 inserted between the connection point 13 and the connection point between the filters 16a and 16b and the transformer 14 is provided to prevent the supply DC current from flowing through the transformer 14. The power separation filters 16a and 16b are constructed of, for example, coils so as to have low impedance for direct current and high impedance for alternating current. This is to avoid short-circuiting the digital signals since the AC impedance between the primary sides 18a and 18b of the DC-DC conversion circuit 17 is low.

さて、以上の構成のデイジタル回線終端装置1
1の電源であるDC−DC変換回路17に、従来構
成のDC−DC変換回路を適用する場合、以下の欠
点が生じる。
Now, the digital line termination device 1 with the above configuration.
When a conventionally configured DC-DC converter circuit is applied to the DC-DC converter circuit 17, which is the power source of No. 1, the following drawbacks occur.

(a) DC−DC変換回路17の1次側と2次側との
間、すなわち1次側18a及び2次側19a
間、あるいは1次側18b及び2次側19b
間、にDC−DC変換回路17のスイツチングに
ともなうスイツチング雑音v1、いわゆる同相モ
ードスイツチング雑音が発生する。この同相モ
ードスイツチング雑音は、加入者線12及びデ
イジタル回線終端装置11などによつて決る不
平衡減衰量に応じて差動モード雑音に変換さ
れ、トランス14の2次側22a,22b間に
廻り込み、デイジタル信号の符号誤りの原因と
なる。このため同相モードスイツチング雑音の
発生を充分に小さくする必要があるが、従来の
DC−DC変換回路ではこれを満足させることが
できなかつた。
(a) Between the primary side and the secondary side of the DC-DC conversion circuit 17, that is, the primary side 18a and the secondary side 19a
between the primary side 18b and the secondary side 19b
During this period, switching noise v1 , so-called common mode switching noise, occurs due to switching of the DC-DC conversion circuit 17. This common mode switching noise is converted into differential mode noise according to the amount of unbalanced attenuation determined by the subscriber line 12, the digital line termination device 11, etc., and is transmitted between the secondary sides 22a and 22b of the transformer 14. This can cause code errors in digital signals. For this reason, it is necessary to sufficiently reduce the generation of common-mode switching noise, but conventional
A DC-DC conversion circuit could not satisfy this requirement.

(b) 加入者線12上には、アナログ電話回線から
のインパルス性雑音等の各種縦雑音が誘導さ
れ、デイジタル信号の符号誤りの原因となるた
め、デイジタル回線終端装置11の不平衡減衰
量は充分に高くする必要がある。前記(a)項に記
載した欠点を除去するため、第2図に示すよう
にDC−DC変換回路17のスイツチング周波数
で充分に低インピーダンスの外付コンデンサ2
3を、1次側18a及び2次側19a間(ある
いは1次側18b及び2次側19b間)に接続
することにより前記同相モードスイツチング雑
音を抑圧しているものがある。しかし、このよ
うな構成とし、かつDC−DC変換回路17の2
次側19aあるいは19bを低インピーダンス
でアースに接続する場合、電力分離フイルタ1
6a(あるいは16b)用のコイルと外付コン
デンサ23とから縦回路に共振点を形成し、こ
の共振点においてデイジタル回線終端回路11
の不平衡減衰量が極度に劣化し符号誤りを生じ
る。このため、前記共振点をパルス伝送帯域よ
り充分に高い周波数とする必要があり、これに
は外付コンデンサ23を除去し、DC−DC変換
回路17の1次側18a,18bと2次側19
a,19bとをトランス14のストレー容量程
度の高インピーダンスで分離することが必要で
ある。しかし、このようにすると従来の回路構
成では前記(a)項に記載した欠点が生じる。
(b) Various types of vertical noise such as impulsive noise from the analog telephone line are induced on the subscriber line 12 and cause code errors in the digital signal, so the unbalanced attenuation of the digital line termination device 11 is It needs to be high enough. In order to eliminate the drawback described in the above item (a), as shown in FIG.
Some devices suppress the common-mode switching noise by connecting 3 between the primary side 18a and the secondary side 19a (or between the primary side 18b and the secondary side 19b). However, with such a configuration and the second part of the DC-DC conversion circuit 17.
When connecting the next side 19a or 19b to earth with low impedance, power isolation filter 1
A resonance point is formed in the vertical circuit from the coil for 6a (or 16b) and the external capacitor 23, and at this resonance point, the digital line termination circuit 11
The unbalanced attenuation of the signal is extremely degraded, resulting in code errors. Therefore, it is necessary to set the resonance point to a frequency sufficiently higher than the pulse transmission band, and for this purpose, the external capacitor 23 is removed and the primary sides 18a, 18b and secondary side 19 of the DC-DC conversion circuit 17 are
a and 19b must be separated by a high impedance comparable to the stray capacitance of the transformer 14. However, in this case, the conventional circuit configuration suffers from the drawbacks described in item (a) above.

以下これらの点について更に詳細に説明する。 These points will be explained in more detail below.

第3図に従来のDC−DC変換回路の基本構成を
示す。直流電源24から1次側18a,18bを
通じて入力された直流入力電圧E1はスイツチ素
子25のオン/オフの繰返し動作(以下スイツチ
ングと呼ぶ)により交番電圧(以下スイツチング
電圧と呼ぶ)に変換され、トランス26の1次巻
線27の両端29,31間にはスイツチング電圧
e1が生じる。このためトランス26の2次巻線2
8の両端32,33間にはスイツチング電圧e2
誘起される。このスイツチング電圧e2はダイオー
ド34で半波整流され、出力コンデンサ35で平
滑され、直流出力電圧E2が得られ、この直流出
力は2次側19a,19bを通じて負荷36へ供
給される。なお1次巻線27の両端29,31間
に誘起されるスイツチング電圧e1と2次巻線28
の両端32,33間に誘起されるスイツチング電
圧e2との比は1次巻線27と2次巻線28との巻
線比により定まる。直流電源24の両端間に入力
コンデンサ37が接続され、またスイツチ素子2
5は例えばトランジスタであつて、このトランジ
スタ25は1次巻線27と直列に挿入され、トラ
ンジスタ25のベース・エミツタ間に駆動回路3
8が接続されている。
FIG. 3 shows the basic configuration of a conventional DC-DC conversion circuit. The DC input voltage E1 input from the DC power supply 24 through the primary sides 18a and 18b is converted into an alternating voltage (hereinafter referred to as switching voltage) by the repeated on/off operation (hereinafter referred to as switching) of the switch element 25, A switching voltage is applied between both ends 29 and 31 of the primary winding 27 of the transformer 26.
e 1 occurs. Therefore, the secondary winding 2 of the transformer 26
A switching voltage e 2 is induced between both ends 32 and 33 of 8. This switching voltage e2 is half-wave rectified by a diode 34 and smoothed by an output capacitor 35 to obtain a DC output voltage E2 , which is supplied to a load 36 through the secondary sides 19a and 19b. Note that the switching voltage e 1 induced between both ends 29 and 31 of the primary winding 27 and the secondary winding 28
The ratio to the switching voltage e 2 induced between both ends 32 and 33 of is determined by the winding ratio between the primary winding 27 and the secondary winding 28. An input capacitor 37 is connected between both ends of the DC power supply 24, and a switch element 2
5 is a transistor, for example, and this transistor 25 is inserted in series with the primary winding 27, and the drive circuit 3 is connected between the base and emitter of the transistor 25.
8 are connected.

この第3図に示した従来のDC−DC変換回路で
は1次側−2次側間、すなわち1次側18a、2
次側19a間に大きなスイツチング電圧が発生す
る欠点があつた。これを同相モードスイツチング
雑音と呼び、以下第4図を用いて説明する。第4
図は第3図に示したDC−DC変換回路において、
同相モードスイツチング雑音の発生機構を交流成
分に着目して示したものである。第4図中の記号
は第3図に準じ、e1,e2,v1及びv2は任意の時点
での各端子間のスイツチング電圧を、また矢印は
各電圧極性の相互関係を示す。スイツチ素子25
と電源24との接続点を1次側18b、ダイオー
ド34と出力コンデンサ35との接続点を2次外
側19bとしている。巻線端29,32間のコン
デンサ42、巻線端31,33間のコンデサン4
3はそれぞれ1次巻線27と2次巻線28との間
に分布するストレー容量を集中定数回路で表わし
たものである。スイツチ素子25、1次巻線2
7、入力コンデンサ37よりなる閉回路を閉路
と名付け、1次巻線27、2次巻線28、コンデ
ンサ42,43よりなる閉回路を閉路と、2次
巻線28、ダイオード34、出力コンデンサ35
よりなる閉回路を閉路とそれぞれ呼ぶ。
In the conventional DC-DC conversion circuit shown in FIG. 3, between the primary side and the secondary side, that is, the primary side 18a,
There was a drawback that a large switching voltage was generated between the next side 19a. This is called common mode switching noise, and will be explained below using FIG. 4. Fourth
The figure shows the DC-DC conversion circuit shown in Figure 3.
This figure shows the generation mechanism of common-mode switching noise, focusing on the AC component. The symbols in FIG. 4 are the same as in FIG. 3, e 1 , e 2 , v 1 and v 2 represent the switching voltages between the respective terminals at any given time, and the arrows represent the mutual relationship between the voltage polarities. Switch element 25
The connection point between the diode 34 and the power supply 24 is the primary side 18b, and the connection point between the diode 34 and the output capacitor 35 is the secondary outside 19b. Capacitor 42 between winding ends 29 and 32, condenser 4 between winding ends 31 and 33
3 represents the stray capacitance distributed between the primary winding 27 and the secondary winding 28 using lumped constant circuits. Switch element 25, primary winding 2
7. The closed circuit consisting of the input capacitor 37 is called a closed circuit, the closed circuit consisting of the primary winding 27, the secondary winding 28, and the capacitors 42 and 43 is called a closed circuit, and the secondary winding 28, the diode 34, and the output capacitor 35 are called a closed circuit.
A closed circuit consisting of the following is called a closed circuit.

第4図において、まず閉路に着目する。入力
コンデンサ37はスイツチング周波数成分に対し
ては短絡(充分に低インピーダンス)であるから
その両端にはスイツチング電圧は発生しない。従
つてキルヒホツフの電圧則からスイツチ素子25
の両端には1次巻線27の両端29,31間に誘
起されるスイツチング電圧e1に等しい振幅のスイ
ツチング電圧が逆位相で発生する。次に閉路に
着目する。出力コンデンサ35はスイツチング周
波数成分に対しては短絡であるから、その両端に
はスイツチング電圧は発生しない。したがつてキ
ルヒホツフの電圧則からダイオード34の両端に
は2次巻線28の両端32,33間に誘起される
スイツチング電圧e2に等しい振幅のスイツチング
電圧が逆位相で発生する。
In FIG. 4, first focus on the closed circuit. Since the input capacitor 37 is short-circuited (sufficiently low impedance) to the switching frequency component, no switching voltage is generated across it. Therefore, from Kirchhoff's voltage law, the switch element 25
A switching voltage having an amplitude equal to the switching voltage e 1 induced between both ends 29 and 31 of the primary winding 27 is generated at both ends of the primary winding 27 in opposite phases. Next, we will focus on closed circuits. Since the output capacitor 35 is short-circuited for the switching frequency component, no switching voltage is generated across it. Therefore, according to Kirchhoff's voltage law, a switching voltage with an amplitude equal to the switching voltage e 2 induced between the ends 32 and 33 of the secondary winding 28 is generated at both ends of the diode 34 in opposite phases.

次に閉路に着目する。通常コンデンサ42,
43の容量値はともに小さく、スイツチング周波
数を含む高周波数に亘り充分に高いインピーダン
スとなる。さて閉路において、コンデンサ4
2,43の両端に発生するスイツチング電圧を
各々v1,v2とすると、キルヒホツフの電圧則から
v1+v2=e1−e2となる関係を満たす。また電圧v1
とv2の比は各々のコンデンサ42,43の容量値
に反比例する。コンデンサ42の両端に発生する
スイツチング電圧v1は同相モードスイツチング雑
音である。以下閉路部分の拡大図である第5図
を用いて説明する。第5図中の記号は第4図に順
ずる。各々コンデンサ42,43の容量値をC1
C2とする。第5図から同相モードスイツチング
雑音の振幅値v1は v1=C2/C1+C2(e2−e1) (1) となり、1次巻線27の両端に生じるスイツチン
グ電圧e1と、2次巻線28の両端に誘起されるス
イツチング電圧e2との双方の影響から発生する。
通常のDC−DC変換回路においてはe1≠e2であ
る。このため1次側18a,18b、2次側19
a,19b間を高インピーダンスで分離し、かつ
同相モードスイツチング雑音の発生を少なくする
ためにはコンデンサ43の容量値C2をコンデン
サ42の容量値C1に対して充分に小さくする必
要がある。しかし、コンデンサ43の容量値C2
はトランスの1次巻線27、2次巻線28及びコ
アの形状によつて定まり、容量値C2はあまり小
さくできない。一方コンデンサ42の容量値C1
を大きくすると(例えばコンデンサ外付により)、
同相モードスイツチング雑音は小さくなるが、1
次側18a,18b−2次側19a,19b間が
低インピーダンスとなる。以上から1次側18
a,18b−2次側19a,19b間を高インピ
ーダンスで分離し、かつ同相モードスイツチング
雑音を低減化させることは従来技術は困難であつ
た。一例として第3図に示した構成で直流入力電
圧E1=30V、直流出力電圧E2=5V、出力電圧1W
程度のDC−DC変換回路においては、同相モード
スイツチング雑音はリツプル成分で約10Vpp程度
生じる。但し、1次、2次巻線の構成によりこの
雑音値は微妙に異なつてくる。
Next, we will focus on closed circuits. Normal capacitor 42,
The capacitance values of 43 are both small, and the impedance is sufficiently high over high frequencies including the switching frequency. Now, in a closed circuit, capacitor 4
If the switching voltages generated at both ends of 2 and 43 are v 1 and v 2 , respectively, then from Kirchhoff's voltage law,
It satisfies the relationship v 1 + v 2 = e 1 − e 2 . Also the voltage v 1
and v 2 is inversely proportional to the capacitance value of each capacitor 42, 43. The switching voltage v 1 generated across capacitor 42 is common mode switching noise. The following description will be made with reference to FIG. 5, which is an enlarged view of the closed circuit portion. The symbols in FIG. 5 correspond to those in FIG. 4. The capacitance values of capacitors 42 and 43 are C 1 ,
Let it be C 2 . From FIG. 5, the amplitude value v 1 of the common mode switching noise is v 1 = C 2 /C 1 +C 2 (e 2 - e 1 ) (1), and the switching voltage e 1 generated across the primary winding 27 is and the switching voltage e 2 induced across the secondary winding 28.
In a normal DC-DC conversion circuit, e 1 ≠ e 2 . Therefore, the primary side 18a, 18b, the secondary side 19
In order to isolate between a and 19b with high impedance and to reduce the occurrence of common mode switching noise, the capacitance value C2 of the capacitor 43 must be made sufficiently smaller than the capacitance value C1 of the capacitor 42. . However, the capacitance value C 2 of the capacitor 43
is determined by the shapes of the primary winding 27, secondary winding 28, and core of the transformer, and the capacitance value C2 cannot be made very small. On the other hand, the capacitance value C 1 of the capacitor 42
When increasing (for example, by adding an external capacitor),
The common mode switching noise will be smaller, but 1
The impedance between the next sides 18a, 18b and the secondary sides 19a, 19b is low. From the above, the primary side 18
It has been difficult in the prior art to isolate the secondary sides 19a, 19b from the secondary sides 19a, 19b with high impedance and to reduce common mode switching noise. As an example, in the configuration shown in Figure 3, the DC input voltage E 1 = 30V, the DC output voltage E 2 = 5V, and the output voltage 1W.
In a DC-DC conversion circuit of about 100 volts, common-mode switching noise occurs as a ripple component of about 10 Vpp. However, this noise value differs slightly depending on the configuration of the primary and secondary windings.

<発明の概要> この発明の目的は直流及びスイツチング周波数
を含む高周波域に亘り1次側−2次側間を高イン
ピーダンスで分離し、しかも同相モードスイツチ
ング雑音の発生が少ないDC−DC変換回路を提供
することにある。
<Summary of the Invention> The purpose of the present invention is to provide a DC-DC conversion circuit that isolates the primary side and the secondary side with high impedance over a high frequency range including DC and switching frequencies, and that generates little common mode switching noise. Our goal is to provide the following.

この発明によれば1次巻線と2次巻線との間に
静電遮へい層が配され、この静電遮へい層は1次
巻線の静止端に接続され、かつ2次巻線の中点か
らみて、2次巻線の一方の側に静電遮へい層に対
して誘起される電圧と、1次巻線の他方の側に静
電遮へい層に対して誘起される電圧が互いに逆極
性となる打消手段が設けられる。
According to this invention, an electrostatic shielding layer is arranged between the primary winding and the secondary winding, and this electrostatic shielding layer is connected to the stationary end of the primary winding and inside the secondary winding. From the point of view, the voltage induced against the electrostatic shielding layer on one side of the secondary winding and the voltage induced against the electrostatic shielding layer on the other side of the primary winding have opposite polarity. A canceling means is provided.

<第1実施例> 第6図はこの発明の第1実施例を示し、半波整
流用のダイオード34a,34bが2次巻線28
の両端にそれぞれ直列に接続される。ダイオード
34a,34bの他端は出力コンデンサ35の両
端に接続される。1次巻線27と2次巻線28と
の間に静電遮へい層46が介在される。この静電
遮へい層46は1次巻線27の交流的な0電位点
(以下静止端と呼ぶ)である巻線端29に接続し
ている。1次側18bも静止端であり、静電遮へ
い層46を1次側18bに接続しても効果は同一
である。その他の記号は第3図に順ずる。このよ
うな構造をしているから以下に述べるように1次
側18a、2次側19a間に発生するスイツチン
グ電圧、即ち同相モードスイツチング雑音を低減
化する作用がある。第6図に示した構成によれば
(i)1次巻線27−2次巻線28間に静電遮へい層
46が設けられ、かつこれは1次巻線27の静止
端である巻線端29に接続されていることにより
1次巻線27の両端に生じるスイツチング電圧e1
が1次側18a、2次側19a間の電圧(同相モ
ードスイツチング雑音)として発生しない。(ii)半
波整流用のダイオード34a,34bが2次巻線
28の両端にそれぞれ接続され、静電遮へい層4
6−巻線端32(あるいは33)間に発生するス
イツチング電圧とダイオード34b(あるいはダ
イオード34a)の両端である巻線端32(ある
いは33)−2次側19a(あるいは19b)間に
発生するスイツチング電圧とが逆極性となり、互
いに打ち消し合うことにより、2次巻線28の両
端に生じるスイツチング電圧e2が1次側18a−
2次側19a間の電圧(同相モードスイツチング
雑音)として発生しない。
<First Embodiment> FIG. 6 shows a first embodiment of the present invention, in which diodes 34a and 34b for half-wave rectification are connected to the secondary winding 28.
are connected in series to both ends of the The other ends of the diodes 34a and 34b are connected to both ends of the output capacitor 35. An electrostatic shielding layer 46 is interposed between the primary winding 27 and the secondary winding 28 . This electrostatic shielding layer 46 is connected to a winding end 29 which is an AC zero potential point (hereinafter referred to as a static end) of the primary winding 27. The primary side 18b is also a stationary end, and the effect is the same even if the electrostatic shielding layer 46 is connected to the primary side 18b. Other symbols are in accordance with Figure 3. This structure has the effect of reducing the switching voltage generated between the primary side 18a and the secondary side 19a, that is, the common mode switching noise, as described below. According to the configuration shown in FIG.
(i) An electrostatic shielding layer 46 is provided between the primary winding 27 and the secondary winding 28, and this is connected to the winding end 29, which is the stationary end of the primary winding 27, so that Switching voltage e 1 generated across the secondary winding 27
is not generated as a voltage (common mode switching noise) between the primary side 18a and the secondary side 19a. (ii) Diodes 34a and 34b for half-wave rectification are connected to both ends of the secondary winding 28, and the electrostatic shielding layer 4
6 - Switching voltage generated between the winding end 32 (or 33) and switching generated between the winding end 32 (or 33) and the secondary side 19a (or 19b), which are both ends of the diode 34b (or diode 34a) The voltages have opposite polarities and cancel each other out, so that the switching voltage e2 generated at both ends of the secondary winding 28 becomes the switching voltage e2 on the primary side 18a-
It does not occur as a voltage (common mode switching noise) across the secondary side 19a.

これらについて第7図を用いて詳細に説明す
る。第7図は第6図に示したDC−DC変換回路に
おいて同相モードスイツチング雑音の低減化作用
を交流成分に着目して示したものである。第7図
中の記号は第6図に準じ、e1,e2,v1及びv2は任
意の時点での各端子間のスイツチング電圧を、ま
た矢印は各電圧極性の相互関係を示す。
These will be explained in detail using FIG. 7. FIG. 7 shows the effect of reducing the common mode switching noise in the DC-DC conversion circuit shown in FIG. 6, focusing on the alternating current component. The symbols in FIG. 7 are the same as in FIG. 6, e 1 , e 2 , v 1 and v 2 indicate the switching voltages between the terminals at any given time, and the arrows indicate the mutual relationship between the voltage polarities.

コンデンサ47は2次巻線28と静電遮へい層
46との間に分布するストレー容量を集中定数回
路で表わし、コンデンサ47は2次巻線28の端
子32と静遮へい層46との間に接続してある。
コンデンサ51は2次巻線28と静電遮へい層4
6との間に分布するストレー容量を集中定数回路
で表わし、コンデンサ51は2次巻線28の端子
33と静電遮へい層46との間に接続される。コ
ンデンサ52,53は1次巻線27と静電遮へい
層46との間に分布するストレー容量を集中定数
回路で表わし、コンデンサ52,53は1次巻線
27の両端29,31と静電遮へい層46との間
に接続される。コンデンサ37、1次巻線27、
スイツチ素子25の閉回路を閉路とし、1次巻
線27、コンデンサ52,53、静電遮へい層4
6の閉回路を閉路とし、閉路は2次巻線2
8、コンデンサ47,51、静電遮へい層46で
構成され、閉路は2次巻線28、ダイオード3
4a,34bコンデンサ35で構成される。最初
に前記(i)項を説明する。第7図において、まず閉
路に着目する。入力コンデンサ37はスイツチ
ング周波数成分に対しては短絡(充分に低インピ
ーダンス)であるから、その両端にはスイツチン
グ電圧は発生しない。従つてキルヒホツフの電圧
則からスイツチ素子25の両端には1次巻線27
の両端29,31間に誘起されるスイツチング電
圧e1に等しい振幅のスイツチング電圧が逆位相で
発生する。次に閉路に着目する。コンデンサ5
2,53は1次巻線27と静電遮へい層46との
間に分布するストレー容量を集中定数回路で表わ
したものである。コンデンサ52は巻線端29と
静電遮へい層46との間に接続され、コンデンサ
53は巻線端31と静電遮へい層46との間に接
続される。ここでコンデンサ52の両端は静電遮
へい層46により短絡されているからスイツチン
グ電圧は発生しない。したがつて閉路における
キルヒホツフの電圧則からコンデンサ53の両端
には、1次巻線27の両端29,31間に生じる
スイツチング電圧e1に等しい振幅のスイツチング
電圧が逆位相で発生する。以上から1次側に発生
するスイツチング電圧e1は静電遮へい層46によ
り1次側のみに閉じ、1次側18a−2次側19
a間の電圧には影響を及ぼさない。
The capacitor 47 represents the stray capacitance distributed between the secondary winding 28 and the electrostatic shielding layer 46 using a lumped constant circuit, and the capacitor 47 is connected between the terminal 32 of the secondary winding 28 and the static shielding layer 46. It has been done.
The capacitor 51 is connected to the secondary winding 28 and the electrostatic shielding layer 4.
6 is represented by a lumped constant circuit, and the capacitor 51 is connected between the terminal 33 of the secondary winding 28 and the electrostatic shielding layer 46. The capacitors 52 and 53 represent the stray capacitance distributed between the primary winding 27 and the electrostatic shielding layer 46 using a lumped constant circuit, and the capacitors 52 and 53 represent the stray capacitance distributed between the primary winding 27 and the electrostatic shielding layer 46. layer 46. capacitor 37, primary winding 27,
The closed circuit of the switch element 25 is a closed circuit, and the primary winding 27, the capacitors 52 and 53, and the electrostatic shielding layer 4
The closed circuit of 6 is a closed circuit, and the closed circuit is the secondary winding 2.
8, consists of capacitors 47 and 51, and an electrostatic shielding layer 46, and the closed circuit is formed by a secondary winding 28 and a diode 3.
It is composed of capacitors 35 4a and 34b. First, the above item (i) will be explained. In FIG. 7, attention is first paid to the closed circuit. Since the input capacitor 37 is short-circuited (sufficiently low impedance) to the switching frequency component, no switching voltage is generated across it. Therefore, from Kirchhoff's voltage law, the primary winding 27 is connected to both ends of the switch element 25.
A switching voltage with an amplitude equal to the switching voltage e 1 induced between the ends 29 and 31 of is generated in opposite phase. Next, we will focus on closed circuits. capacitor 5
2 and 53 represent the stray capacitance distributed between the primary winding 27 and the electrostatic shielding layer 46 using lumped constant circuits. Capacitor 52 is connected between winding end 29 and electrostatic shielding layer 46 , and capacitor 53 is connected between winding end 31 and electrostatic shielding layer 46 . Here, since both ends of the capacitor 52 are short-circuited by the electrostatic shielding layer 46, no switching voltage is generated. Therefore, according to Kirchhoff's voltage law in a closed circuit, a switching voltage with an amplitude equal to the switching voltage e 1 generated between both ends 29 and 31 of the primary winding 27 is generated at opposite ends of the capacitor 53 in opposite phases. From the above, the switching voltage e1 generated on the primary side is closed only to the primary side by the electrostatic shielding layer 46, and the switching voltage e1 generated on the primary side is
It does not affect the voltage between a.

次に前記(ii)項について説明する。第7図におい
て閉路に着目する。出力コンデンサ35はスイ
ツチング周波数成分に対しては短絡であるから両
端にはスイツチング電圧は発生しない。また2次
巻線28の両端32,33間には、スイツチング
電圧e2が誘起されている。ここで閉路における
キルヒホツフの電圧則から、ダイオード34a,
34bの両端には2次巻線28の両端32,33
間に誘起されるスイツチング電圧e2とは逆位相の
スイツチング電圧が、振幅が2分割されて発生す
る。ここでダイオード特性のばらつきを考えて、
ダイオード34a,34bの両端に発生するスイ
ツチング電圧の振幅を各々e2/2+Δ、e2/2−Δとす る。
Next, the above item (ii) will be explained. In FIG. 7, attention is paid to the closed circuit. Since the output capacitor 35 is short-circuited for the switching frequency component, no switching voltage is generated across the output capacitor 35. Further, a switching voltage e 2 is induced between both ends 32 and 33 of the secondary winding 28. Here, from Kirchhoff's voltage law in a closed circuit, the diode 34a,
Both ends 32 and 33 of the secondary winding 28 are connected to both ends of 34b.
A switching voltage having an opposite phase to the switching voltage e 2 induced between the two is generated with the amplitude divided into two. Considering the variation in diode characteristics,
Let the amplitudes of the switching voltages generated across the diodes 34a and 34b be e 2 /2+Δ and e 2 /2−Δ, respectively.

次に閉路に着目する。コンデンサ47,51
は静電遮へい層46と2次巻線28との間に分布
するストレー容量を集中定数回路で表わしたもの
であり、コンデンサ47は静電遮へい層47と巻
線端32との間に接続され、コンデンサ51は静
電遮へい層46と巻線端33との間に接続される
通常、このコンデンサ47,51の容量値はとも
に小さく、スイツチング周波数を含む高周波域に
亘り充分に高インピーダンスとなる。さて、コン
デンサ47,51の両端に発生するスイツチング
電圧を各々v1、v2とすると、閉路におけるキル
ヒホツフの電圧則から、v1+v2=e2となる関係を
満たす。以下閉路部分の拡大図である第8図を
用いて説明する。第8図中の記号は第7図に順ず
る。各々コンデンサ47,51の容量値をそれぞ
れC3、C4とする。第8図の閉路について閉路
方程式を解くと、 v1=C4/C3+C4e2 (2) となる。さて、再び第7図に戻つて説明する。
Next, we will focus on closed circuits. Capacitor 47, 51
is a lumped constant circuit representing the stray capacitance distributed between the electrostatic shielding layer 46 and the secondary winding 28, and the capacitor 47 is connected between the electrostatic shielding layer 47 and the winding end 32. , capacitor 51 is connected between electrostatic shielding layer 46 and winding end 33. Normally, capacitance values of both capacitors 47 and 51 are small, and the impedance is sufficiently high over a high frequency range including the switching frequency. Now, when the switching voltages generated across the capacitors 47 and 51 are respectively v 1 and v 2 , the following relationship is satisfied from Kirchhoff's voltage law in a closed circuit: v 1 +v 2 =e 2 . The following description will be made with reference to FIG. 8, which is an enlarged view of the closed circuit portion. The symbols in FIG. 8 correspond to those in FIG. Let the capacitance values of the capacitors 47 and 51 be C 3 and C 4 , respectively. Solving the cycle equation for the cycle in Figure 8 yields v 1 = C 4 /C 3 + C 4 e 2 (2). Now, let's go back to FIG. 7 and explain.

同相モードスイツチング電圧は1次側18a−
2次側19a間に生じるスイツチング電圧であ
り、これをv3と記すと第7図から、 v3=v1−(e2/2−Δ) (3) 式(3)に式(2)を代入し、 v3=C4−C3/C3+C4・e2/2+Δ (4) となる。式(4)においてΔの値は充分に小さく同相
モードスイツチング雑音は、コンデンサ47の容
量値C3とコンデンサ51の容量値C4との差が小
さい程低減化される。さて、第6図において、静
電遮へい層46−巻線端32間のストレー容量と
静電遮へい層46−巻線端33間のストレー容量
を等しくする技術は比較的容易であり、静電遮へ
い層46に対する巻線端32の物理的位置と、静
電遮へい層46に対する巻線端33の物理的位置
を対称とすればよい。例えば2次巻線28を静電
遮へい層46に対して1層巻きとなるように構成
すれば良い。すなわち、第8図においてコンデン
サ47の容量値C3とコンデンサ51の容量値C4
とを概ね等しくする技術は既知である。以上から
半波整流用のダイオード34a,34bを2次巻
線2の両端にそれぞれ接続することにより、2次
巻線28の両端に誘起されるスイツチング電圧e2
が1次側18a−2次側19a間の電圧に及ぼす
影響を低減化させ得ることを説明できた。
The common mode switching voltage is on the primary side 18a-
This is the switching voltage that occurs between the secondary side 19a, and if this is written as v 3 , then from FIG. Substituting , v 3 = C 4 − C 3 /C 3 +C 4・e 2 /2+Δ (4). In equation (4), the value of Δ is sufficiently small, and the common mode switching noise is reduced as the difference between the capacitance value C 3 of the capacitor 47 and the capacitance value C 4 of the capacitor 51 becomes smaller. Now, in FIG. 6, the technique of equalizing the stray capacitance between the electrostatic shielding layer 46 and the winding end 32 and the stray capacitance between the electrostatic shielding layer 46 and the winding end 33 is relatively easy; The physical position of winding end 32 with respect to layer 46 and the physical position of winding end 33 with respect to electrostatic shielding layer 46 may be symmetrical. For example, the secondary winding 28 may be configured to have one layer of winding around the electrostatic shielding layer 46. That is, in FIG. 8, the capacitance value C 3 of the capacitor 47 and the capacitance value C 4 of the capacitor 51 are
Techniques for making these approximately equal are known. From the above, by connecting the half-wave rectifying diodes 34a and 34b to both ends of the secondary winding 2, the switching voltage e 2 induced across the secondary winding 28 is
It has been explained that the influence on the voltage between the primary side 18a and the secondary side 19a can be reduced.

以上、第6図の構成により直流及びスイツチン
グ周波数を含む高周波域に亘り1次側18a,1
8b−2次側19a,19b間を高インピーダン
スで分離し、かつ同相モードスイツチング雑音の
発生が少ないDC−DC変換回路を提供できる。
As described above, with the configuration shown in FIG. 6, the primary side 18a, 1
It is possible to provide a DC-DC conversion circuit that isolates the secondary sides 19a and 19b with high impedance and generates less common mode switching noise.

第6図において2次側が多出力で2次巻線を複
数個有するDC−DC変換回路とする場合には1次
巻線、複数の2次巻線を順次同軸心上に形成し、
2次巻線相互間にも静電遮へい層を設け、かつこ
の静電遮へい層を、1次巻線−2次巻線間の静電
遮へい層46に接続した構成とすることが、同相
モードスイツチング雑音の発生を少なくする上で
有利である。
In FIG. 6, when the secondary side is a DC-DC converter circuit with multiple outputs and multiple secondary windings, the primary winding and multiple secondary windings are sequentially formed on the same axis,
By providing an electrostatic shielding layer between the secondary windings and connecting this electrostatic shielding layer to the electrostatic shielding layer 46 between the primary winding and the secondary winding, common mode This is advantageous in reducing the occurrence of switching noise.

<第2実施例> 以上はいわゆる電流伝送形、つまり第6図にお
いて、1次側のスイツチ素子25がオフの時に、
2次側の半波整流用のダイオード34a,34b
が導通する形式のDC−DC変換回路にこの発明を
適用したが、いわゆる電圧伝送形、つまり1次側
のスイツチ素子がオンの時に2次側の半波整流用
のダイオードが導通する形式のDC−DC変換回路
にも、この発明を適用できる。第6図と対応する
この発明の電圧伝送形のDC−DC変換回路を第9
図に示す。これらの場合において整流用ダイオー
ド34a,34bが第6図の場合と逆極性とさ
れ、その他は同一構成である。
<Second Embodiment> The above is a so-called current transmission type, that is, in FIG. 6, when the primary side switch element 25 is off,
Diodes 34a and 34b for half-wave rectification on the secondary side
This invention was applied to a DC-DC conversion circuit of the type in which the current is conductive, but it is also applicable to a DC-DC conversion circuit of the so-called voltage transmission type, in which the half-wave rectifier diode on the secondary side conducts when the switch element on the primary side is on. -The present invention can also be applied to a DC conversion circuit. The voltage transmission type DC-DC conversion circuit of the present invention corresponding to FIG. 6 is shown in FIG. 9.
As shown in the figure. In these cases, the rectifying diodes 34a, 34b have opposite polarities to those in the case of FIG. 6, and the other configurations are the same.

<効果> 以上説明したようにこの発明により、直流及び
スイツチング周波数を含む高周波域に亘り1次側
及び2次側間を高インピーダンスで分離し、かつ
同相モードスイツチング雑音の発生が少ないDC
−DC変換回路が提供できるため、平衡形ケーブ
ルを用いたデイジタル加入者線伝送系において、
局からの遠方給電によつて動作する加入者宅内側
に設置されるデイジタル回線終端装置用の受電用
電源としての適用に利点がある。具体的にはDC
−DC変換回路の発生するスイツチング雑音のパ
ルス伝送系回路への廻り込みが少なく、デイジタ
ル回線終端装置と加入者線との高インピーダンス
分離が可能である。これによる効果はパルス伝送
帯域においてデイジタル回線終端装置の高い不平
衡減衰量が得られ、加入者線上に誘導される大き
な縦雑音に対してデイジタル信号の符号誤りを極
力抑圧し得ることである。
<Effects> As explained above, the present invention provides a DC switching system that isolates the primary side and secondary side with high impedance over a high frequency range including DC and switching frequencies, and generates less common mode switching noise.
-Since we can provide DC conversion circuits, we can provide
It has an advantage in application as a power receiving power source for a digital line termination device installed inside a subscriber's premises that operates by supplying power from a remote station. Specifically, DC
- Switching noise generated by the DC conversion circuit is less likely to enter the pulse transmission system circuit, and high impedance separation between the digital line termination device and the subscriber line is possible. The effect of this is that a high unbalanced attenuation of the digital line termination device can be obtained in the pulse transmission band, and code errors in the digital signal can be suppressed as much as possible against large vertical noise induced on the subscriber line.

次に数値例を示す。第6図及び第9図に示した
構成において、入力電圧E1を約26V、入力電流を
約24mA、出力電圧E2を5V±3.5%、出力電圧を
約500mW、1次巻線27の巻線数を80回程度、
2次巻線28の巻線数を16回程度、静電遮へい層
46は銅箔、スイツチ素子25はMOS−FET、
整流用ダイオード34a,34bはシヨツトキー
バリアダイオード、トランス2次巻線28は静電
遮へい層46に対して1層巻き、スイツチング周
波数約70KHzとしたDC−DC変換回路において、
同相モードスイツチング雑音はリツプ成分で約
0.5Vpp、電力変換効率は約80%であつた。なお、
スイツチ素子の駆動回路38は他励形あるいは自
励形としても、上記同相モードスイツチング雑音
は同一であつた。
A numerical example is shown next. In the configuration shown in FIGS. 6 and 9, the input voltage E 1 is approximately 26 V, the input current is approximately 24 mA, the output voltage E 2 is 5 V ± 3.5%, the output voltage is approximately 500 mW, and the primary winding 27 turns. The number of lines is about 80 times,
The number of turns of the secondary winding 28 is about 16, the electrostatic shielding layer 46 is copper foil, the switch element 25 is a MOS-FET,
In the DC-DC conversion circuit, the rectifying diodes 34a and 34b are shot key barrier diodes, the transformer secondary winding 28 is wound in one layer around the electrostatic shielding layer 46, and the switching frequency is approximately 70 KHz.
Common-mode switching noise is a lip component of approximately
The power conversion efficiency was 0.5Vpp and approximately 80%. In addition,
The common mode switching noise was the same whether the switch element drive circuit 38 was of the separately excited type or the self-excited type.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図はそれぞれ加入者宅内側に設
置されるデイジタル回線終端装置の構成を示す
図、第3図は従来の電流伝送形DC−DC変換回路
の基本構成を示す接続図、第4図は第3図のDC
−DC変換回路における同相モードスイツチング
雑音発生機構の説明図、第5図は第4図の閉路
部分の拡大図、第6図はこの発明を電流伝送形
DC−DC変換回路に適用した実施例を示す接続
図、第7図は第6図のDC−DC変換回路における
同相モードスイツチング雑音低減化作用の説明
図、第8図は第7図の閉路部分の拡大図、第9
図はこの発明を電圧伝送形DC−DC変換回路に適
用した他の実施例を示す接続図である。 24……直流電源、25……スイツチ素子、2
6……トランス、27……1次巻線、28……2
次巻線、34a,34b……半波整流用のダイオ
ード、35……出力コンデンサ、36……負荷、
37……入力コンデンサ、38……スイツチ素子
の駆動回路、46……静電遮へい層。
Figures 1 and 2 are diagrams showing the configuration of a digital line termination device installed inside a subscriber's premises, respectively. Figure 3 is a connection diagram showing the basic configuration of a conventional current transmission type DC-DC conversion circuit. Figure 4 is the DC of Figure 3.
- An explanatory diagram of the common-mode switching noise generation mechanism in a DC conversion circuit, Figure 5 is an enlarged view of the closed circuit part of Figure 4, and Figure 6 shows the current transmission type of this invention.
A connection diagram showing an example applied to a DC-DC conversion circuit, Fig. 7 is an explanatory diagram of the common mode switching noise reduction effect in the DC-DC conversion circuit of Fig. 6, and Fig. 8 is a closed circuit diagram of Fig. 7. Enlarged view of part, No. 9
The figure is a connection diagram showing another embodiment in which the present invention is applied to a voltage transmission type DC-DC conversion circuit. 24...DC power supply, 25...Switch element, 2
6...Transformer, 27...Primary winding, 28...2
Next winding, 34a, 34b... Diode for half-wave rectification, 35... Output capacitor, 36... Load,
37... Input capacitor, 38... Switch element drive circuit, 46... Electrostatic shielding layer.

Claims (1)

【特許請求の範囲】[Claims] 1 直流電力をスイツチングしてトランスの1次
巻線へ供給し、そのトランスの2次巻線の出力を
整流平滑して直流出力を得るDC−DC変換回路に
おいて、前記1次巻線と2次巻線との間に、その
1次巻線の静止端に接続された静電遮へい層を有
し、前記2次巻線の両端にそれぞれ前記整流のた
めの第1、第2半波整流用のダイオードが、第1
のダイオードのアノードと第2のダイオードのカ
ソードとが2次巻線を挟んで直列に接続されてい
るものであることを特徴とするDC−DC変換回
路。
1. In a DC-DC conversion circuit that switches and supplies DC power to the primary winding of a transformer and rectifies and smoothes the output of the secondary winding of the transformer to obtain a DC output, the primary winding and the secondary An electrostatic shielding layer is provided between the winding and the static end of the primary winding, and first and second half-wave rectifiers for the rectification are provided at both ends of the secondary winding, respectively. the first diode
A DC-DC conversion circuit characterized in that the anode of the diode and the cathode of the second diode are connected in series with a secondary winding interposed therebetween.
JP63262622A 1988-10-18 1988-10-18 Dc/dc converter circuit Granted JPH0295168A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63262622A JPH0295168A (en) 1988-10-18 1988-10-18 Dc/dc converter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63262622A JPH0295168A (en) 1988-10-18 1988-10-18 Dc/dc converter circuit

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP13236482A Division JPS5925578A (en) 1982-07-28 1982-07-28 Dc-dc converting circuit

Publications (2)

Publication Number Publication Date
JPH0295168A JPH0295168A (en) 1990-04-05
JPH0530145B2 true JPH0530145B2 (en) 1993-05-07

Family

ID=17378349

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63262622A Granted JPH0295168A (en) 1988-10-18 1988-10-18 Dc/dc converter circuit

Country Status (1)

Country Link
JP (1) JPH0295168A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012120362A (en) * 2010-12-02 2012-06-21 Sanken Electric Co Ltd Dc-dc converter

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5058522A (en) * 1973-07-30 1975-05-21
JPS5130409A (en) * 1974-09-09 1976-03-15 Nippon Telegraph & Telephone Deetajushinsochi no kidokakuritsuhoshiki

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5320650Y2 (en) * 1973-12-12 1978-05-31
JPS52134610U (en) * 1976-04-05 1977-10-13

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5058522A (en) * 1973-07-30 1975-05-21
JPS5130409A (en) * 1974-09-09 1976-03-15 Nippon Telegraph & Telephone Deetajushinsochi no kidokakuritsuhoshiki

Also Published As

Publication number Publication date
JPH0295168A (en) 1990-04-05

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