JPH05300429A - Video signal processing circuit - Google Patents

Video signal processing circuit

Info

Publication number
JPH05300429A
JPH05300429A JP4104643A JP10464392A JPH05300429A JP H05300429 A JPH05300429 A JP H05300429A JP 4104643 A JP4104643 A JP 4104643A JP 10464392 A JP10464392 A JP 10464392A JP H05300429 A JPH05300429 A JP H05300429A
Authority
JP
Japan
Prior art keywords
circuit
signal
level
vca
variable gain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4104643A
Other languages
Japanese (ja)
Other versions
JP3096519B2 (en
Inventor
Kazuo Kitsuka
和雄 木塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP04104643A priority Critical patent/JP3096519B2/en
Publication of JPH05300429A publication Critical patent/JPH05300429A/en
Application granted granted Critical
Publication of JP3096519B2 publication Critical patent/JP3096519B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Studio Circuits (AREA)
  • Processing Of Color Television Signals (AREA)

Abstract

PURPOSE:To reduce the number of the external parts and pins of an IC in the case of making into the IC by adjusting the chroma signal level of a slave picture corresponding to the level detecting output of a chroma signal for master picture. CONSTITUTION:For a video signal for master picture from an input terminal 1, only the chroma signal component is extracted by a BPF 2 and impressed to a first VCA(voltage controlled amplifier circuit) 16. The level of an output signal from the VCA 16 is detected by a level detection circuit 5 and corresponding to the detecting output, the gain of the VCA 16 is controlled. Therefore, the chroma signal for master picture at a fixed level is obtained at the output terminal of the VCA 16. A PLL circuit 11 generates output signals synchronized with input signals. On the other hand, the output signal of a memory 8 is D/A converted 9 and modulated by a modulation circuit 10, and the modulated chroma signal is impressed to a second VCA 17. Then, the gain relation of third and fourth VCA 18 and 19 is made inversely proportional. Thus, the gains of the VCA 16 and 17 can be exactly made inversely proportional. Therefore, no low-pass filter is required.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、親画面と子画面のクロ
マレベルをそろえることが出来る二画面TV(テレビジ
ョン)受像機の映像信号処理回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing circuit of a dual screen TV (television) receiver capable of aligning chroma levels of a main screen and a sub screen.

【0002】[0002]

【従来の技術】1つの画面上に2つの映像内容を映し出
す所謂PIP(ピクチャーインピクチャー)が公知であ
る。PIPは、例えば特開昭61−194983号公報
に記載されている如く、親画面の映像内容と子画面の映
像内容とを切換スイッチで切換えて1つの画面上に映し
出すようにしている。
2. Description of the Related Art A so-called PIP (picture-in-picture) is known in which two image contents are displayed on one screen. As described in, for example, Japanese Patent Application Laid-Open No. 61-194983, the PIP is designed so that the image content of the main screen and the image content of the child screen are switched by a change-over switch to be displayed on one screen.

【0003】図2は、その様な二画面TV受像機を示す
回路図で、入力端子(1)からの親画面用映像信号は、
BPF(2)及びLPF(3)でクロマ信号と輝度信号
に分離され、前記BPF(2)の出力端にはクロマ信号
が、前記LPF(3)の出力端には輝度信号が得られ
る。前記クロマ信号は、ACC増幅回路(4)及びAC
C検波回路(5)から成るACC(自動色制御)回路
(6)で一定レベルに調整された後、第1混合回路
(7)に印加され、前記LPF(3)からの輝度信号と
混合される。その為、前記第1混合回路(7)の出力端
にはクロマ信号のレベルが一定の親画面用映像信号が得
られる。
FIG. 2 is a circuit diagram showing such a dual-screen TV receiver. The parent-screen video signal from the input terminal (1) is
The chroma signal and the luminance signal are separated by the BPF (2) and the LPF (3), and the chroma signal is obtained at the output end of the BPF (2) and the luminance signal is obtained at the output end of the LPF (3). The chroma signal is supplied to the ACC amplifier circuit (4) and AC.
After being adjusted to a constant level by an ACC (automatic color control) circuit (6) composed of a C detection circuit (5), it is applied to a first mixing circuit (7) and mixed with a luminance signal from the LPF (3). It Therefore, at the output terminal of the first mixing circuit (7), a parent screen video signal having a constant chroma signal level can be obtained.

【0004】一方、子画面用映像信号の内容が記憶され
たメモリ(8)の出力信号は、D−A変換回路(9)に
印加されD−A変換される。すると、D−A変換回路
(9)からB−Y及びR−Y色差信号が発生し、変調回
路(10)に印加される。変調回路(10)には前記A
CC回路(6)の出力バースト信号に同期したPLL回
路(11)の出力信号(副搬送波)が印加されており、
これを前記B−Y及びR−Y色差信号で変調する。する
と、変調回路(10)の出力端にはクロマ信号が発生
し、第2混合回路(12)でD−A変換回路(9)から
の輝度信号と混合される。その為、前記第2混合回路
(12)の出力端には子画面用映像信号が得られる。ス
イッチ回路(13)は、端子(14)からの親画面中に
子画面を挿入する為の切換制御信号に応じて切換わるよ
うに制御される。従って、図2の回路によれば、出力端
子(15)に二画面のテレビ画像を得ることが出来る。
On the other hand, the output signal of the memory (8) in which the contents of the sub-picture video signal are stored is applied to the DA conversion circuit (9) and DA converted. Then, the D-A conversion circuit (9) generates BY and RY color difference signals, which are applied to the modulation circuit (10). The modulation circuit (10) has the A
The output signal (subcarrier) of the PLL circuit (11) synchronized with the output burst signal of the CC circuit (6) is applied,
This is modulated with the BY and RY color difference signals. Then, a chroma signal is generated at the output end of the modulation circuit (10) and mixed with the luminance signal from the DA conversion circuit (9) in the second mixing circuit (12). Therefore, a sub-screen video signal is obtained at the output terminal of the second mixing circuit (12). The switch circuit (13) is controlled so as to switch according to a switching control signal for inserting the child screen into the parent screen from the terminal (14). Therefore, according to the circuit of FIG. 2, a two-screen television image can be obtained at the output terminal (15).

【0005】ところで、図2の回路においては親画面の
クロマ信号レベルをACC回路(6)の働きによって一
定レベルに制御している。そこで、子画面のクロマ信号
レベルも前記一定レベルと等しくなるように変調回路
(10)に加える入力信号レベルを調整して両信号のク
ロマレベルをそろえていた。
By the way, in the circuit of FIG. 2, the chroma signal level of the parent screen is controlled to a constant level by the action of the ACC circuit (6). Therefore, the input signal level applied to the modulation circuit (10) is adjusted so that the chroma signal level of the child screen becomes equal to the above-mentioned constant level, and the chroma levels of both signals are aligned.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、図2の
回路においては親画面のクロマ信号レベルを一定にする
為に親画面用の映像信号を輝度信号とクロマ信号とに一
旦分離した後、再び混合させるようにしているので、前
記輝度信号を分離する為のローパスフィルタを必要とす
る問題があった。前記ローパスフィルタは、コンデンサ
及びインダクターを必要とするのでICの外付けとな
り、外付部品及びICのピン数の増加を招くという問題
があった。
However, in the circuit of FIG. 2, the video signal for the main screen is once separated into the luminance signal and the chroma signal in order to keep the chroma signal level of the main screen constant, and then mixed again. Therefore, there is a problem that a low-pass filter for separating the luminance signal is required. Since the low-pass filter requires a capacitor and an inductor, the low-pass filter is externally attached to the IC, which causes a problem of increasing the number of external components and pins of the IC.

【0007】[0007]

【課題を解決するための手段】本発明は上述の点に鑑み
成されたもので、親画面用クロマ信号と子画面用クロマ
信号とのレベルを一致させる映像信号処理回路であっ
て、親画面用クロマ信号のレベル調整を行なう第1可変
利得増幅回路と、該第1可変利得増幅回路と同一の構成
を有し、子画面用クロマ信号のレベル調整を行なう第2
可変利得増幅回路と、前記第1可変利得増幅回路の出力
クロマ信号レベルを検波し、その検波出力を前記第1可
変利得増幅回路に印加するレベル検波回路と、該レベル
検波回路の検波出力と逆比例関係の制御信号を作成し、
該制御信号を前記第2可変利得増幅回路に印加する制御
回路と、から成ることを特徴とする。
The present invention has been made in view of the above points, and is a video signal processing circuit for making the levels of the chroma signal for the main screen and the chroma signal for the sub screen coincide with each other. Variable gain amplifying circuit for adjusting the level of the chroma signal for use with the first and second variable gain amplifying circuits having the same configuration as the first variable gain amplifying circuit for adjusting the level of the chroma signal for the small screen
A variable gain amplifying circuit, a level detecting circuit that detects the output chroma signal level of the first variable gain amplifying circuit, and applies the detected output to the first variable gain amplifying circuit, and a detection output that is the reverse of the detecting output of the level detecting circuit. Create a proportional control signal,
And a control circuit for applying the control signal to the second variable gain amplifier circuit.

【0008】[0008]

【作用】本発明に依れば、親画面用のクロマ信号のレベ
ル検波出力に応じて、子画面用のクロマ信号が印加され
る第2可変利得増幅回路の利得を制御しているので、子
画面のクロマレベルは親画面のクロマレベルに常に追従
するようになり、両クロマ信号のクロマレベルをそろえ
ることが出来る。その際、親画面用の映像信号はクロマ
レベルを一定にする必要がないので分離、混合する必要
が無くローパスフィルタを必要としない。又、本発明に
依れば制御回路から正確に逆比例関係の利得制御信号が
得られるので、第1及び第2VCAとして同一の回路を
使用することが出来、IC化に適すると共に正確なクロ
マ信号調整が可能となる。
According to the present invention, the gain of the second variable gain amplifier circuit to which the chroma signal for the child screen is applied is controlled according to the level detection output of the chroma signal for the parent screen. The chroma level of the screen will always follow the chroma level of the parent screen, and the chroma levels of both chroma signals can be aligned. At this time, the video signal for the main screen does not need to have a constant chroma level, so there is no need to separate and mix, and a low pass filter is not required. Further, according to the present invention, a gain control signal having an inversely proportional relationship can be accurately obtained from the control circuit, so that the same circuit can be used as the first and second VCAs, which is suitable for IC integration and an accurate chroma signal. Adjustment is possible.

【0009】[0009]

【実施例】図1は本発明の一実施例を示す回路図で、
(16)はレベル検波回路(5)の検波出力に応じて利
得αが変化する第1VCA(電圧制御増幅回路)、(1
7)は該第1VCA(16)と同一の回路構成を有する
第2VCA、(18)は第1VCA(16)と同一の回
路構成を有し、レベル検波回路(5)の検波出力に応じ
て利得αが変化する第3VCA、(19)は該第3VC
A(18)の出力信号を更にβ倍する第4VCA、(2
0)は該第4VCA(19)の出力信号と基準信号とを
比較し、その差に応じて第4VCA(19)の利得を制
御する比較回路、(21)は前記第2VCA(17)か
らの子画面用クロマ信号とD−A変換回路(9)からの
輝度信号との混合を行ない子画面用の映像信号を出力す
る混合回路である。
FIG. 1 is a circuit diagram showing an embodiment of the present invention.
(16) is a first VCA (voltage control amplifier circuit) whose gain α changes according to the detection output of the level detection circuit (5), (1
7) is a second VCA having the same circuit configuration as the first VCA (16), (18) has the same circuit configuration as the first VCA (16), and has a gain depending on the detection output of the level detection circuit (5). The third VCA in which α changes, (19) is the third VC
The fourth VCA that further increases the output signal of A (18) by β, (2
0) compares the output signal of the fourth VCA (19) with a reference signal and controls the gain of the fourth VCA (19) according to the difference between them, and (21) outputs from the second VCA (17). This is a mixing circuit that mixes the chroma signal for the sub-screen and the luminance signal from the DA conversion circuit (9) and outputs the video signal for the sub-screen.

【0010】尚、図1において図2と同一の回路素子に
ついては同一の符号を付し説明を省略する。入力端子
(1)からの親画面用映像信号は、BPF(2)でクロ
マ信号成分のみが抽出されて第1VCA(16)に印加
される。第1VCA(16)の出力信号は、レベル検波
回路(5)でレベル検波され、その検波出力に応じて第
1VCA(16)の利得が制御される。その為、前記第
1VCA(16)の出力端には一定レベルの親画面用ク
ロマ信号が得られる。PLL回路(11)は、位相比較
器、ローパスフィルタ及びVCOから構成され、入力信
号に同期した出力信号を発生するものである。その時、
前記PLL回路(11)への入力信号はレベルが一定で
あるものが望ましく、前記第1VCA(16)は、この
為に必要となっている。
In FIG. 1, the same circuit elements as those in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted. In the parent screen video signal from the input terminal (1), only the chroma signal component is extracted by the BPF (2) and applied to the first VCA (16). The output signal of the first VCA (16) is level-detected by the level detection circuit (5), and the gain of the first VCA (16) is controlled according to the detected output. Therefore, the chroma signal for the parent screen of a constant level is obtained at the output terminal of the first VCA (16). The PLL circuit (11) is composed of a phase comparator, a low pass filter and a VCO, and generates an output signal synchronized with the input signal. At that time,
The input signal to the PLL circuit (11) preferably has a constant level, and the first VCA (16) is necessary for this purpose.

【0011】一方、メモリ(8)の出力信号は、D−A
変換回路(9)でD−A変換され、変調回路(10)で
変調され、変調されたクロマ信号が第2VCA(17)
に印加される。今、第3VCA(18)の無制御時の出
力電流をI0とすれば、制御時の出力電流はαI0とな
る。その為、第4VCA(19)の出力電流はβαI0
となる。ここで、比較回路(20)の基準信号電流をK
0(ただし、Kは1未満)とすると、比較回路(2
0)の負帰還作用により β・α・I0=K・I0 ……………(1) が成立し、式(1)より第3及び第4VCA(18)及
び(19)の利得の関係は β=K/α ………………………(2) となる。式(2)より第3及び第4VCA(18)及び
(19)の利得の関係が逆比例であることが解かる。そ
れ故、比較回路(20)の出力制御信号を用いて、第2
VCA(17)の利得を制御すれば、第1VCA(1
6)と第2VCA(17)の利得を正確に逆比例の関係
にすることができる。
On the other hand, the output signal of the memory (8) is DA
The conversion circuit (9) performs D-A conversion, the modulation circuit (10) modulates, and the modulated chroma signal is the second VCA (17).
Applied to. Now, assuming that the output current of the third VCA (18) in the non-controlled state is I 0 , the output current in the controlled state is αI 0 . Therefore, the output current of the fourth VCA (19) is βαI 0
Becomes Here, the reference signal current of the comparison circuit (20) is set to K
If I 0 (where K is less than 1), the comparison circuit (2
Β) αI 0 = K · I 0 (1) is established by the negative feedback action of ( 0 ), and the gains of the third and fourth VCAs (18) and (19) are obtained from the equation (1). The relationship is β = K / α ………………………… (2). From the equation (2), it is understood that the gain relationships of the third and fourth VCAs (18) and (19) are inversely proportional. Therefore, by using the output control signal of the comparison circuit (20), the second
If the gain of VCA (17) is controlled, the first VCA (1
6) and the gain of the second VCA (17) can be made to have an exact inverse proportional relationship.

【0012】その為、親画面用のクロマ信号レベルに追
従して子画面用のクロマ信号レベルがレベル調整される
ことになり、クロマレベルの揃った二画面テレビ信号を
出力端子(15)に得られる。図3は、図1の第1乃至
第4VCA(16),(17),(18)及び(19)
と比較回路(20)の具体回路図を示すもので、第1入
力端子(22)には親画面用のクロマ信号が印加され、
第2入力端子(23)には子画面用のクロマ信号が印加
される。そして、第1出力端子(24)には親画面用の
レベル調整されたクロマ信号が得られ、第2出力端子
(25)には子画面用のレベル調整されたクロマ信号が
得られる。動作の説明は省略する。
Therefore, the chroma signal level for the sub-screen is adjusted in accordance with the chroma signal level for the main screen, and a dual-screen television signal with a uniform chroma level is obtained at the output terminal (15). Be done. FIG. 3 shows the first to fourth VCAs (16), (17), (18) and (19) of FIG.
And a specific circuit diagram of the comparison circuit (20), in which a chroma signal for the parent screen is applied to the first input terminal (22),
A chroma signal for the child screen is applied to the second input terminal (23). Then, the level-adjusted chroma signal for the parent screen is obtained at the first output terminal (24), and the level-adjusted chroma signal for the child screen is obtained at the second output terminal (25). The description of the operation is omitted.

【0013】[0013]

【発明の効果】以上述べた如く、本発明に依れば親画面
のクロマ信号レベルと子画面のクロマ信号レベルとをそ
ろえるに際し、親画面用クロマ信号のレベル検波出力に
応じて子画面のクロマ信号レベルを調整しているので、
親画面のクロマ信号にACCを施す必要がなく輝度信号
の分離混合が不要となり、その為、ローパスフィルタを
必要としない。従って、IC化に際してICの外付部品
及びピン数の削減が計れる。更に本発明によれば、第1
可変利得増幅回路と第2可変利得増幅回路に対する利得
制御信号として互いに逆比例の関係のものを供すること
ができるので、同一構成の一般的な差動増幅器を使用で
きる。その為、小レベルから大レベルまで正確に親子の
クロマ信号レベルを揃えることができる。
As described above, according to the present invention, when the chroma signal level of the main screen and the chroma signal level of the sub screen are aligned, the chroma of the sub screen is detected according to the level detection output of the chroma signal for the main screen. Since I am adjusting the signal level,
It is not necessary to apply ACC to the chroma signal of the main screen, and the separation / mixing of the luminance signal is not necessary. Therefore, a low pass filter is not required. Therefore, when integrated into an IC, the number of external parts and pins of the IC can be reduced. Further according to the invention, the first
Since the gain control signals for the variable gain amplifying circuit and the second variable gain amplifying circuit can be provided in inverse proportion to each other, a general differential amplifier having the same configuration can be used. Therefore, the chroma signal levels of the parent and child can be accurately aligned from the small level to the large level.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の映像信号処理回路を示す回路図であ
る。
FIG. 1 is a circuit diagram showing a video signal processing circuit of the present invention.

【図2】従来の映像信号処理回路を示す回路図である。FIG. 2 is a circuit diagram showing a conventional video signal processing circuit.

【図3】図1の具体回路例を示す回路図である。FIG. 3 is a circuit diagram showing a specific circuit example of FIG.

【符号の説明】[Explanation of symbols]

(5) レベル検波回路 (16) 第1VCA (17) 第2VCA (18) 第3VCA (19) 第4VCA (20) 比較回路 (5) Level detection circuit (16) First VCA (17) Second VCA (18) Third VCA (19) Fourth VCA (20) Comparison circuit

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 親画面用クロマ信号と子画面用クロマ信
号とのレベルを一致させる映像信号処理回路であって、
親画面用クロマ信号のレベル調整を行なう第1可変利得
増幅回路と、 該第1可変利得増幅回路と同一の構成を有し、子画面用
クロマ信号のレベル調整を行なう第2可変利得増幅回路
と、 前記第1可変利得増幅回路の出力クロマ信号レベルを検
波し、その検波出力を前記第1可変利得増幅回路に印加
するレベル検波回路と、 該レベル検波回路の検波出力と逆比例関係の制御信号を
作成し、該制御信号を前記第2可変利得増幅回路に印加
する制御回路と、 から成ることを特徴とする映像信号処理回路。
1. A video signal processing circuit for matching the levels of a master-screen chroma signal and a child-screen chroma signal,
A first variable gain amplifying circuit for adjusting the level of the chroma signal for the main screen, and a second variable gain amplifying circuit for adjusting the level of the chroma signal for the small screen, which has the same configuration as the first variable gain amplifying circuit A level detection circuit that detects the output chroma signal level of the first variable gain amplification circuit and applies the detection output to the first variable gain amplification circuit; and a control signal that is inversely proportional to the detection output of the level detection circuit. And a control circuit for applying the control signal to the second variable gain amplifier circuit, and a video signal processing circuit.
【請求項2】 前記制御回路は、 前記レベル検波回路の検波出力に応じて利得が変化する
第3可変利得増幅回路と、 該第3可変利得増幅回路の出力信号を更に増幅する第4
可変利得増幅回路と、 該第4可変利得増幅回路の出力信号と基準信号とのレベ
ル比較を行ない、その差に応じて前記第4可変利得増幅
回路の利得を制御する比較回路と、 から成り、前記比較回路の比較出力信号に応じて前記第
2可変利得増幅回路の利得制御を行なうようにしたこと
を特徴とする請求項1記載の映像信号処理回路。
2. The control circuit further comprises a third variable gain amplifier circuit whose gain changes according to the detection output of the level detection circuit, and a fourth variable gain amplifier circuit which further amplifies the output signal of the third variable gain amplifier circuit.
A variable gain amplifier circuit; and a comparator circuit that performs level comparison between the output signal of the fourth variable gain amplifier circuit and a reference signal, and controls the gain of the fourth variable gain amplifier circuit according to the difference between them. 2. The video signal processing circuit according to claim 1, wherein the gain control of the second variable gain amplifier circuit is performed according to the comparison output signal of the comparison circuit.
JP04104643A 1992-04-23 1992-04-23 Video signal processing circuit Expired - Fee Related JP3096519B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP04104643A JP3096519B2 (en) 1992-04-23 1992-04-23 Video signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP04104643A JP3096519B2 (en) 1992-04-23 1992-04-23 Video signal processing circuit

Publications (2)

Publication Number Publication Date
JPH05300429A true JPH05300429A (en) 1993-11-12
JP3096519B2 JP3096519B2 (en) 2000-10-10

Family

ID=14386138

Family Applications (1)

Application Number Title Priority Date Filing Date
JP04104643A Expired - Fee Related JP3096519B2 (en) 1992-04-23 1992-04-23 Video signal processing circuit

Country Status (1)

Country Link
JP (1) JP3096519B2 (en)

Also Published As

Publication number Publication date
JP3096519B2 (en) 2000-10-10

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