JPH05300379A - Code quantity distribution circuit - Google Patents

Abstract

PURPOSE:To attain ideal bit distribution for fixed length processing. CONSTITUTION:A total activity calculation section 42 integrates a block activity to obtain the total activity. A correction quantity calculation section 45 obtains a calculation equation for the correction in response to a compression rate by the training method and uses a normalizing coefficient alpha as a variable to obtain the correction quantity of a distributed bit number. A subtructor 43 subtracts the correction from the block activity to obtain the block activity after the correction. A multiplier 46 multiplies a total correction quantity with the correction quantity to obtain the total correction quantity and a subtractor 44 subtracts the total correction quantity from the total activity to obtain the total activity after the correction. A divider 33 obtains a ratio of outputs of the subtractors 43, 44 to obtain an activity ratio and a multiplier 43 multiplies the activity ratio with an AC total bit number to obtain a distributed bit number. The activity ratio is corrected and the ideal bit distribution is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code amount distribution circuit for making the code amount of an orthogonal transform coding device for compressing image data by orthogonal transform coding a constant rate.

[0002]

2. Description of the Related Art In recent years, a system for highly efficiently encoding and recording or transmitting image information has become widespread. The amount of information of a digitized still image is enormous as compared with the amount of information of voice and the like, and if transmission or recording is performed without compressing information, there are many problems in terms of communication speed and cost. For this reason,
Still image data is compressed at a high compression rate even if some deterioration in image quality is allowed. In response to such movement, ISO (In
ternational Organization for Standardization) and C
CITT (International Telegraph and Telephone Co
Joint Photographic Experts Group (JPEG), a joint international working group of the nsultative Committee, is a type of orthogonal transform called DCT (Discrete Cosine Transfor).
We have proposed a proposal for efficient coding of still images using m).

FIG. 6 is a block diagram for explaining the encoding according to this recommendation.

In this system, still image data is converted to DCT.
After (discrete cosine transform) processing, Huffman coding, which is a type of entropy coding, is performed to compress the data. The input image data is given to the DCT circuit 2 in the block formation circuit 1 in block units of, for example, 8 × 8 pixels. The DCT circuit 2 DCT-processes the block data and outputs the transform coefficient to the quantization circuit 3. The DCT transform coefficient from the DCT circuit 2 has frequency components in the horizontal and vertical directions from low to high frequencies, and the average value of all data is D.
The C component is given to the quantizing circuit 3, and the other components are given to the quantizing circuit 3 as AC components. The quantizing circuit 3 quantizes the DCT transform coefficient based on the quantizing coefficient stored in a quantizing table (not shown) to reduce the data amount, and to reduce the DP amount.
Output to the CM circuit 5 and the zigzag scan circuit 7.

The DPCM circuit 5 is provided with a quantized output for the DC component of the transform coefficient, and the DPCM circuit 5 stores the DC value in the memory 4 and reads it out to obtain the difference from the DC component of the previous block. This difference value is given to the DC Huffman coding circuit 6 for DC components to be coded. That is, the DC Huffman encoding circuit 6 uses the DC (not shown).
The code length of the difference value is Huffman-encoded by referring to the Huffman table for use, and the data of the combination of the Huffman code and the code of the difference value is output to the multiplexer (hereinafter referred to as MUX) 10.

On the other hand, the quantized output for the AC component of the transform coefficient is zigzag-scanned in the zigzag scanning circuit 7 from the low band in the horizontal and vertical directions to the high band and is read. The zero run length measuring unit 8 includes a zigzag scan circuit 7
It is reset by the non-zero coefficient value of the output of and counts the number of consecutive zero data (zero run length). When a non-zero value is input, the zero run length measuring unit 8 outputs the zero run length to the AC Huffman coding circuit 9. The AC Huffman encoding circuit 9 is also supplied with the quantized output of the AC component from the zigzag scan circuit 7. When the non-zero coefficient and the zero-run length from the zero-run length measuring unit 8 are input, the AC Huffman coding circuit 9 uses a Huffman table (not shown) to set a pair of data of the zero-run length and the code length of the non-zero coefficient. Is Huffman encoded. Further, the AC Huffman coding circuit 9 adds the code of the non-zero coefficient to the generated Huffman code and outputs it to the MUX 10. The MUX 10 synthesizes and outputs the Huffman codes of the DC component and the AC component.

On the decoding side (not shown), the Huffman code is first decoded to obtain the zero run length and the code length of the non-zero coefficient value, and the coefficient value is discriminated using these code lengths. In this way, a transform coefficient block is formed, and further inverse quantization and orthogonal inverse transform are performed to restore data.

By the way, the Huffman coding circuits 6 and 9 are
Variable-length coding that assigns short bits to data with a high occurrence probability and long bits to data with a low occurrence probability. Reduce the total amount of data. Therefore, the data amount after encoding changes depending on the statistical distribution of the quantized output.

However, when the variable length coding is adopted, the compression code amount varies depending on the picture. Therefore, when the compressed data is recorded in the storage medium, it is possible to know the capacity of the storage medium required for recording before recording. No, and the storage media cannot be used efficiently. For example,
When applied to an electronic camera, the number of recordable images is not constant even if the capacity of the recording medium is constant. Therefore, a method of making the compression code amount a constant rate may be adopted.

For example, by changing the quantization coefficient given to the quantization circuit 3, it is possible to roughly control the code amount. If you set the quantization factor to a relatively large value,
Although the quantization step becomes coarse and the information deteriorates, the dynamic range of the quantization output becomes small and the code amount also becomes small. In practice, a method of multiplying the basic quantization coefficient of the quantization table by the normalization coefficient α is adopted. Further, when a predetermined code amount is assigned to each block in advance (block bit allocation), and the code output exceeds the assigned code amount,
A method of stopping the coding in the block may be adopted.

In the case of controlling the normalization coefficient α to make it a constant rate, the normalization coefficient α is appropriately changed until it converges to the specified code amount, and the coding is repeated. In this method, the time required for convergence is unknown and the final encoding may take a long time. On the other hand, when only bit allocation is performed, the code amount may not reach the specified code amount, a relatively large number of extra bits may be generated, and the block high frequency component may not be used at all.

Therefore, a method is adopted in which the control of the normalization coefficient α and the block bit allocation are used together to keep the total code amount within the specified code amount. In this method, first, the amount of information (hereinafter referred to as activity) for each block is calculated in order to estimate the code amount of the image. As an activity,
There are a method of using the sum of deviation amounts of block data, a method of using the sum of absolute values of DCT transform coefficients, and a method of using the sum of bit lengths of transform coefficients. Further, the normalization coefficient α is obtained as a function of the total sum of activities. The distribution bit number is obtained by multiplying the specified code amount by the ratio of the block activity and the total sum of the activities. In this method, the normalization coefficient α
Also, it is sufficient to perform two scans, that is, a scan of all image data for obtaining the bit allocation and a scan at the time of actual encoding, and high-speed fixed-length encoding is possible.

FIG. 7 is a block diagram showing an orthogonal transform coding apparatus for performing such a scan twice. In the example of FIG. 7, DCT processing is adopted for orthogonal transformation. In the figure, the broken line arrow indicates the process of the first scan, and the solid line arrow indicates the process of the second scan.

First, in the first scan, the total activity of the image is obtained and the parameters for fixing the code length are set. That is, the input image is divided into blocks in the blocking circuit 1 and given to the DCT circuit 2. D
The CT circuit 2 performs DCT processing and outputs a transform coefficient.
Since the DC component of the transform coefficient is an important quantity, its code quantity is first obtained. That is, the DC component of the transform coefficient is quantized in the DC quantizing circuit 11, and then the DPCM circuit 5 obtains the difference value from the DC component value of the previous block and gives it to the DC Huffman coding circuit 6. DC Huffman encoding circuit 6
Refers to the DC Huffman table 12 and the DPCM circuit 5
Huffman-encode the output of. The encoded output from the DC Huffman encoding circuit 6 is given to the DC total code amount calculation unit 13,
The total code amount of the encoded output of the DC component is calculated. The calculated DC total code amount is given to the block bit allocation control unit 14.

On the other hand, the AC component of the conversion coefficient is given to the block activity calculating section 15. The block activity calculation unit 15 counts the code length of the transform coefficient to obtain the block activity. The total activity calculation unit 20 adds the activities of each block to obtain the total activity. In order to keep the code amount within the specified code amount, the normalization coefficient α calculation unit 16 calculates the normalization coefficient α that normalizes the basic quantization coefficient stored in the quantization table 17 using the obtained total activity. To do. This completes the operation of the first scan.

Next, in the second scan, actual encoding is performed. As with the first scan, the transform coefficient from the DCT circuit 2 is the DC quantizing circuit 11 and DPCM for the DC component.
It is encoded by the circuit 5 and the DC Huffman encoding circuit 6 and output to the MUX 10. Further, the block activity calculation unit 15 calculates the block activity from the DCT transform coefficient and gives it to the block bit allocation control unit 14. The block bit allocation control unit 14 obtains the total code amount (AC total code amount (the number of bits)) that can be used for the AC component by calculating (the specified code amount of the image-the DC total code amount).

On the other hand, the AC component of the DCT transform coefficient is given to the AC quantizing circuit 19. The basic quantization coefficient of the quantization table 17 is normalized by the normalization coefficient α and stored in the normalized quantization table 18. The AC quantization circuit 19 quantizes the AC component based on the quantized coefficient from the normalized quantization table 18 and outputs the quantized AC component to the AC Huffman encoding circuit 9 via the zigzag scan circuit 20. The zigzag scanning circuit 20 outputs a quantized output in a zigzag manner from a low band in the horizontal and vertical directions to a high band.

The AC Huffman encoding circuit 9 two-dimensionally Huffman-encodes the data of the set of the zero run length and the code length of the non-zero coefficient by referring to the AC Huffman table 21 to perform MUX 10.
Output to. In this case, the block bit allocation control unit
14 allocates bits to each block.
That is, the block bit allocation control unit 14 calculates the number of allocated bits of each block by (prescribed code amount of image−DC total code amount) ×
Determined by calculation of (block activity / total activity). The code amount of the encoded data from the AC Huffman encoding circuit 9 is given to the block bit allocation control unit 14. The block bit distribution control unit 14 outputs a coding stop command to the AC Huffman coding circuit 9 when the integrated value of the code amount of the coded data exceeds the number of allocated bits of the block.
Then, the AC Huffman coding circuit 9 stops the coding process and does not output the coded data that exceeds the block allocation bit number. The MUX 10 multiplexes the encoded outputs for the AC component and the DC component and outputs the multiplexed outputs. Thus, the total code amount is prevented from exceeding the specified code amount.

As described above, in the apparatus of FIG. 7, the normalization coefficient α for normalizing the basic quantization coefficient is controlled based on the total activity of one screen, and the bit allocation is determined for each block. The code length is fixed.

FIG. 8 is a block bit allocation control unit in FIG.
FIG. 14 is a block diagram showing a specific configuration of 14.

The distribution bit number calculation unit 23 of the block bit distribution control unit 14 is provided with the DC total code amount (bit number), total activity and block activity. As described above, the distributed bit number calculation unit 23 calculates the DC from the specified code amount.
The total number of bits is subtracted to obtain the total number of AC bits, and further, the number of distributed bits for each block is obtained from the total activity and the block activity and output to the comparator 24.

On the other hand, the DCT processed and quantized block data is stored in the block memory 22. The zigzag scan circuit 20 reads the data in the block memory 22 in a zigzag manner, and outputs the data of the set of the zero run length and the code length of the non-zero coefficient value to the AC Huffman encoding circuit 9. AC
The Huffman coding circuit 9 refers to the AC Huffman table 21 to convert the data of the combination of the zero run length and the code length of the non-zero coefficient value into the Huffman code. AC Huffman encoding circuit 9
The code amount of the output of is supplied to the comparator 24 via the accumulator 25.

The accumulator 25 integrates the code amount and gives the integrated code amount to the comparator 24, and the comparator 24 compares the integrated code amount of a predetermined block with the block allocation bit number. When the accumulated code amount from the accumulator 25 exceeds the block allocation bit number, the comparator 24 outputs an encoding stop command to the AC Huffman encoding circuit 9, and the difference between the accumulated code amount and the block allocation bit number before the excess. The (remainder bit number) is output to the distributed bit number calculation unit 23 as the carry-over bit number. This carry-over bit number is added to the block distribution bit number in the next block and carried over. When the coding stop command is input, the AC Huffman coding circuit 9 stops coding and outputs a coding output within the number of block allocation bits.

By the way, the number of bits allocated to each block is
As described above, it is calculated using the ratio of block activity and total activity (hereinafter referred to as activity ratio). That is, the ratio between the predicted distribution bit number of each block and the AC total bit number (hereinafter referred to as the distribution bit ratio) matches the activity ratio. However, the block activity is not a value obtained from the number of bits actually used for encoding, but a predicted value, and the ideal allocation bit ratio may not match the activity ratio.

FIG. 9 is a block diagram showing a conventional code amount distribution circuit 31 for calculating the distribution bit number. This circuit corresponds to the block activity calculation unit 15, the total activity calculation unit 20, and the block bit allocation control unit 14 in FIG. 7.

The output of the DCT circuit is the activity integrating section.
Give to 32. The activity integrating section 32 integrates the absolute value of the AC component of the DCT transform coefficient for one block to obtain the block activity, and integrates the block activity to obtain the total activity. The block activity and the total activity are given to the divider 33 to obtain the ratio of both. The divider 33 outputs the obtained ratio to the multiplier 34 as an activity ratio. The AC total bit number is also supplied to the multiplier 34, and the multiplier 34 multiplies the AC total bit number by the activity ratio to obtain the distribution bit number of each block.

FIG. 10 is a graph for explaining the characteristics of the conventional code amount distribution circuit 31 of FIG. FIG. 10 shows the characteristics when the compression ratio is set to 1/4 by taking the activity ratio on the horizontal axis and the distribution bit ratio on the vertical axis. Figure 1
The straight line of 0 indicates the characteristic of the code amount distribution circuit 31, and the dot indicates the ideal characteristic actually measured for a certain image. Figure 10
As shown in FIG. 9, when the bit allocation by the code amount allocation circuit 31 of FIG. 9 is adopted, the deviation from the ideal characteristic is relatively large. Especially when the activity ratio is relatively high, that is, when the screen is relatively fine, the calculated allocation bit ratio is much larger than the ideal allocation bit ratio, and unnecessary bits are allocated. I understand that.

FIG. 11 is a block diagram showing a conventional code amount distribution circuit 35 adopting another method.

The DCT conversion coefficient is calculated by the activity integrating section 36.
Give to. The activity integrating section 36 integrates the number of bits of the AC component of the conversion coefficient for one block to obtain the block activity, and integrates the block activity to obtain the total activity. The divider 33 obtains the activity ratio from the ratio of the block activity and the total activity from the activity accumulator 36, and the multiplier 34 multiplies the activity ratio by the AC total bit number to obtain the distributed bit number.

12 and 13 are graphs showing the characteristics of the code amount distribution circuit 35 with the activity ratio on the horizontal axis and the distribution bit ratio on the vertical axis. FIG. 12 shows the characteristics when the compression rate is set to 1/4, and FIG. 13 shows the characteristics when the compression rate is set to 1/16.

When the compression rate is set to 1/4, as shown in FIG. 12, the distribution bit number of the code amount distribution circuit 35 becomes substantially equal to the ideal distribution bit number, and highly accurate bit distribution is performed. I understand. However, the compression rate is 1/16
If it is set to a high level, as shown in FIG.
Therefore, the bit allocation due to is significantly different from the ideal bit allocation. This is because the compression rate is increased by increasing the normalization coefficient α, and the amount of information bits to be deleted increases in quantization, resulting in an error in the activity ratio.

[0032]

As described above, the conventional code amount distribution circuit described above has a problem in that the difference between the calculated bit distribution and the ideal bit distribution is relatively large.

It is an object of the present invention to provide a code amount distribution circuit capable of performing ideal bit allocation by correcting the predicted allocation bit number.

[0034]

A code amount distribution circuit according to the present invention is configured to orthogonally transform and code an input video signal in units of a predetermined block and quantize the coded output to obtain a coded output at a constant rate. In a code amount distribution circuit for allocating the usable code amount, a distribution amount for predicting the distribution amount of each block by obtaining the ratio of the index indicating the information amount of each block and the index indicating the information amount of all blocks Prediction means,
A code amount distribution circuit, comprising: a correction unit that corrects a prediction error of the distribution amount prediction unit generated by the quantization based on an index indicating the information amount of all the blocks or a quantization characteristic.

[0035]

In the present invention, the distribution amount predicting means predicts the distribution amount by obtaining the ratio of the index indicating the information amount of each block and the index indicating the information amount of all blocks. The correction means corrects the predicted value based on the index indicating the information amount of all blocks or the quantization characteristic. As a result, the distribution amount changed due to the loss of information due to quantization is corrected.

[0036]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a code amount distribution circuit according to the present invention. The present embodiment is applied to the orthogonal transform coding device of FIG.

The total number of AC bits, the block activity, and the normalization coefficient α are input to the code amount distribution circuit 41. A
The total number of C bits is the first from the specified code amount that can be used for encoding.
It is obtained by subtracting the total DC bit number calculated in the scan. The block activity is a sum of deviation amounts of block data, a sum of absolute values of DCT transform coefficients of one block, a sum of bit lengths of DCT transform coefficients of one block, or the like. The normalization coefficient α is a function of the total activity, and adjusts the basic quantization coefficient to determine the compression ratio of the screen.

The block activity is supplied to the total activity calculator 42 and the subtractor 43. The total activity calculation unit 42 calculates the total activity by adding up the block activities of all blocks and outputs the total activity to the subtractor 44. The normalization coefficient α is given to the correction amount calculation unit 45. The correction amount calculation unit 45 calculates a correction amount for correcting the activity ratio and outputs it to the subtractor 43 and the multiplier 46. The correction amount calculation unit 45 calculates the correction amount based on a first-order correction equation having a compression rate (normalization coefficient α) as a variable. The constant term of this linear expression is determined by a training method by actually performing image compression.

The subtractor 43 subtracts the correction amount from the block activity and outputs the corrected block activity to the divider 33. The multiplier 46 multiplies the correction amount by the total number of blocks to obtain the total correction amount. Output to the subtractor 44. The subtractor 44 subtracts the total correction amount from the total activity and outputs the corrected total activity to the divider 33. The divider 33 outputs the ratio of the corrected block activity and the corrected total activity to the multiplier 34 as an activity ratio.
The multiplier 34 multiplies the AC total bit number by the activity ratio to obtain the distribution bit number and outputs it.

Next, the operation of the embodiment thus constructed will be described with reference to the graphs of FIGS. In FIG. 2, the horizontal axis represents the normalization coefficient α and the vertical axis represents the correction amount,
6 is a graph for explaining the correction amount calculation unit 45.

The block activity is given to the total activity calculator 42 and the subtractor 43. The total activity calculation unit 42 integrates the block activities to obtain the total activity and outputs it to the subtractor 44. The subtractor 43 subtracts the correction amount from the block activity to obtain the corrected block activity. The correction amount is calculated by the correction amount calculation unit 45.
Calculate by The correction amount calculation unit 45 first compresses a plurality of images and obtains a calculation formula for obtaining an optimum correction amount by a training method. FIG. 2 shows a calculation formula of the correction amount when the compression rate of the screen is set to 1/16 by the broken line. The □ mark in FIG. 2 is obtained by actually measuring the ideal correction amount in the actual encoding. For example, in FIG.
Then, when the normalization coefficient α of the predetermined screen when the image compression ratio is set to 1/16 is 0.9, the correction amount is 45
Shows that an ideal bit allocation was obtained.

The correction amount calculation unit 45 obtains the correction amount corresponding to the normalization coefficient α based on the calculation formula by the training method and outputs it to the subtractor 43 and the multiplier 46. Multiplier
Reference numeral 46 multiplies the correction amount by the total number of blocks to obtain the total correction amount for one screen, and outputs it to the subtractor 44. The subtractor 44 subtracts the total correction amount from the total activity to obtain the corrected total activity, and outputs the corrected total activity to the divider 33. The divider 33 obtains the ratio between the corrected block activity and the total activity and outputs it as the activity ratio to the multiplier 34. The multiplier 34 multiplies the AC total bit number by the activity ratio to obtain the distribution bit number.

In FIG. 3, the horizontal axis represents the activity ratio from the divider 33, and the vertical axis represents the distribution bit ratio.
It is a graph which shows the characteristic of the example in case of being 16. In FIG. 3, the straight line indicates the characteristic of the embodiment circuit, and the dots indicate the ideal characteristic actually measured for a certain image.

As shown in FIG. 3, the activity ratio from the divider 33 is calculated by calculating the activity ratio after correcting the block activity and the total activity with the correction amount based on the linear expression obtained by the training method. The prediction result and the ideal allocation bit ratio substantially match, and the predicted distribution bit number of each block and the ideal distribution bit number substantially match.

As described above, in the present embodiment, the correction amount calculation unit 45 obtains the primary correction formula of the distribution bit number with the normalization coefficient α corresponding to the definition of the image as a variable by the training method. The block activity and the total activity are corrected by calculating the correction amount based on the normalization coefficient α using this linear expression, and even if the compression ratio is relatively high, the predicted activity ratio is ideally allocated to bits. Can match the ratio. Therefore, the number of bits allocated to each block is ideal, and good coding can be performed regardless of the compression ratio.

FIG. 4 is a block diagram showing another embodiment of the present invention. 4, the same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

The code amount distribution circuit 51 of this embodiment differs from the embodiment of FIG. 1 only in the correction amount calculation unit 52, and the correction amount calculation unit 52 is
The correction amount is calculated using the total activity from the total activity calculation unit 42 and output to the subtractor 43 and the multiplier 46. At the time when the first scan is completed, the total activity is given to the correction amount calculation unit 52 to calculate the correction amount of bit allocation.

In the embodiment constructed as described above,
The correction amount is determined based on the total activity. The normalization coefficient α is a function of the total activity, and by correcting the block activity and the total activity based on the correction amount from the correction amount calculation unit 52, it is possible to obtain a substantially ideal allocation bit number.

FIG. 5 is a block diagram showing another embodiment of the present invention. 5, the same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

In the code amount distribution circuit 55 of this embodiment, the sum of the bit lengths of the quantized outputs for the AC components of the DCT transform coefficients is given to the correction amount calculation section 56 instead of the normalization coefficient α. 1 is different from the first embodiment. The DCT transform coefficient is given to the AC quantization circuit 19. The AC quantization circuit 19 quantizes the AC component of the DCT transform coefficient based on the quantized coefficient from the normalized quantization table 18, and outputs it to the addition circuit 57. Adder circuit
57 sequentially adds the quantized outputs and outputs the sum of the bit lengths of the quantized outputs to the correction amount calculation unit 56. At the end of the first scan, the sum of the bit lengths of the quantized coefficients is given to the correction amount calculation unit 56 to calculate the correction amount of bit allocation.

In the embodiment thus constructed,
The correction amount calculation unit 56 determines the correction amount based on the total bit length of the quantized output. Even in this case, similarly to the embodiment of FIG. 1, by correcting the block activity and the total activity based on the correction amount from the correction amount calculation unit 56, it is possible to obtain a substantially ideal number of allocated bits.

Although the normalized quantization table 18 used for encoding is used in this embodiment, a unique quantization table may be used.

[0053]

As described above, according to the present invention, since the predicted distribution amount is corrected, there is an effect that ideal bit distribution can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a code amount distribution circuit according to the present invention.

FIG. 2 is a graph for explaining the operation of the embodiment of FIG.

FIG. 3 is a graph for explaining the operation of the embodiment of FIG.

FIG. 4 is a block diagram showing another embodiment of the present invention.

FIG. 5 is a block diagram showing another embodiment of the present invention.

FIG. 6 is a block diagram showing an orthogonal transform encoding device.

FIG. 7 is a block diagram showing an orthogonal transform encoding device.

8 is a block diagram showing a specific configuration of a block bit allocation control unit in FIG.

FIG. 9 is a block diagram showing a conventional code amount distribution circuit.

10 is a graph showing the characteristics of the conventional example of FIG.

FIG. 11 is a block diagram showing a conventional code amount distribution circuit.

12 is a graph showing characteristics of the conventional example of FIG.

13 is a graph showing characteristics of the conventional example of FIG.

[Explanation of symbols]

33 ... Divider, 34, 46 ... Multiplier, 41 ... Code amount distribution circuit, 42
… Total activity calculator, 43, 44… Subtractor, 45… Correction amount calculator

Claims (2)

[Claims] 1. A code amount distribution circuit for allocating a code amount usable to each block in order to convert a coded output obtained by orthogonal transform coding and quantizing an input video signal in a predetermined block unit into a constant rate. A distribution amount prediction unit that predicts a distribution amount of each block by obtaining a ratio of an index indicating the information amount of each block and an index indicating the information amount of all blocks; and the distribution amount prediction generated by the quantization. And a correction means for correcting the prediction error of the means. 2. A code amount allocating circuit for allocating a code amount usable to each block in order to convert a coded output obtained by orthogonal transform coding and quantizing an input video signal in a predetermined block unit into a constant rate. A distribution amount prediction unit that predicts a distribution amount of each block by obtaining a ratio of an index indicating the information amount of each block and an index indicating the information amount of all blocks; and the distribution amount prediction generated by the quantization. And a correction means for correcting the prediction error of the means.