JPH0529941A - A/d converter - Google Patents

Abstract

PURPOSE:To reduce the area of configuration and power consumption by using a voltage comparator circuit used for the step 1 also for the step 2 in common so as to form the voltage comparator circuits whose number is a half of number of serial parallel D/A converters. CONSTITUTION:Switch circuits SA0/SA2 are closed and an input VAIN is inputted to voltage comparator circuits C0-C2. After the end of sampling, a switch circuit SB1 is closed and then the circuit SB0 is closed to impress an output of a D/A converter to the voltage comparator circuits C0, C1 and the output is compared with an analog input. Then the switch circuits SC0-SC2 are closed and switches S0--S3 are closed to impress the output of the D/A converter to the voltage comparator of conversion of 4-bit accuracy. In this case, since a voltage C1. Since the charge is not lost nor injected for the period of the result of conversion of 4-bit accuracy. In this case, since a voltage Va is not negative, a charge is not injected in a capacitive element step 1 in the capacitive element of the output of the voltage comparator circuit used for the period in the step 1, the voltage comparator circuit is used in common for the step 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter, and more particularly to a serial / parallel A / D converter.

[0002]

2. Description of the Related Art FIG. 6 shows an example of a conventional A / D converter.
As shown in, the analog input terminal (A _IN ), the digital output terminal (D _OUT ), the D / A converter, the six voltage comparison circuits (C _{0 to} C ₅ ) and the encoder are provided, and the voltage comparison circuit ( The inputs of C _{0 to} C ₅ are switch circuits (SA0 to SA).
5) is connected to the analog input terminal (A _IN ) via the switch circuit (SB0 to SB2, SC3 to SC).
5) is connected to the output of the D / A converter, the output of the voltage comparison circuit (C _{0 to} C ₅ ) is input to the encoder, and the output of the encoder is input to the D / A converter and digital output. 4bi configured by connecting to the terminal (D _OUT )
There are t serial-parallel A / D converters. The D / A converter that constitutes the present A / D converter is a switch (S _{0 to} S ₃ ) in which the resistance element (R) connected between + V _REF and −V _REF is controlled by the output of the encoder. It is configured. The voltage comparison circuits (C _{0 to} C ₅ ) are, as shown in FIG. 5A, a P-channel MOS-FET (P ₁ ) and an N-channel MOS-.
An inverter composed of an FET (N ₁ ), and an N-channel MOS-FET connected between the input and output (OUT) of the inverter and having a gate to which a sampling signal (φ _S ) is applied.
(N ₂ ) and the input-output (OUT) of the inverter, and between the input-input (IN) of the P-channel MOS-FET (P ₂ ) and the inverter to which the inverted gate signal is applied to the gate. It is composed of connected capacitive elements (C ₁ ). Further, as shown in FIG. 5B, the differential amplifier (DAMP) and the two inputs (-of the differential amplifier (DAMP))
And +) are applied to the gates of the N-channel MOS-FETs (N ₃ and N ₄ ) to which the sampling signal (φ _S ) is applied, and to the gates of the P-channel MOS-FETs (P ₃ and N ₄ ) to which the inverted sampling signal is applied. It is also possible to use a voltage comparison circuit that is connected to the bias voltage terminal (V _B ) via P ₄ ) and to the input (IN) and GND via the capacitive elements (C ₂ and C ₃ ). Good.

Next, the operation will be described with reference to FIGS. First, during the sampling period, the switch circuits (SA0-SA5) are closed to close the analog input terminal (A _IN ).
The analog input (V _AIN ) input to is applied to the inputs of the voltage comparison circuits (C _{0 to} C ₅ ). When the circuit shown in FIG. 5A is used as the voltage comparison circuit (C _{0 to} C ₅ ), the sampling signal (φ _S ) becomes high and the inverted sampling signal becomes low, and the N-channel type M
OS-FET (N ₂ ) and P-channel MOS-FET
(P ₂ ) turns on and the inverter input is output (OUT)
Are short-circuited, and the logical threshold voltage of the inverter (about 1/2
V _CC ) and the capacitor (C ₁ ) has a charge proportional to the analog input (V _AIN ): (V _AIN −1/2)
V _CC ) × C ₁ is stored. In addition, the voltage comparison circuit (C _{0 to} C
₅ ), when the circuit shown in FIG. 5B is used, the sampling signal (φ _S ) is inverted to high and the sampling signal becomes low, and the N-channel MOS-FET (N ₃
, N ₄ ) and P-channel type MOS-FETs (P ₃ and P ₄ ) are turned on, the inputs (− and +) of the differential amplifier (DAMP) are biased to the bias voltage (V _B ), and the capacitive element (C _{In 2} ), a charge proportional to the analog input (V _AIN ): (V _AIN −V _B ) × C ₂ is stored. Then, when the switch circuits (SA0 to SA5) are opened, the sampling signal (φ _S ) becomes low, and the inverted sampling signal becomes high, so that the N-channel MOS-FET (N ₂ ) P
Channel type MOS-FET (P ₂ ) and N channel type M
Sampling ends OS-FET (N ₃ and N ₄₎ are turned off.

Then, in step 1, a switch circuit (SB0
～SB2) is applied to the input of 2bit accuracy of the D / A converter output voltage comparator circuit (C ₀ ~C ₂₎ closed, the analog input and the D / A converter output voltage comparator circuit (C ₀ ~
C ₂ ). Here, if the D / A converter output is lower than the analog input, a high signal is output. If the D / A converter output is higher than the analog input signal, a low signal is output from the voltage comparison circuit (C
_{0 to} C ₂ ) and encoded by an encoder to obtain a rough conversion result with 2-bit precision.

Next, in step 2, a switch circuit (SC3 ...
SC5) is closed, and one of the switches S _0, S ₁ is S ₂ or S ₃ is closed according to the conversion result obtained in step 1 to output a 4-bit precision D / A converter output to a voltage comparison circuit. (C ₃ ~C ₅₎ is applied to the input of a voltage comparator circuit (C ₃ ~C ₅₎ outputs encoded in 4-bit precision of the conversion result by the encoder of the resulting.

[0006]

[Problems that the Invention is to Solve In this conventional A / D converter, the case of using the voltage comparator circuit shown in FIG. 5 (a), the input of the sampling period the capacitor element (C ₁₎ (I
The voltage on the N side is the analog input (V _AIN ) and the voltage on the inverter side is the logical threshold voltage of the inverter (about 1/2).
Biased to V _CC ) and input (IN) in subsequent step 1
Voltage side is given D / A converter output voltage (V D _{/ A)} and became when the inverter side voltage (v _a) is given by the following equation (1).

[0007]

From the above equation, for example, when V _AIN = 0 [V], V _{D / A} > 1/2 V _CC and v _a becomes equal to or higher than the power supply voltage (V _CC ) and the drain of the P-channel type MOS-FET (P ₂ ). (P
Type diffusion layer) is forward biased, the electric charge stored in the capacitive element (C ₁ ) is lost, and V _{DIN / A} <1 when V _AIN = V _CC
At / 2V _CC , v _a becomes a negative voltage and N-channel MOS-F
The drain (N-type diffusion layer) of ET (N ₂ ) is forward-biased and charges are injected into the capacitive element (C ₁ ). Also, FIG.
When the voltage comparison circuit shown in (b) is used, the voltage on the input (IN) side of the capacitive element (C ₂ ) for the sampling period is the analog input (V _AIN ), and the voltage on the differential amplifier (DAMP) side is the bias voltage ( Biased to V _B ), followed by step 1
And the voltage on the input (IN) side is the output voltage of the D / A converter (V
_{D / A} ), the voltage (V _B ) on the differential amplifier (DAMP) side is given by the following equation (2).

[0009]

From the above equation, when VAIN = 0 [V], V _{D / A}
> (V _CC −V _B ), v _b becomes equal to or higher than the power supply voltage (V _CC ), and the drain (P type diffusion layer) of the P channel type MOS-FET (P ₃ ) is forward biased to the capacitive element (C ₂ ). When the stored charge is lost and V _AIN = V _CC , V _{D / A} <(V
_CC -V _B) in v _b becomes negative voltage N-channel type MOS-
The drain (N-type diffusion layer) of the FET (N ₃ ) is forward-biased and charges are injected into the capacitive element (C ₂ ).

As described above, in the capacitive element of the voltage comparison circuit used in step 1, during the period of step 1,
The voltage comparison circuit used in step 1 cannot be used in step 2 because the analog input value stored in the capacitive element is destroyed due to the dissipation or injection of charges, and the voltage comparison circuit used in step 1 In addition to this, there is a problem that the voltage comparison circuit used in step 2 must be configured.

Further, there is a problem that carriers are injected into the substrate from the drain of the MOS-FET, and the injected carriers are absorbed by the connection point having a high impedance and the conversion accuracy is lowered.

[0013]

The A / D converter of the present invention comprises an analog input terminal, a digital output terminal, a D / A converter, a plurality of voltage comparison circuits and encoders to which inputs are applied via capacitive elements. Each of the plurality of voltage comparators has an input connected to an analog input terminal via a first switch circuit, and a D / A converter via a second switch circuit group including a plurality of switch circuits. The output of the plurality of voltage comparison circuits is input to the encoder, the output of the encoder is input to the D / A converter and is also connected to the digital output terminal.
Of the D / A converter and the sampled analog by sequentially closing a plurality of switch circuits that constitute the second switch circuit group after closing the switch circuit of 4 to sample the analog input applied to the analog input terminal. In a serial-parallel A / D converter that obtains a conversion result through a plurality of steps of comparing inputs, a predetermined output and sampling period of the D / A converter are provided immediately after sampling an analog input, and the D / A conversion is performed. In the first step of comparing the output of the converter with the sampled analog input, if the sampled analog input is lower than the predetermined output of the D / A converter, it is lower than the predetermined output of the D / A converter. Only the output of the D / A converter, or if the sampled analog input is higher than the predetermined output of the D / A converter. / A converter of high D / A converter than a predetermined output of the output only through the second switch circuit group is applied to the input of the voltage comparator circuit.

[0014]

The present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment according to the present invention. An analog input terminal (A _IN ), a digital output terminal (D _OUT ), a D / A converter, and three voltage comparison circuits ( C ₀ -C ₂₎ and provided with an encoder, the input switch circuit of the voltage comparator circuit (C ₀ ~C ₂₎ (SA0~SA
2) is connected to the analog input terminal (A _IN ) via a switch circuit (SB0 to SB2 and SC0 to SC).
2) is connected to the output of the D / A converter via the switch circuit group (SG0 to SG2) composed of 2), the output of the voltage comparison circuit (C _{0 to} C ₂ ) is input to the encoder, and the output of the encoder is 4 shows a 4-bit serial-parallel D / A converter that is input to the D / A converter and is connected to a digital output terminal (D _OUT ). The D / A converter in this embodiment is composed of a resistance element (R) connected between + V _REF and -V _REF and switches (S _{0 to} S ₃ ) controlled by the output of the encoder. The voltage comparison circuit (C
_{0 to} C ₂ ) are P channel type M as shown in FIG.
OS-FET (P ₁ ) and N-channel MOS-FET
(N ₁ ) and an N-channel type MOS-FET (N- _S connected to the input-output (OUT) of the inverter and having a gate to which the sampling signal (φ _S ) is applied.
₂ ) and the input signal to the output (OUT) of the inverter, and the inverted sampling signal is applied to the gate of P
It is composed of a channel type MOS-FET (P ₂ ) and a capacitive element (C ₁ ) connected between the input and input (IN) of the inverter. Further, as shown in FIG. 5B, a differential amplifier (DAMP) and an N-channel MOS-FET in which a sampling signal (φ _S ) is applied to the gates of the two inputs (− and +) of the differential amplifier. (N ₃ and N ₄ ) and a P-channel MO with the inverted sampling signal applied to the gate
It is connected to the bias voltage terminal (V _B ) through the S-FETs (P ₃ and P ₄ ) and the capacitive elements (C ₂ and C ₃ ).
A voltage comparison circuit configured by connecting to the input (IN) and GND via the may be used.

Next, the operation will be described with reference to FIGS. 1, 2 and 5. First, during the sampling period, the switch circuits (SA0 to SA2) are closed to close the analog input terminal (A
_The analog input (V _AIN ) input to ( _IN ) is applied to the inputs of the voltage comparison circuits (C _{0 to} C ₂ ). When the circuit shown in FIG. 4A is used as the voltage comparison circuit (C _{0 to} C ₂ ), the sampling signal (φ _S ) becomes high,
The inverted sampling signal becomes low and the N-channel type MOS-FET (N ₂ ) and the P-channel type MOS-FE are used.
T (P ₂ ) is turned on and the input and output (OU
T) is short-circuited, and the logical threshold voltage of the inverter (about 1
/ 2V _CC) is biased to the capacitive element (C ₁₎ to the charge proportional to the analog input _{(V AIN): (V AIN} -1/2
V _CC ) × C ₁ is stored. In addition, the voltage comparison circuit (C _{0 to} C
_When the circuit shown in FIG. 5B is used as ₂ ), the sampling signal (φ _S ) becomes high and the inverted sampling signal becomes low, so that the N-channel MOS-FET
(N ₃ and N ₄ ) and P-channel MOS-FET (P
₃ and P ₄ ) are turned on and the inputs (− and +) of the differential amplifier (DAMP) are biased to the bias voltage (V _B ),
A charge: (V _AIN -V _B ) × C ₂ proportional to the analog input (V _AIN ) is stored in the capacitive element (C ₂ ). Then, as the switch circuits (SA0 to SA2) are opened, the sampling signal (φ _S ) becomes low and the inverted sampling signal becomes high, so that the N-channel MOS-FET (N ₃
And N ₄ ) and P-channel type MOS-FETs (P ₃ and P ₄ ) are turned off, and the sampling is completed.

After the sampling is completed, the switch circuit (SB
Output of D / A converter with 1) closed: 1/2 {(+
V _REF ) − (− V _REF )} and a sampled analog input (V _AIN ) are newly provided with a proportional period (step 0), and in the subsequent step 1, the comparison result in step 0 is V _AIN <1/2. {+ V _REF )-(-
If V _REF )}, the switch circuit (SB1) and the switch circuit (SB0) are closed and the 2-bit precision D / A converter output is applied to the input of the voltage comparison circuit (C ₀ and C ₁ ) to obtain an analog signal. Compare with input. Here, if the D / A converter output is lower than the analog input, a high
When the converter output is higher than the analog input, a low is output from the voltage comparison circuit (C ₀ ) and encoded by the encoder to obtain a rough conversion result with 2-bit accuracy. In this case, the output of the switch circuit (SB2) is the input of the open and the voltage comparator circuit (C ₂₎ D / A converter is not applied, V _AIN <1/2 at step 0 {(+
Since it is known that V _REF ) − (− V _REF )}, the voltage comparison circuit (C ₂ ) is expected to output low, and the encoder compares the voltage comparison circuit (C ₂ ). If a row is input as a result, the encoded conversion result is correct. The comparison result in step 0 is V _AIN > 1
If it is / 2 {(+ V _REF )-(-V _REF )}, the switch circuit (SB2) is closed in addition to the switch circuit (SB1), and 2
Similarly, by applying the output of the D / A converter of bit accuracy to the input of the voltage comparison circuit (C ₁ and C ₂ ),
A conversion result with rough t-precision can be obtained. In this case, the switch circuit (SB0) is open and the output of the D / A converter is not applied to the input of the voltage comparison circuit (C ₀ ), but in step 0 V _AIN > 1/2 {(+ V _REF ) − (−
V _REF )), it is expected that a high voltage will be output from the voltage comparison circuit (C ₀ ), and high will be input to the encoder as the comparison result of the voltage comparison circuit (C ₀ ). If so, the encoded conversion result is correct.

Next, in step 2, switch circuits (SC0-SC0)
SC2) closes, and either S ₀ to S ₁ or S ₂ or S ₃ depending on the conversion result obtained in step 1 1
D / A converter output of 4bit accuracy closes the set of switches is applied to the input of a voltage comparator circuit (C ₀ ~C _2), the output of the voltage comparator circuit (C ₀ ~C ₂₎ is encoded by the encoder A 4-bit precision conversion result is obtained.

In a first embodiment according to the present invention, FIG.
When the voltage comparison circuit shown in (a) is used, step 1
In the capacitive element (C ₁₎ the inverter side of the voltage at the (v _a) is given by As described above (Equation 1). Here, for example, when V _AIN = 0 [V], in the first embodiment according to the present invention, a voltage higher than 1/2 {(+ V _REF ) − (− V _REF )} is applied to the input of the voltage comparison circuit. There is no such thing. When + V _REF = V _CC, −V _REF = 0 [V], a voltage higher than 1/2 V _CC is not applied to the input of the voltage comparison circuit, and therefore va is equal to or higher than the power supply voltage (V _CC ) according to (Equation 1). Since it does not become a P-channel MOS-FET
The drain (P-type diffusion layer) of (P ₂ ) is not forward-biased, and the charge accumulated in the capacitive element (C ₁ ) is not lost. When V _AIN = V _{CC, in} the first embodiment of the present invention, 1/2 {(+ V _REF )-(-V
_No voltage lower than _REF )} is applied to the input of the voltage comparison circuit. When + V _REF = V _CC and −V _REF = 0 [V], a voltage lower than 1/2 V _CC is not applied to the input of the voltage comparison circuit, and therefore, according to (Equation 1), v _a may be a negative voltage. Therefore, the drain (N-type diffusion layer) of the N-channel MOS-FET (N ₂ ) is not forward biased, and no charge is injected into the capacitive element (C ₁ ).
When the voltage comparison circuit shown in FIG. 5B is used, in step 1, the differential amplifier (DAM) in the capacitive element (C ₂ ) is used.
The potential (v _b ) on the P side is given by (Equation 2) as described above, and if the bias voltage (V _B ) is set to 1/2 V _CC , (Equation 2) becomes the same as (Equation 1). . Therefore, even when the voltage comparison circuit shown in FIG. 5B is used, as described above, the charge stored in the capacitive element (C ₂ ) is lost or the charge is injected into the capacitive element (C ₂ ). Never.

As described above, in the capacitive element of the voltage comparison circuit used in step 1, no charge is dissipated or injected during the period of step 1, and the analog input value stored in the capacitive element is not destroyed. As described in the first embodiment of the present invention, the voltage comparison circuit used in step 1 can be shared in step 2.

Furthermore, since there is no carrier injection from the drain of the MOS-FET to the substrate, there is no problem that the carriers injected into the substrate are absorbed by the connection point with high impedance and the conversion accuracy is lowered.

FIG. 3A is a circuit diagram showing a second embodiment according to the present invention, in which (2i + 1) voltage comparison circuits (C
_{0 to} C _2i ), the inputs of the voltage comparison circuit (C _{0 to} C _2i ) are connected to the analog input terminal (A _IN ) via the switch circuits (SA ₀ to SA _2i ) and the switch circuit (S
B0 to SB2i and SC0 to SC2i) are connected to the output of the D / A converter via the switch circuit group (SG0 to SG2i). Further, the voltage comparison circuit (C _{0 to} C _2i ) has a P-channel type MOS-FET (P ₁ ) and an N-channel type MOS-FE as shown in FIG.
P-channel MOS-FET consisting of T (N ₁ )
G _m of (P ₁ ) is an N-channel type MOS-FET (N ₁ )
And higher the set (e.g., 2 / 3V _CC) inverter than the logic threshold voltage supply voltage (V _CC) half value (1 / 2V _CC) of by setting larger than g _m of the input of the inverter To the output (OUT) and the sampling signal (φ _S ) is applied to the gate of the N-channel MO
Input to input of the S-FET (N ₂ ) and the inverter (I
It is composed of a capacitive element (C ₁ ) connected between N). Further, as shown in FIG. 3B, a differential amplifier (DAM
P) and the two inputs (-and +) of the differential amplifier to the gate, and the sampling signal (φ _S ) is applied to the N-channel MO.
Power supply voltage (V _CC ) via S-FET (N ₂ and N ₄ ).
Is connected to a bias voltage terminal (V _B ) set higher than half the value (1/2 V _CC ) (for example, 2/3 V _CC ) and input (IN) through the capacitive elements (C ₂ and C ₃ ). )
And a voltage comparison circuit configured to be connected to GND. The structure of other parts is the same as the first embodiment of the present invention described above.
3 is the same as the embodiment of FIG.
Also in (a), the digital output terminal (D _OUT ) and the encoder are omitted.

Next, the operation will be described with reference to FIGS. 3 and 4. First, during the sampling period, the switch circuits (SA0 to SA2i) are closed and the analog input (V _AIN ) input to the analog input terminal (A _IN ) is applied to the input of the voltage comparison circuit (C _{0 to} C _2i ). When the circuit shown in FIG. 4A is used as the voltage comparison circuit (C _{0 to} C _2i ), the sampling signal (φ _S ) becomes high and the N-channel MOS-FET (N ₂ ) turns on. The input and output of the inverter are short-circuited, biased to the logical threshold voltage (2 / 3V _CC ) of the inverter, and the charge proportional to the analog input (V _AIN ) is applied to the capacitive element (C ₁ ):
(V _AIN −2 / 3V _CC ) × C ₁ is stored. When the circuit shown in FIG. 4B is used as the voltage comparison circuit (C _{0 to} C _2i ), the sampling signal (φ _S ) becomes high and the N-channel type MOS-FET (N ₃ and N ₄ ) becomes. Is turned on, the inputs (-and +) of the differential amplifier (DAMP) are biased to the bias voltage (V _B = 2 / 3V _CC ), and the capacitive element (C ₂ ) is proportional to the analog input (V _AIN ). The electric charge (V _AIN −V _B ) × C2 is stored. Then, as the switch circuits (SA0 to SA2i) are opened, the sampling signal (φ _S ) becomes low, and the N-channel MOS-FET
(N ₃ and N ₄ ) are turned off and the sampling is completed.

After the sampling is completed, the switch circuit (SB
i) is closed, for example, the output of the D / A converter: 1/2 {(+ V
_REF ) − (− V _REF )} and a sampled analog input (V _AIN ) are provided in a period (step 0). In the subsequent step 1, the comparison result in step 0 is V _AIN <1/2 {(+ V _REF )-(-V _REF )}, the switch circuit (SBi) and the switch circuit (SB
0 to SBi + 1) is closed and log2 (2i + 2) bit
The accuracy of the D / A converter output is compared with the voltage comparison circuit (C ₀ ~
C _{i + 1} ) applied to the input to compare with the analog input. Here, if the D / A converter output is lower than the analog input, a high voltage is output, and if the D / A converter output is higher than the analog input, a low voltage is detected by the voltage comparison circuit (C _{0 to} C _{i + 1} ).
Output from and encoded by the encoder log2
A rough conversion result with (2i + 2) bit precision can be obtained. In this case, the switch circuit (SBi + 2~SB2i) is the input of which open voltage comparator _{(C i + 2 ~C 2i)} D / A
The output of the converter is not applied, but V
_{Since it is known that AIN} <1/2 {(+ V _REF ) − (− V _REF )}, it is expected that the voltage comparator circuit (C _{i + 2 to} C _2i ) outputs a low. If the row is input to the encoder as the comparison result of the voltage comparison circuits (C _{i + 2 to} C _2i ), the encoded conversion result is correct. The comparison result in step 0 is V _AIN > 1/2 {(+ V _REF ).
If-(-V _REF )}, the switch circuit (SBi) and other g
Close the switch circuits (SBi-1 to SB2i) and log
Similarly, a rough conversion result with log2 (2i + 2) bit precision is obtained by applying the output of the D / A converter with 2 (2i + 2) bit precision to the input of the voltage comparison circuit (C _{i-1 to} C ₂ :). . In this case, the switch circuit (SB0-S
Bi-2) is open and the voltage comparison circuit (C _{0 to} C _i-2 ).
The output of the D / A converter is not applied to the input of
In step 0, V _AIN > 1/2 {(+ V _REF ) − (− V
Because it has proven _REF)}, a voltage comparator circuit (C ₀ ~C _i-2) is expected to high is output from the voltage comparator circuit to the encoder (C ₀ ~C _i-2 If you enter high as the result of the comparison, the encoded result is correct. Next, in steps, switch circuits (SC0 to SC2
When i) is closed, the output of the D / A converter with 2log2 (2i + 2) bit precision is applied to the input of the voltage comparison circuit (C _{0 to} C _2i ) according to the conversion result obtained in step 1, and the voltage comparison circuit (C ₀ The output of ~ C _2i ) is encoded by the encoder to obtain a conversion result with 2log (2i + 2) bit precision.

In a second embodiment according to the present invention, FIG.
When the voltage comparison circuit shown in (a) is used, the input (IN) side of the capacitive element (C ₁ ) for the sampling period is the analog input (V _AIN ) and the voltage on the inverter side is the logical threshold voltage (2) of the inverter. / 3 V _CC ), and when the voltage on the input (IN) side becomes the output voltage (V _{D / A} ) of the predetermined D / A converter in the subsequent step 1, the voltage (v _i ) on the inverter side becomes It is given by the following equation (3).

[0026]

Here, for example, when V _AIN = V _CC , in the second embodiment of the present invention, 1/2 {(+ V _REF )-(-V
_REF ))-α (α is a voltage corresponding to 1 [LSB] in log2 (2i + 2) bit precision) is not applied to the input of the voltage comparison circuit. + V _REF =
When V _CC , -V _REF = 0 [V], a voltage lower than (1/2 V _CC -α) is not applied to the input of the voltage comparison circuit, so that from the equation (3), v _c > 1/6 V _CC- α becomes α <1 /
If it is set to be 6 V _CC , v _c will not become a negative voltage, so that the drain (N type diffusion layer) of the N channel type MOS-FET (N ₂ ) will not be forward biased. , No charge is injected into the capacitive element (C ₁ ). Further, for example, when V _AIN = 0 [V], v _c becomes equal to or higher than the power supply voltage (V _CC ) but the P-channel type MOS-FET is not connected to the inverter side of the capacitive element (C ₁ ) and the forward direction. Since there is no biased P-type diffusion layer, the capacitive element (C
There is no loss of charge stored in ₁ ). See also FIG.
When the voltage comparison circuit shown in (b) is used, V _B = 2 /
If it is 3 V _CC , the potential on the differential amplifier (DAMP) side of the capacitive element (C ₂ ) in step 1 is equal to v _c shown in (Equation 3), so that the electric charge is injected into the capacitive element (C ₂ ). And the electric charge stored in the capacitive element (C ₂ ) is not lost.

As described above, in the capacitive element of the voltage comparison circuit used in step 1, no charge is dissipated or injected during the period of step 1, and the analog value stored in the capacitive element is not destroyed. Similar to the first embodiment according to the present invention, the voltage comparison circuit used in step 1 can be shared in step 2. In addition, since carriers are not injected from the drain of the MOS-FET into the substrate, the carriers injected into the substrate are not absorbed by the connection point with high impedance and the conversion accuracy is not lowered. Further, in the second embodiment according to the present invention, when the comparison result in the voltage comparison circuit (C _i ) is high in step 0, the voltage comparison circuit (C
_{0 to} C _i ) In addition to the voltage comparison circuit (C _{i + 1} ), the analog input is compared with the output of the D / A converter, and if the comparison result in the voltage comparison circuit (C _i ) is low in step 0. Step 1
In addition to the voltage comparison circuit (C _{i to} C _2i ), the voltage comparison circuit (C _i
i-1 ) also compares the analog input and the output of the D / A converter, the comparison result in step 0 is log2 (2
Even if the error in i + 2) bit is less than 1 [LSB], the correct conversion result can be obtained in step 1. In other words, when step 0 is completed in a short time, the comparison result includes an error, but a correct conversion result is obtained in step 1, so that the period of step 0 can be shortened and the speed can be increased.

[0029]

As described above, according to the present invention, since the voltage comparison circuit used in step 1 can be shared in step 2, the voltage comparison circuit is composed of half the number of conventional serial-parallel type D / A converters. This has the effect of enabling reduction of the configuration area and power consumption.

Further, since the carriers are not injected into the substrate, the carriers injected into the substrate are not absorbed by the connection points having high impedance and the conversion accuracy is not lowered.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment according to the present invention.

FIG. 2 is a timing chart of FIG.

FIG. 3 is a circuit diagram and a timing chart showing a second embodiment according to the present invention.

FIG. 4 is a circuit diagram showing a voltage comparison circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a voltage comparison circuit.

FIG. 6 is a circuit diagram showing a conventional A / D converter.

FIG. 7 is a timing chart of FIG.

Claims (4)

[Claims] 1. An analog input terminal, a digital output terminal, a D / A converter, a plurality of voltage comparison circuits to which inputs are applied via capacitive elements, and an encoder. One switch circuit is connected to the analog input terminal, and a second switch circuit group composed of a plurality of switch circuits is connected to the output of the D / A converter, and the plurality of voltage comparison circuits are connected. The output of the circuit is input to the encoder, the output of the encoder is input to the D / A converter and connected to the digital output terminal, and the first switch circuit is closed to close the analog input terminal. After sampling the analog input applied to the D / A circuit, the plurality of switch circuits forming the second switch circuit group are sequentially closed. In a serial-parallel A / D converter that obtains a conversion result through a plurality of steps of comparing an output of a converter and a sampled analog input, a predetermined output of the D / A converter is provided immediately after sampling the analog input. In the first step of providing a period for comparing the sampled analog input and comparing the output of the D / A converter with the sampled analog input, the sampled analog input is If the output is lower than the output, only the output of the D / A converter lower than the predetermined output of the D / A converter,
When the sampled analog input is higher than the predetermined output of the D / A converter, only the output of the D / A converter higher than the predetermined output of the D / A converter is output by the second An A / D converter which is applied to an input of the voltage comparison circuit via a switch circuit group. 2. The D / A when the sampled analog input is lower than a predetermined output of the D / A converter.
Sampling not only the output of the D / A converter which is lower than the predetermined output of the A converter, but also the output of the D / A converter which is higher than the predetermined output of the D / A converter by a desired value. If the analog input is higher than the predetermined output of the D / A converter, not only the output of the D / A converter higher than the predetermined output of the D / A converter but also the D / A conversion The A / A converter according to claim 1, wherein an output of the D / A converter that is lower than a predetermined output of the voltage converter by a desired value is applied to the voltage comparison circuit via the switch circuit group.
D converter. 3. The voltage comparison circuit to which the input is applied via a capacitive element comprises an inverter and a capacitive element, the input of which is applied to the input of the inverter through the capacitive element, and the output of which is the output of the inverter. In the voltage comparison circuit taken out from the above, the logic threshold voltage of the inverter is set higher than half the value of the power supply voltage, and the one conductivity type connected between the input and the output of the inverter and having the sampling signal applied to the gate. Type first MOS
A signal which is composed of a FET or which sets the logical threshold voltage of the inverter lower than half the value of the power supply voltage and which is connected between the input and output of the inverter and has the gate inverted from the sampling signal. And a second MOS of opposite conductivity type to the first MOS-FET
3. A FET according to claim 1 or 2, characterized in that
A / D converter described in 1. 4. The voltage comparison circuit, to which the input is applied via a capacitive element, comprises a differential amplifier, a bias voltage terminal, first and second capacitive elements, and the differential amplifier has a first input and the first and second capacitive elements. An input is applied via a first capacitive element, a second input of the differential amplifier is connected to a power supply terminal or the bias voltage terminal via the second capacitive element, and an output is applied to the differential amplifier. In the voltage comparison circuit extracted from the output of the amplifier, the voltage at the bias voltage terminal is set higher than half the value of the power supply voltage, and the voltage between the first and second inputs of the differential amplifier and the bias voltage terminal is set. It is composed of first and second MOS-FETs of one conductivity type that are connected and have a sampling signal applied to their gates,
Alternatively, the voltage of the bias voltage terminal is set lower than half the value of the power supply voltage, and the first voltage of the differential amplifier is set.
And a third conductivity type opposite to the first and second MOS-FETs connected between the second input and the bias voltage terminal and having a gate applied with a signal obtained by inverting the sampling signal.
And the fourth MOS-FET. 4. The A / D converter according to claim 1, wherein