JPH05298900A - Read/write memory - Google Patents

Abstract

PURPOSE: To provide an integrated circuit having a memory which is provided with a parallel test data comparator. CONSTITUTION: The parallel test data comparator 32 is provided with an NOR- state function part, having a parallel transistor providing a gate to which inputs from respective internal data lines are supplied and a HAND-state function part having the parallel transistor, providing the gate to which the inputs from the respective internal data lines are supplied. The output nodes of the respective function parts are respectively controlled by the signal of a test enable circuit 30 and also respectively biased by a single transistor which can be beated by one of the parallel transistors When the whole internal data lines are in a same logical level, the outputs of NOR and HAND are in the same logical level. At the time of difference, they are in the different logical levels. An exclusive OR-satate function part is used, in order to generate a success or failure signal in response to the NOR and HAND output nodes.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates generally to integrated circuits, and more particularly to memory integrated circuits and special test modes within the circuits. The invention also relates to a technique for writing data into an integrated circuit memory.

[0002]

2. Description of the Prior Art In modern highly integrated memories, such as random access memories having, for example, 2 ²⁰ bits (1 megabit) or more, to test the functionality and timing of every bit in the memory. The time and equipment required make up a significant portion of the manufacturing cost. Therefore, as the time required for such testing increases, so does the manufacturing cost. Similarly, if the time required to test the memory can be reduced, the manufacturing cost of the memory is also reduced. Since memory devices are typically manufactured in large quantities, even a few seconds of savings per device can result in significant cost savings and avoidance of capital investment. This is because the number of memory devices manufactured is large.

Random access memory (RAM) is particularly one that has significant test costs. Because it is necessary to both write data to and read data from each of the bits in the memory, and the RAM often suffers from pattern sensitivity. Is. Pattern sensitivity impairments occur because the ability of a bit to maintain the state of its stored data may depend on the state of the data stored in the bit physically adjacent to the particular bit under test. To do. Not only does this make the test time for a RAM linearly dependent on its density or density (ie, the number of bits available for storage), but for some pattern sensitivity tests, It shall depend on the square of the number (or 3/2 index). Clearly, as the density or density of RAM devices increases (typically four times per generation), the time required to test each bit of each device in mass production increases at a rapid rate. .

It should be noted that many other integrated circuit devices other than the memory chip itself use memory on-chip. Examples of such integrated circuits include many modern microprocessors and microcomputers, as well as custom devices such as gate arrays with embedded memory therein. Similar cost issues are encountered when manufacturing these products, which involves the time and equipment required to test the memory portion.

A solution that has been used in the past to reduce the time and equipment required for testing semiconductor memories, such as RAM, is to use a special "test" mode, In that case, the memory enters a special operation that differs from its normal operation. In such a test mode, memory operation may be significantly different from normal operation. This is because the internal test operation can be performed without imposing the constraint condition of the normal operation.

One example of a special test mode is an internal "parallel" or multi-bit test mode. The conventional parallel test mode allows access to more than one memory location in a single cycle, and common data is written to and read from multiple locations simultaneously. In the case of a memory with multiple input / output terminals, multiple bits are accessed in such a mode for each of the input / output terminals to achieve parallel test operation. This parallel test mode is, of course, not usable in normal operation. This is because the user must be able to access each bit independently in order to use the full capacity of the memory. Such parallel test operation is preferably
It is implemented in such a way that the bits accessed in each cycle are physically separated from each other, so there is little probability of pattern sensitivity interference between bits accessed simultaneously. For a description of such parallel test operations, see McAdams et a.
l. Written "1 megabit CMO with test design function"
S dynamic RAM (A 1-Mbit CMOS
Dynamic RAM With Design-F
or-Test Functions) ", IEEE
Journal of Solid-State Circuits,
Vol. SC-21, No. 5 (10 October 1986)
Mon.), pages 635-642.

As described in the above-referenced document, conventional parallel test operations can be implemented in one of two ways. The first of these methods simply compares the data states read from each of the plurality of simultaneously accessed bits to each other. If all of the simultaneously accessed bits have the same data, then the test operation is a pass. The second method for parallel testing, commonly referred to as the "predictive data parallel test", compares the data provided by the accessed data with each other and against the contents of the on-chip registers to identify all accessed bits as the same. Not only that the data has been read, but that the read data state is the correct data state.

In any case, an internal comparison of a plurality of sensed data states must be performed on-chip, from which the results are delivered externally. McA
dams et al. In the above document, a multistage comparator is provided as described with reference to FIG.
It receives internal data lines DL0-DL7 and performs comparisons between them (and, if desired, comparison with scheduled data ED). However, in this example,
Each internal data line is connected to both the input end of the NAND function part and the input end of the OR function part. Therefore, McAda
ms et al. The loading of the internal data lines provided by the parallel comparators described in the literature is significant and slows the performance of the internal read path during normal operation. Furthermore, McAdam
s et al. Layout area required for literature comparators (one of which is an exclusive OR 11
Including individual logic function parts) is considered to be significant.

US Pat. Nos. 4,654,849 and 4,860,259 describe other parallel testing methods. The multi-bit comparator disclosed in these references (see FIGS. 1 and 8 of US Pat. No. 4,654,849;
See U.S. Pat. No. 4,860,259, FIGS. 4A and 7B), respectively, in McAdams et al. Configured as static logic gates, and as such, are therefore believed to suffer from similar increased problems in internal data bus loading, and consequently poor performance and significant performance in normal operation. There are also layout and chip area issues.

Another known technique for performing internal parallel comparisons in test mode is Shimada et al. Author "46 nanosecond 1-megabit CMOS SRAM (A 4
6-ns 1-Mbit CMOS SRAM) ", I
EEE Journal of Solid-State Circuits, Vol. 23, No. 1, (1988 2
Mon), pp. 53-58. Parallel testing is performed in this device by simultaneous access of four array blocks, as described with respect to FIG. 5 of this document. The comparison of the data retrieved from the 4 accessed bits is performed by the arbiter buffer,
The buffer is BUS and BUS in a wired AND manner
Drive the _ line. As noted on page 55 of that document,
The P-channel pull-up transistor in the arbiter buffer is small, so if any of the four selected cells fail (eg, have a "0" instead of a "1"), then BUS and BUS Both _ lines are at a low logic level. In such a case, the operation of the NAND gate provides a "1" input to both the NOR driving the pullup and pulldown transistors of the output buffer, forcing a high impedance state at the output of the device.

However, as is apparent from the configuration, it is clear that the arbiter buffer is connected in series with the data path between the sense amplifier and the data output terminal in both the normal mode and the parallel test mode. Therefore, the propagation delay required by the arbiter buffer is present during normal operating mode as well, and thus the access time penalty is forced to be taken to perform the parallel test comparison. This penalty is exacerbated by the configuration of the arbiter buffer as follows.
That is, the P-channel pull-up transistor is small enough so that a single N-channel pull-down transistor (in the example of a test failure resulting from reading a "0" instead of a "1") is the other three. May pull down the BUS or BUS_ line that is pulled high by the P-channel transistor of. The small size for this pull-up device, of course, creates the time for the BUS or BUS_ line to slowly transition from a low logic level to a high logic level for a read operation. Moreover, this slow transition time is exacerbated when the parallel test configuration transitions from every fourth test to every eighth or wider parallel test operation. This is because a single N-channel transistor must be able to pull down the node that is being pulled up by 15 P-channel pull-up transistors in the case of every 7 or 16 tests. Is. Therefore, Shimada et al. The method described in the above document diminishes its usefulness in the case of wider parallel test operations. Of course, as memory grows larger and larger, it becomes desirable to test a larger number of bits in parallel.

Further, US Patent Application No. 552,5 filed on Jul. 13, 1990 and assigned to the present applicant.
No. 67 describes a static random access memory (SRAM) including a parallel test mode, the result of the parallel test is sent to the data output terminal, and the high impedance state is parallel compared to a specific input / output. Indicates that it has failed. SRA described in the above application
The M device uses a series of comparators to compare multiple internal data lines in parallel test mode. As described with respect to FIG. 3 of the above-referenced US patent application Ser. No. 552,567, pairs of data words are compared bit by bit by a series of comparators, the result of which is the final signal generated and output driver. Is supplied to.

Also, in the field of integrated circuit memory, the speed at which memory access is performed is, of course, a critical parameter. The importance of memory performance is due to the recent significant increase in the speed at which computer systems operate (eg, 33 MHz for currently readily available personal computers).
Has made it even more important. Such high speed computer systems currently have as their main memory, for example, a specified cycle time and
High-speed static random access memory (SRA) such as SRAM with read access time of less than 0 nanosecond
M) is used.

Read access time is, of course, an important parameter in such memories, but the ability to accurately perform a write operation to selected memory cells in the SRAM device within the specified cycle time is also adequate. It is essential for system operation. Receipt and internal communication or delivery of input data are important factors in the design of such memories. Moreover, the timing of the various control signals in the memory is also very important. This is because the input data must be given to the correct memory cell.

Most conventional integrated circuits generate internal write control signals that must be activated at appropriate times in a memory cycle relative to other internal operations.
For example, if the internal write signal is activated faster than the address decode operation, the input data may be written to the wrong memory location (ie, the memory location accessed in the previous cycle). Therefore, the conventional memory configuration is
For example, the generation of the leading edge of the write signal is delayed by a gate delay to ensure that it is not activated until sufficient time has elapsed to perform the address decode operation.

Furthermore, the end of the write operation must be tightly controlled so that it occurs before the operation of the next cycle, and if the internal write signal is ended too late,
Data is in the wrong position (ie, the position accessed in the next cycle) after the decode operation of the next address.
Will be written in. For example, in a conventional SRAM, the timing of the ATD signal and the internal address radio are usually selected by balancing the read and write cycle timings. In particular, during a read cycle, it is desirable for the internal address signal to propagate as quickly as possible to minimize the read access time. However, the rapid propagation of the address signal can cause a new address to reach part of the chip before the signal that terminates the write operation, which is especially the case for long memory chips. That means that the writing of the previous cycle will affect the new address. Therefore, in the memory design, the propagation of the internal address signal may be slowed from the maximum speed (and thus the read performance may be delayed) so that a write error does not occur.

Thus, the combination described above requires that the leading edge of the write signal be delayed from the beginning of the address value, but the trailing edge of the write signal precedes its next transition.
This timing relationship is conventionally achieved by gate delay. In modern high speed, highly integrated memories, high speeds and the long distances these internal signals must travel create internal race conditions between signals with their internal timing controlled by the designed gate delay. Increasing the risk. The possibility of this race condition is
Exacerbated by receiving address inputs on different parts of a large chip, it is often necessary to delay the write sequence to avoid such race conditions.

The difficulty of accurately controlling internal write operations using gate delays is further exacerbated in SRAMs whose cycles are initiated by address transition detection. Because a new cycle can be started at any time, and address transitions can occur at various address input terminals in an asynchronous manner, resulting in long-term instability. Because.

[0019]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a memory having a parallel test mode in which loading on internal data bus lines is minimal. Another object of the invention is to provide such a memory having a parallel test multi-bit data comparator which is outside the internal data path in normal operation. Yet another object of the present invention is to provide such a memory with minimal propagation delay in parallel test multi-bit comparisons. Yet another object of the present invention is to provide such a memory that can be efficiently laid out in a relatively small chip area.

It is an object of the present invention to provide control of internal write operations without relying on relative gate delays. Another object of the invention is to provide such control without requiring additional cycle time. Yet another object of the invention is to provide such write control in a relatively simple manner. Yet another object of the invention is to provide such write control in a memory that is exposed to unstable inputs such as address values. Yet another object of the present invention is to optimize timing internal address signals and address transition detection signals for read operations without the risk of write errors, while improving read access time performance. It is possible.

[0021]

The present invention can be implemented in a read / write memory, such as a static random access memory (SRAM) having a parallel test mode. In a normal read operation, a comparator is coupled in parallel with the data path to each of the internal data lines in the chip. The comparator receives each of the internal data lines at the gate of the pull-up transistor in the first stage and at the gate of the pull-down transistor in the second stage. The first stage further has a pull-down transistor controlled by the test enable signal, and the second stage has a pull-up transistor controlled by the test enable signal. A common drain node in the first and second stages provides a comparison result, and each of the transistors receiving an internal data line at its gate powers a control pull-down and pull-up transistor in each of the first and second stages. Dimensioned to exceed. Therefore, the logical coupling of the common drain nodes provides an indication of whether the comparison succeeded or failed, while reducing parasitic loading on the internal data lines.

The present invention can be incorporated into integrated circuit memories, such as static random access memory (SRAM), in which differential bit lines and data lines are balanced. The write driver is interlocked with the balancing signal so that no writing occurs during the balancing period. Since the balancing occurs during a time period when the address input is unstable, this interlock ensures that the write operation is not enabled during the address transition period and is accurate and of high performance. Secure the write operation.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An example of an integrated circuit incorporating the preferred embodiment of the present invention will be described with reference to FIG. In this example, the memory 1 is a static random access memory (S
RAM) and having its memory cells in a plurality of blocks 10, which blocks are shown in FIG. 1 according to one example of their physical location in such a memory. The present invention is also applicable to other types of integrated circuits that use elongated data conductors, such integrated circuits including microprocessors, logic devices, and read-only memories, FIFOs, It also includes other types of memory, including DRAM and the like.

As in the prior art, the memory cells in memory 1 are arranged in rows and columns and are selected according to the address signals received at address terminals A _{0 to} A _n . The address terminals A _{0 to} A _n are connected to an address buffer 28, which buffers the received address signal and delivers a part of the address signal on the bus ROW to the row decoders 24a, 24b. The rest is on the bus COL and the column decoders 26a, 26b
To send. Row decoders 24a, 24b select a row of memory cells by enabling selected word lines in a conventional manner, and are therefore preferably located along the sides of memory array block 10. In this example, column decoders 26a, 26b select eight memory cells in the selected row to be sensed by sense amplifier 13 according to the column portion of the address.

In the memory 1 according to this example, the memory cells are grouped into 16 array blocks 10 _{0 to} 10 ₁₅ . Partitioning this memory into 16 array blocks 10 is particularly useful in low power memories such as those used in portable computers. This is because only the block 10 in which the selected memory cell is located needs to be enabled during the cycle. The block selection is according to one of the row address bits (representing the upper or lower half) and four of the column address bits (representing one of the 16 array blocks 10 to be selected). It is possible to carry out. Further reductions in activation power are provided by Array Block 1 as described in commonly assigned US patent application Ser. No. 588,609 filed September 26, 1990.
This can be achieved by incorporating a latched row line repeater between zeros.

As in most modern SRAMs and DRAMs, memory 1 has a node (eg, bit line) at a particular point in the memory cycle.
It involves a certain amount of dynamic motion, such as precharging and balancing. The start of the cycle in the SRAM 1 is generated by the address transition detection performed by the address transition detection (ATD) circuit 25. ATD circuit 2
5 is connected to each of the address inputs A _{0 to} A _n , preferably in front of the address buffer 28 (as shown), and any one or more of the address inputs A _{0 to} A _n. In the above, a pulse is generated on the line ATD in response to detecting the transition, and such a pulse is useful for controlling the internal operation of the memory 1 in the conventional manner and in the manner described below.

Other internal operating functions are controlled by the timing and control circuit 29, which receives the signal from the ATD circuit 25 via line ATD, which
It also receives certain external control signals, such as a chip enable signal at terminal CE and a read / write select signal at terminal R / W_. Timing and control circuit 29 generates various control signals based on these inputs for controlling various functions in memory 1 in a conventional manner. The control signal is shown in FIG. 1 for simplicity of explanation.
Not shown in. Each of array blocks 10 ₀ through 10 _15, as shown in FIG. 1, it is associated with a corresponding group of sense / write circuits 13 ₀ to 13 _15. In this example, eight individual senses, one for each of the eight bits to be delivered via the internal read data bus 22 from the selected one of the array blocks 10 _{0 to} 10 _15. / Write circuit is the detection / write circuit 1 of each group
It is provided within 3 _{0 to} 13 ₁₅ . Each of the sense / write circuits 13 includes both sense amplifiers and write drivers, as described in more detail below. Each of the plurality of groups of data drivers 15 receives a data signal therefrom and thereby drives the read data bus 22 with a corresponding group of sense amplifiers 13 ₀ -1.
3 ₁₅ and a separate data driver 15 is associated with a separate sense / write circuit 13 in each group and one data driver 15 is associated with the read data bus 2
Drive each line in 2. It is desirable for the data driver 15 to have a high impedance mode to avoid bus contention and enable precharging.

In this embodiment, the memory array is
Further, the array block 1 is divided into half parts.
0 _{0 to} 10 ₇ make up one half of the array and array blocks 10 _{8 to} 10 ₁₅ make up half of the other array. The read data bus 22 runs along the length of one half of these arrays, and FIG.
It is located between them as shown in. Each individual data conductor in the read data bus 22 is connected to a corresponding data driver in each of the 16 data driver groups 15 of the 16 array blocks 10 _{0 to} 10 ₁₅ . In the case of a read / write memory, such as memory 1, an input data bus 38 is also connected to each of the sense / write circuits 13 for delivering input data to be written to the selected memory cells in a conventional manner. Has been done. On the other hand, the input data can be communicated or delivered along the read data bus 22 in a time multiplexed manner, as is conventionally used in some memory configurations.

For fast read access times, it may be desirable to have one dummy data conductor in read data bus 22 associated with each of the data conductors. As will be described below, each dummy data conductor is driven to a relatively complementary state with its associated data conductor, and charge splitting between the two precharges the data conductors on the read data bus 22. Is possible.

The memory 1 in this embodiment has a single input / output terminal DQ where data is provided in read operations or data is received in write operations. Therefore, the input buffer 23 and the output buffer 25 are connected to the terminal DQ, and controlled by the timing and control circuit 29 in a conventional manner according to whether the read operation or the write operation is selected. The input buffer 28 is of a construction known in the art for receiving input data and delivering it. Output buffer 25 is a tri-state buffer having a conventional configuration, or, preferably, in the U.S. patent application (Attorney Docket No. 91-C-110) assigned to the present applicant and filed concurrently therewith. It can be of the configuration as described.

As will be explained below, each access of the memory 1 according to this embodiment of the present invention will cause the eight memory cells in the selected array block 10 to be respectively input data bus for write and read operations. 38 or read data bus 22 in communication. Since the memory 1 has a by-one structure, that is, one by one,
An O select circuit 20 is connected to both the input data bus 38 and the read data bus 22 and which of the lines on the input data bus 38 is in communication with the input buffer 23 during a write operation or the read operation. , Bus C which represents which of the lines on read data bus 22 is in communication with output buffer 25.
Receive part of the column address on OL '. The I / O selection circuit 20 also receives control signals from the test enable circuit 30 via the TC line, as described below.

The memory 1 further comprises a test enable circuit 30 for controlling entry into and exit from a special test mode, for example an internal parallel test. In this embodiment of the memory 1, the test enable circuit 30 is assigned to the applicant 19
US Patent Application No. 56, filed Aug. 17, 1990
It is constructed as described in No. 9,968.
As such, in this embodiment, the test enable circuit 30 receives a subset of m inputs from the address terminals A _{0 to} A _n that determine whether to enter the test mode, and the line TC. Signal (active low) through to enable parallel test mode. For example, U.S. Patent Application No. 569,
No. 968, it is possible to act as a clock signal when one of the m address inputs is in an overvoltage or undervoltage condition and the other of the m address inputs. Provides a code sequence to the test enable circuit 30 on each pulse of the clock signal, the code sequence indicating whether or not to enter a special test mode, and if multi-test mode is enabled. Indicates which of the test modes is selected. Of course, other conventional circuits and methods for entering the test mode can be used in the memory 1, including preparatory test mode terminals, detection of overvoltage conditions on the clock terminals, and the like. ..

Line T from test enable circuit 30
C is sent to the I / O selection circuit 20 and controls its operation. In particular, during the parallel test mode, it is desirable to write the same data state from a single terminal DQ to all eight internally selected locations in one cycle. As such, the test enable circuit 30 provides the I / O select circuit 20 with the line TC so that all eight lines on the input data bus 38 are driven by the input buffer 23 in a parallel test mode write operation.
It is possible to control

Line T from test enable circuit 30
C is further coupled to the test data comparator 32 according to this embodiment of the invention, enabling it as described below. The test data comparator 32 is
In addition, a data line is received from each of the data conductors of read data bus 22 and above which data driver 15
Drives the states of eight selected memory cells in a read operation. The location of test data comparator 32 shown in FIG. 1 does not represent its physical location in memory 1. Because, in order to reduce the loading effect in normal operation, the data bus 2 connected to it
This is because it is desirable that the length of 2 be as short as possible.

In this embodiment of the invention, test mode comparator 32 compares the data states of all eight lines of data bus 22 and produces a signal on line CMPR representing the result of the comparison. In this embodiment, a low level on line CMPR during the test mode indicates that all eight lines of data bus 22 have the same data state (“pass” condition). , And a high level on line CMPR during the test mode indicates that different ones of the lines of data bus 22 have different data states (“fail” conditions). The line CMPR can be provided at an external terminal of the memory 1, for example when the memory 1 is in wafer form. On the other hand, the line CMPR can be used to communicate the comparison result, for example to control the state of another terminal, such as the terminal DQ, and such a configuration can be used in a packaged form of the memory 1 It is suitable for performing parallel test of. This is because the number of external terminals for the memory integrated circuit is minimized. U.S. patent application Ser. No. 552,567, assigned to the applicant of the present application and filed July 13, 1990, sets an output terminal such as terminal DQ high to indicate that a parallel test read has failed. The configuration for setting the impedance state is described.
Other conventional techniques for transmitting the results of parallel test comparisons can be used in conjunction with the test data comparator 32 under the control of the line CMPR.

The structure and operation of the test data comparator 32 according to the preferred embodiment of the present invention will now be described in detail with reference to FIG. The test data comparator 32 has an 8-bit NOR function unit 35 and an 8-bit NAND function unit 37, which compare eight lines of the data bus 22 and supply them to the nodes N2 and N3, respectively. To do. As will be apparent from the following description, N according to the present invention
The OR function 35 and NAND function 37 configurations provide a minimal load on the read data bus 22 and can be configured in a relatively small chip area.

NOR function 35 has a P-channel pull-up transistor 34, its source is biased to V _cc , its drain is connected to node N2, and its gate is controlled by line TC. To be done. N-channel pull-down transistor 31 has its drain connected to node N2, its source biased to ground, and its gate connected to line TC.
Connected to. Therefore, if parallel test mode is not enabled (line TC high), transistor 31
Is on, transistor 34 is off, and node N2 is pulled low. In the parallel test mode (line TC low), transistor 31 is off and transistor 34 allows transistor 34 to pull node N2 high.

NOR function 35 further includes eight N-channel transistors 36 _{0 to} 36 ₇ , each of which has its drain connected to node N2 and its source biased to ground. There is. The gates of N-channel transistors 36 _{0 to} 36 ₇ are connected to individual lines 22 _{0 to} 22 _{7 of} read data bus 22, respectively. In this embodiment of the invention, each of the transistors 36 has a relatively strong drive relative to that of the transistor 34, so that any one of the transistors 36 has more power than the transistor 34, And it is desirable to be able to pull node N2 low when both are on. For example, the W / L of transistor 34 can be on the order of 4, while the W / L of each transistor 36.
L can be on the order of 6 or more.

The NAND function section 37 is configured in a manner relatively opposite to the NOR function section 35. N-channel transistor 42 has its source biased to ground,
Its drain is connected to node N3, and its gate is coupled via inverter 33 to line TC. The P-channel transistor 39 has its source at V
Biased to _cc , its drain is connected to node N3, and its gate is coupled to line TC via inverter 33. Thus, when parallel test mode is not enabled (line TC high), transistor 42 is off and transistor 39 is on, driving node N3 high. In the parallel test mode, transistor 42 is on and transistor 39 is off, allowing transistor 42 to pull node N3 low.

The NAND function section 37 further has eight P-channel transistors 40 _{0 to} 40 ₇ ,
Each of them has its source biased to V _cc , its drain connected to node N3, and its gate connected to a separate data line 22 _{0 to} 22 ₇ on read data bus 22, respectively. is doing. As with the NOR function unit 35, the drive capability of each of the transistors 40 in the NAND function unit 37 is preferably
Even larger than that of transistor 42, and thus when both transistors 40 and 42 are on, node N3 is pulled high by transistor 40. For example, the W / L of transistor 42 can be on the order of 4, while the W / L of each transistor 40.
Can be on the order of 6 or more.

Each of the nodes N2 and N3 is coupled to the input ends of the NAND function section 42 and the NOR function section 44. The output terminal of the NAND function unit 42 is connected to the NOR function unit 44.
Similarly to the output end of the NOR function unit 46, it is connected to the input end of the NOR function unit 46 via the inverter 41. Line TC is NO
It is connected to the input end of the R function unit 46. NOR function part 4
The output of 6 is sent to the line CM via a pair of inverters 45.
Drive PR. When driving the state of the line CMPR, the operation of the NAND function unit 42 and the NOR function units 44, 46 together with the inverters 41, 45 is such that the nodes N2, N3 having a low level output forced by the high line TC. Is the same as the exclusive OR of The following truth table represents the state of the line TC and the line CMPR in response to the nodes N2, N3.

TC N2 N3 CMPR 1 0 1 0 (parallel test disable) 0 1 1 0 (test pass, all 0) 0 0 0 0 (test pass, all 1) 0 0 1 1 (test fail) As will be apparent from the description, the TC low, N2 high and N3 low conditions cannot occur in this embodiment of the invention.

In operation, if line TC is high, indicating that parallel testing is not enabled, then both transistors 31 and 39 are on and both transistors 34 and 42 are off: Regardless of the state of the lines of read data bus 22, node N2 is low and node N3 is high. This is a line CMP, as shown by the truth table above.
Delivered on R with a low logic level.

When the parallel test is enabled by the operation of test enable circuit 30, it drives line TC low, turning off transistors 31 and 39 and turning on transistors 34 and 42. In this state, the logic state of read data bus 22 determines the states of nodes N2 and N3, and thus the state of line CMPR. Therefore, the result of the parallel read operation can be determined by the test data comparator 32.

In this embodiment, if all eight lines of read data bus 22 are at a high logic level (a "1" is stored in each of the eight accessed memory cells). All N-channel transistors 36 _{0 to} 36 ₇ in NOR function 35 are turned on, and thus node N2 is driven low. Furthermore, P-channel transistors 40 _{0 to} 4
Any _0-7 will not be turned on. Because transistor 42 is on because line TC is low, node N3 is also at low level. Referring to the truth table above, the condition that both line TC and nodes N2, N3 are low will force a low logic level on line CMPR, indicating that the parallel read is a pass. Because all eight accessed cells have the same data state (in this case, "1"). If desired, the true data state can be delivered to terminal DQ, as described in the aforementioned US patent application Ser. No. 552,567.

Conversely, if all eight lines on the read data bus 22 are low (representing a "0" stored in each of the eight memory cells accessed), the NAND function. All P-channel transistors 40 _{0 to} 40 ₇ in section 37 are turned on, driving node N3 high, and P-channel transistor 36
None of _{0 to} 36 ₇ are on and transistor 3
4 (on due to low line TC) is node N
Allows 2 to be pulled high. As shown in the truth table above, the condition that line TC is low and both nodes N2 and N3 are high will cause a low logic level on line CMPR, again causing the parallel test read to pass. That is, it means passing.

If all eight lines on the read data bus 22 do not have the same data state, then
Line CMPR is driven high, indicating a failure. For example, read data line 22 ₂
Is high while all other test data lines are low (ie, the accessed memory cell associated with the read data bus line 22 ₂ has an incorrect data state). N-channel transistor 36 ₂ is on (and all other transistors 36 are off). As mentioned above, each of the transistors 36 has a significantly greater drive than the transistor 34 in the NOR function 35, so that the transistor 36 ₂ overcomes the drive of the transistor 34 and pulls node N2 low. Since the other seven read data lines 22 are low, seven of the transistors 40 in NAND function 37 are on and drive node N3 high. Referring to the truth table above, line TC is low, node N2 is low and node N is low.
A high of 3 drives a high logic level on line CMPR, indicating that not all of the memory cells accessed in a parallel read operation have the same data state therein, and Indicates that the test has failed.

As described above, the transistor 40 in the NAND function section 37 is dimensioned so that the driving of any one of the transistors 40 outweighs the driving of the transistor 42. Thus, if only one of the read data lines 22 has a low logic level while all others have a high logic level, node N3 will be pulled high and NOR function 35 will Drive node N2 high due to the seven read data lines 22 having a high logic level. As in the fail case described above, line CMPR is driven high, representing a fail condition. Test data comparator 32 according to the invention
The arrangement provides significant advantages over conventional on-chip parallel test data comparators, especially when the number of bits tested in parallel increases. First, each internal data bus line is simply connected to the gates of two transistors instead of connecting to the pull-up transistor and pull-down transistor in each of the plurality of logic function units. It is parallel rather than serial to the data path used. As a result, the load and delay of the parallel test comparison circuit according to the present invention has a minimal effect on the performance of the memory in the main data path and in normal operation. Second, the transistors in the test data comparator 32 can be kept relatively small in size, which makes the layout of the parallel test circuit efficient and makes parallel comparison extremely easy. Let me do it. This is because the delay through test data comparator 32 is minimal and independent of the number of test data lines compared. As such, the present invention is particularly useful for modern memories, such as dynamic RAMs, where 32 or more bits may be tested in parallel. It is also easy to add scheduled data comparisons into the parallel test circuit according to the invention. Because it only needs to add two transistors in parallel with those receiving the internal data lines.

The memory 1 has a single input / output terminal DQ in this embodiment, but of course the invention is applicable to other memory configurations as well, in particular It is also possible to apply to those in which the number of memory cells accessed in either test mode or normal operation exceeds the number of output terminals. The present invention is particularly useful for a memory capable of selecting the number of input / output terminals DQ by changing a metal mask, for example.
This is because it allows a memory with a smaller number of terminals to be tested in substantially the same test time as one with all terminals selected.
Selection of the number of input / output terminals by metal mask is desirable for memory manufacturers. because,
This is because it allows flexibility in manufacturing planning until later in the manufacturing process.

An example of an integrated circuit constructed according to the preferred embodiment of the present invention will now be described with reference to FIG. It should be noted that the embodiment shown in FIG. 3 is similar to the embodiment shown in FIG. 1, and therefore elements that achieve the same function are provided with the same reference numbers. Therefore, in the following description, the portions of the embodiment of FIG. 3 different from the embodiment of FIG. 1 will be mainly described.

The memory 1 in this embodiment is of the byte width type and, as such, it has eight input / output terminals DQ _{0 to} DQ ₇ , in which:
Output data is provided during a read operation and input data is received during a write operation. The input / output circuit 20 has, on the one hand, an output data bus 22
And an input data bus 38 and, on the other hand, a terminal DQ, and has a conventional input and output buffer connected thereto.

In this embodiment, the memory array is divided in half and the array blocks 10 _{0 to} 10 ₇ are divided.
Form one half of the array and the array blocks 10 _{8 to} 10 _{15 form the} other half. An internal data bus 22 runs half the length of these arrays and is located between them as shown in FIG. One for each individual data conductor on the data bus 22
It connects to the corresponding data driver in each of the 16 data driver groups 15 of the 6 array blocks 10 _{0 to} 10 ₁₅ . In the case of a read / write memory, such as memory 1, the input data bus 38 may further include
It is connected to each of the sense / write circuits 13 for delivering input data to be written from the terminal DQ via the input / output circuit 20 to the selected memory cells in a conventional manner. On the other hand, as is known in the case of certain memory configurations, the input data can be sent along the data bus 22 in a time-multiplexed manner.

It is desirable to provide one dummy data conductor in the data bus 22 in association with each of the data conductors for fast read access times. Each dummy data conductor is driven to a relatively complementary state with its associated data conductor so that precharging of the data conductor on the data bus 22 can be accomplished by charge splitting between the two.

Next, with reference to FIG. 4, description will be given on the configuration of columns in the array block 10 of the memory 1. This configuration and its operation are described in detail in U.S. Patent Application No. 627,059 filed December 3, 1990, which is assigned to the present applicant. The memory cell 30 shown in block form in FIG. 4 is a conventional static RAM cell in the present embodiment, which is composed of, for example, cross-coupled N-channel inverters with resistive loads. Each cell is connected to the true and complement bit lines BLT and B via the N-channel pass transistor 31.
LC (T and C stand for true and complement, respectively). The gate of the pass transistor 31 has a row line R activated by appropriate row decoders 24a and 24b.
Controlled by L. As is well known for memory circuits,
Due to the operation of row line RL, only one memory cell 30 is coupled to each pair of bit lines BLT and BLC.

[0055] Bit lines BLT, each BLC is connected to the drain of the P-channel transistor 32, the source of the transistor 32 is connected to the (V _cc in the present embodiment) pre-charge voltage. In this embodiment of the invention, the gate of transistor 32 is controlled by line COLEQC _n from its associated column decoder 26a, 26b. Accordingly, transistor 32 is shown to indicate that the line COLEQC _n from column decoder 26 is at a low logic level and that column is not selected.
Precharge the bit lines BLT and BLC. The P-channel balancing transistor 34 has its source-drain path connected between the bit lines BLT and BLC, and its gate connected to the line COLEQ from the column decoder 26.
Are connected to the C _n, thus line COLEQC _n time during a low (i.e., during precharge via transistors 32), bit lines BLT, BLC is V _cc when the same voltage (this ).

As described in the above-referenced US patent application Ser. No. 627,059, the signal on line COLEQC _n that enables precharging and balancing of column n in memory 1 is the column address value (ie, it is selected). Line COLEQT _n
Is the logical complement of). Therefore, during the time period when the column n is not selected, the bit lines BLT, B
The LCs are precharged and equilibrated with each other. Figure 3
In the case of memory 1 of, this means that all columns in array block 10 that have no selected columns and all unselected columns in selected array block 10 Means all are in precharge and equilibration. The advantages of this decoded precharge and balancing control are described in detail in the above-mentioned US Pat. No. 627,059, and, generally, only selected columns are precharged and balanced. All that needs to be done is that the active current drawn for precharging and balancing is reduced. Moreover, the transients generated in the memory 1 are significantly reduced. This is because the instantaneous current required to carry out precharge and balancing is significantly reduced. Such an arrangement also eliminates the need for static or other loads on the bit lines and provides pull-ups for unselected columns that have not been released and thus selected memory cells 30 or write circuits. Without facing a pull-up or other DC load connected to it,
It makes it possible to establish a differential signal on the bit lines BLT and BLC in the floating state.

On the other hand, the gates of the precharge transistor 32 and the balancing transistor 34 are controlled by a global timing signal from the timing / control circuit 29 so that all columns are simultaneously balanced and precharged. , So that all columns are released on each access, so that the contents of the selected memory cell 30 in the selected row, regardless of whether that column is selected or not, can be changed to the bit lines BLT, BLC. Will be deployed across. Such an operation occurs in a conventional dynamic RAM, so that refreshing of unselected columns is performed. A memory based on this alternative configuration can also benefit from the present invention.

Each of the bit lines BLT and BLC further includes
It is connected to the pass gates 36, and each pass gate 36 has a P
It has a channel transistor 36p and an N-channel transistor 36n, and their source / drain paths are connected in parallel. Input / output lines 21T _j , 2
1C _j (true and complement, respectively) are connected from the bit lines BLT and BLC to the opposite side of the pass gate 36, respectively. The gate of the transistor 36n is the line COL.
Connected to EQC _n and the gate of transistor 36p is connected to line COLEQT _n , so that transistors 36n and 36p for a column will only be selected if that column is selected (ie, line COLEQC _n is high). Is on and line COLEQT _n is low), and transistors 36n and 36p for a column are not selected for that column (ie, line COLEQC _n is low and line COLEQT _n is high). Is off. Therefore, the pass gate 36
Is the state of the bit lines BLT and BLC, if the column is selected as represented on lines COLEQC _n and COLEQT _n , the input / output lines 21T _j and 21T _j and 21
Send to C _j . The columns of FIG. 4 have sense / write circuit 1 as represented by input / output lines 21T _j and 21C _j.
It is associated with the jth of three. Note that each of the columns in array block 10 _n associated with the jth sense amplifier 13 has their pass gates 36 connected to input / output lines 21T _j and 21C _j . Since only one of these columns is selected by the column decoder 18 for a given column address value, the input / output lines may be turned off if the unselected columns turn off their pass gates 36. There is no bus contention on 21T _j and 21C _j .

Next, with reference to FIG. 5, the structure of an example of the detection / write circuit 13 including both the read path and the write path will be described. Of course, it is also possible to use sense amplifiers and write circuits having other configurations in connection with the present invention. In particular, one example of such another configuration is a multi-stage sense amplifier configuration, in which a level shifter stage connected to each of the differential bit lines to realize a DC level shift is followed by a current mirror and a differential sense. It includes a combination with an amplifier (differential sense amplifier similar to that shown in FIG. 5). Other sense amplifier configurations can be used in variations of the one shown in FIG.

In FIG. 5, the complementary input / output line 21T
_j and 21C _j are each connected to the drain of a P-channel precharge transistor 42, the source of which is both the input / output line 21T _j , 21C.
connected to (V _cc if the) precharge voltage for _j. The input / output lines 21T _j and 21C _j are further connected to each other by a P-channel balancing transistor 41. The gates of transistors 41 and 42 are connected to line IOEQC, which is the ATD circuit 2.
Address transition detected by 5 or input / output line 2
A balance of 1 is generated by the timing and control circuit 29 in response to such other events during the cycle period where it is desired.

On the read side of the sensing / writing circuit 13 _j , each of the input / output lines 21T _j , 21C _j is connected to a P-channel pass transistor 43, the gate of each of the pass transistors 43 being separated by the isolation signal ISO. Controlled. Therefore, the input / output lines 21T _j and 21
C _j can be isolated from the read circuit by the line ISO being at a high logic level and connected to it by the line ISO being at a low logic level. The complement lines on the opposite side of the pass transistor 43 from the true and complement input / output lines 21T _j and 21C _j are the true and complement sense nodes SNT in FIG. 5, respectively.
And SNC.

As will be described below, the sensing / writing circuit 1
If the sense amplifier 48 in 3 operates in a dynamic manner, the sense nodes SNT, SNC are preferably precharged and balanced during the appropriate part of the cycle. Each of the P-channel precharge transistors 46 has its source / drain path connected between V _cc and each of the detection nodes SNT and SNC. The balancing transistor 45 is a P-channel transistor whose source / drain path is the detection node SN.
It is connected between T and SNC. The gates of transistors 45 and 46 are all controlled by the line SAEQC,
When it is at a low level, it has bit lines BLT, BL
Precharge and balance nodes SNT, SNC in a similar manner as described above for C and input / output lines 21T _j , 21C _j .

The sense amplifier 48 is a conventional CMOS latch composed of cross-coupled inverters, the input and output ends of which are connected in a conventional manner to the sense nodes SNT, SNC. There is. The N-channel pull-down transistor 47 has its source
The drain path is connected between the source of the N-channel transistor in sense amplifier 48 and ground, and its gate is controlled by line SCLK.

The pull-down transistor 47 provides the dynamic control of the sense amplifier 48 and thus the sense node SNT,
The SNC detection operation is performed in a dynamic manner. As is known in the dynamic RAM, the dynamic detection in this configuration is performed by the pass transistor 43 being the detection nodes SNT and S.
Transistor 47 is initially controlled to be off when connecting NC to input / output lines 21T _j and 21C _j , and during this part of the cycle, sense amplifier 48 connects between sense nodes SNT and SNC. A small differential voltage is supplied. After this small difference voltage is generated, the line SCLK is driven high and thus the sense amplifier 4
The source of the pull-down transistor in 8 is pulled to ground. This causes sense amplifier 48 to generate a large differential signal on sense nodes SNT, SNC and to latch the sensed state of sense nodes SNT, SNC.

In this embodiment, the sense amplifier 13
_j is associated with the input / output terminal DQ _k . Therefore, the sense nodes SNT, SNC are coupled to the inputs of the tri-state data driver 15 _jk , which drives the data bus conductor 22 _k which is connected to the input / output circuit 20. In the read operation, the input / output circuit 20
A suitable output driver is included to provide the state of the data bus conductor 22 _{k at} the input / output terminal DQ _k .

Next, looking at the write side of the detection / write circuit 13 _j , the line 38 _{k of} the input bus 38 is connected from the input / output terminal DQ _k via the input / output circuit 20 in the write operation. Send the input data of. The write control signal WDE from the timing and control circuit 29 and the input data line 38 _k are received by the inputs to the NAND gates 54T and 54C (line 38 _j indicates that it is NAND).
Inverted by inverter 53 before connecting to gate 54C). In accordance with the present invention, a balance enable signal (eg,
The write control signal WDE is generated in accordance with the timing of the lines COLEQC, IOEQC. The generation of the write control signal WDE and the advantages of the invention in such generation will be described below.

The output of the NAND gate 54T controls the gate of the P-channel pull-up transistor 56T which is connected in a push-pull manner together with the N-channel pull-down transistor 57T, and the output of the NAND gate 54T is supplied to the P-channel via the inverter 55T. It is connected to the gate of an N-channel pull-down transistor 57C which is connected in a push-pull manner with pull-up transistor 56C. Similarly, the NAND gate 54
The output terminal of C is directly connected to the gate of the pull-up transistor 56C and is also connected to the gate of the pull-down transistor 57T via the inverter 55C. The drains of transistors 56T and 57T drive input / output line 21T _j , and transistor 56C
And the drains of 57C drive the input / output line 21C _j .

Therefore, the write side of the sensing / writing circuit 13 _j operates as a complementary pair of tristate drivers.
The driver provides a high impedance state to the input / output lines 21T _j , 21C _j in response to the write control line WDE being at a low logic level, which drives both outputs of NAND gates 54T and 54C. All the transistors 56T, 56C, 5 are set to a high logic level.
Turn off 7T and 57C. Of course, during read cycles and during write cycles to array block 10 other than those associated with sense / write circuit 13 _j ,
The write control line WDE is at such a low logic level.

According to this preferred embodiment, a source follower is provided on the write side of the sensing / writing circuit 13 _j .
N-channel transistor 60T has its source connected to input / output line 21T _j and its drain is V
biased to _cc , the gate of transistor 60T is inverted twice by inverters 55C and 59C N
It is controlled by the output of the AND gate 54C. Similarly,
The source of the N-channel transistor 60C is input /
It is connected to the output line 21C _j and its drain is V _cc
Biased to and the gate of transistor 60T is controlled by the output of NAND gate 54T which is inverted twice by inverters 55T and 59T.

After the write operation and before the read operation,
To help pull up input / output lines 21T _j and 21C _j, source follower transistors 60T and 60C are provided (often referred to as "write recovery"). To explain the operation, during the write operation,
One of the input / output lines 21T _j and 21C _j driven low by pull-down transistor 57 turns off its associated source follower transistor 60 (by inverting from inverter 59), and source follower transistor 60 is , Other input / output lines driven high by its pull-up device 56.
When the write control line WDE returns to a low logic level at the end of the write operation, both outputs of NAND gate 54 are high and thus transistor 60 that was not previously on.
Is turned on. This causes the associated input / output line 21 _j from its previous low level to the voltage V _cc -V _t.
Pull up toward (Note that V _t is transistor 6
0 threshold voltage). The precharge transistor 42, once turned on, receives the input / output line 2
When 1T _j and 21C _j are completely pulled up to V _cc and the voltage on the input / output lines 21T _j and 21C _j reaches a voltage above V _cc -V _t , the transistor 60 has no further effect. Therefore, the source follower transistor 60 assists in write recovery of the memory 1 without requiring critical timing control and in a manner that reduces di / dt noise. In addition, since both source follower transistors 60 are on during the read operation, input / output lines 21T _j and 21C _j will have V _cc
Is clamped to -V _t, it makes it possible to generate a differential voltage easily at thereon.

The write circuit described in sense / write circuit 13 _j is particularly advantageous as described above and in the above-referenced US Pat. No. 627,059, but this circuit is described by way of example. It's just a thing. It should be understood that other conventional write circuits whose operation is controlled by signals such as those mentioned above on line WDE can be used with the present invention, and thereby take full advantage thereof. It is possible.

Next, the control circuit 29 'in the timing / control circuit 29 will be described in detail with reference to FIG. The function of the control circuit 29 'is that the balancing signal SA described above is used.
To generate EQC, IOEQC, COLEQC, and to perform other operations useful in both read and write operations in memory 1. In addition, the control circuit 29 'controls the write control signal WD received by the write circuit in each of the sense / write circuits 13 in the memory 1.
It is also for generating E. Generating the write control signal WDE in accordance with the present invention is particularly beneficial in achieving a high performance write operation with limited risk of race conditions and other errors in such operation. Is.

The control circuit 29 'has a read / write terminal R /
It receives a first input from W_ (not shown, but buffered in a conventional manner if desired), which indicates that a read operation should be performed at a high level and a write at a low level. Indicates that the action should be taken. The read / write terminal R / W_ is
Clock generator 64 and inverter 61 (line WE
Via (above) to the first input of AND gate 66, the output of AND gate 66 drives line WDE with the write control signal described above. Clock generator circuit 64 can be configured in a conventional manner to generate an internal clock signal in response to a pulse on line ATD, which internal clock signal implements a balancing operation in memory 1. In order to have a desired delay and period from the ATD pulse, which can be different than that of the ATD pulse. The present invention does not rely on delays within the clock generator 64 for proper signal generation, it being possible to use delays therein for optimizing circuit performance.

The control circuit 29 'further includes an ATD circuit 25.
In response to detecting a transition at one of the address inputs (or, if desired, a control signal input) from the line ATD, and thus a positive polarity on line ATD at the beginning of a new memory cycle. A pulse appears. Clock generator 62 receives line ATD and outputs signal EQ.
And the signal EQ is applied to an inverter 63 having an output for driving the line EQC. As in the case of clock generator 64, clock generator 62 is conventionally configured to generate a clock signal of desired timing and duration in response to terminal R / W_.
And it is possible to have a delay built in to optimize the performance of the memory 1. Line EQC is AN
It is applied to the second input of D gate 66. Line EQC
Are further received by various buffers or drivers 68, each of which produces a particular balancing signal which is applied to the column and sense / write circuit 13 as described above. In this embodiment of the invention, line EQC is low during balancing for all columns, and high when balancing is not enabled.

Therefore, the line WDE corresponds to the logical AND of the lines WE and EQC. As mentioned above, line WDE operates to allow data from input data bus 38 to be written to the selected memory cell via input / output lines 21T, 21C when at a high logic level. . Referring again to FIG. 4, in this embodiment of the invention, line WE is high (indicating that a write signal was received at terminal R / W_) and line E.
Line WDE is at a high logic level when QC is both high (indicating that the balancing portion of the cycle has not occurred). Therefore, the write circuit in sense / write circuit 13 is enabled only during the unbalanced portion of the cycle. As will be explained below, such gating of the write enable signal on line WDE, which corresponds to balancing, ensures proper operation of the write operation in memory 1, even at high speeds.

Next, the operation of the memory 1 according to the present invention will be described with reference to FIG. 7, and particularly an example of a write operation to an arbitrary memory cell 30 having address values n and n + 1 will be described. This example starts from the cycle before the read operation to the memory cell 30 specified by address n-1 was performed. Therefore, terminals A _{0 to} A
_n (shown on line ADDR in FIG. 7) and internal decode address value (line INT in FIG. 5)
Both (denoted on ADDR) carry the value n-1 and terminal R / W_ is at a high logic level.

In the next cycle, the address terminals A _{0 to} A
_The new address value received at _n (in this case,
Starting with the value n), at this time a low logic level is received at the terminal R / W_, which in the present case indicates that a write operation should be performed. In response to the transitions at one or more of the address terminals A _{0 to} A _n and at the terminal R / W_, the AND circuit 25 outputs the line AT.
Generate a high logic level pulse on D. This line AT
The high level pulse on D is received by the control circuit 29 '(FIG. 6) which responds to the line E.
Generate a low logic level pulse on QC. As mentioned above, the low logic level pulse on line EQC is
Generate active low pulse on OEQC and SAEQC (both to sense / write circuit 13) and line CO
Precharge and balancing operations are initiated via buffer driver 68 (for all bit lines) which generate low and high pulses on LEQC and COLEQT, respectively.

During the equilibration period, shown in FIG. 7 as the period when line EQC is low, address decode operations and other internal operations can be performed in memory 1 in preparation for the desired access. As shown in FIG. 7, the internal decode address reaches a new value corresponding to address value n, and clock generator 64 also generates a high logic level on line WE.

In conventional memory, the signal on line WE (or a similar signal) generated at terminal R / W_ is provided to control the write circuit in the sense / write circuit. However, the timing of this signal in relation to the address decoding operation is important. because,
If it occurs before the stabilization of the internal address value, the data is written to the memory cell corresponding to the previous address value (in this case address n-1) as well as the desired address. I will end up. Therefore, the memory array will store incorrect information.

However, in this embodiment of the invention, line WE is not directly coupled to the write circuitry within sense / write circuit 13, but instead receives and receives line EQC at the other input. AN in control circuit 29 'driving line WDE at the output
It is supplied to the input terminal of the D gate 66. As a result, line WDE will not be driven high and will not enable the write circuit until the balancing operation is complete, as represented by driving line EQC to a high logic level. If address transitions are continuously detected, the balancing period will continue to exist, so
The signal on line EQC is generated from the ATD pulse and the internal decode address value has stabilized by the time the balancing is complete. As a result, the timing of the line WE relative to the decoding of the internal address value is no longer critical.

Furthermore, especially for extremely long memory chips, conventional memory configurations require consideration of write operations in internal address propagation and timing path design for signals such as ATD pulses.
In particular, if the timing of such signals is optimized solely for read performance in such memories, the internal address signals may reach the memory location before the end of the write operation, where A write error may occur. This required that the timing design of these signals balance the read and write timing of the memory. However, in accordance with the present invention, the interlock between the internal write signal and the balancing timing should be optimized only for read access time performance without exposing the memory to the risk of end-of-write errors. Internal read signal (eg,
It is possible to design the timing of (address propagation).

When line WDE goes high, the write circuit in the selected sense / write circuit 13 _j is enabled and the data on its associated input data bus conductor 38 _k to input lines 21T _j and 21C _j . Provided and programmed into the selected memory cell 30 corresponding to the selected column and row. Line WDE is the next cycle (as shown)
It can be driven high continuously or timed out to reduce power dissipation.

When the next address value n + 1 is received, the ATD
Circuit 25 again generates a high level pulse on line ATD, which again drives line EQC to the low state as previously described, performing the balancing operation. When line EQC goes low, line WDE goes to terminal R
Despite the low logic level signal remaining at / W_, it is driven low by the operation of AND gate 68. This balancing operation occurs in memory 1, as in conventional memory, well before the address value decoding operation. As such, the write operation is terminated before internally receiving the new address value, precluding the erroneous writing of the previous cycle's input data into the next cycle's address. As with the previous cycle, line WDE is driven high with the completion of equilibration, as generated by the return of line EQC to the high state.

Therefore, according to the present invention, when the write enable signal sent to the write circuit is interlocked with the balancing signal, high performance is achieved with the risk of writing to the wrong position being minimized. It is possible to carry out a write operation. The write enable signal does not start before the completion of the balancing that depends on address stabilization and thus guarantees that no data will be written to the memory location accessed in the previous cycle. There is. Further, the write enable signal ends at the beginning of balancing in the next cycle, thus ensuring that the data of the previous cycle is not written to the address of the next cycle. Such control is performed independent of relative delay periods, thus minimizing the risk of race conditions, especially for high speed, large chip size integrated circuit memories.

Although specific embodiments of the present invention have been described in detail above, the present invention should not be limited to these specific examples, and various modifications can be made without departing from the technical scope of the present invention. It goes without saying that the above can be modified.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing a memory incorporating a preferred embodiment of the present invention.

2 is a schematic diagram illustrating a multi-bit data comparator for a parallel test mode in the memory of FIG.

FIG. 3 is a schematic block diagram showing a memory according to another preferred embodiment of the present invention.

4 is a schematic diagram of a typical column in the memory of FIG.

5 is a schematic diagram showing a sense amplifier / write circuit in the memory of FIG.

6 is a schematic block diagram showing a part of a timing / control circuit in the memory of FIG.

FIG. 7 is a timing diagram showing the operation of the preferred embodiment of the present invention.

[Explanation of symbols]

 1 Memory 10 Memory Array Block 13 Detection / Write Circuit 15 Data Driver 20 I / O Selection Circuit 22 Read Data Bus 23 Input Buffer 25 Output Buffer (ATD Circuit) 28 Address Buffer 29 Timing / Control Circuit 30 Test Enable Circuit 32 Test Data Comparison vessel

Claims (33)

[Claims] 1. A data comparator circuit in a memory having a parallel test mode in which a plurality of on-chip data lines are compared with each other, wherein a first logic function unit having a first output node is provided, and One logic function unit includes a first pull-up device coupled between the first output node and a first bias voltage corresponding to a first logic state to bias the first output node to a first bias voltage; And each having a conductive path coupled between the first output node and a second bias voltage corresponding to a second logic state and each being coupled to an associated one of the plurality of data lines. A second logic function unit having a second output node, the second logic function unit having a plurality of pull-down transistors each having a terminal; A pull-down device coupled between the second output node and the second bias voltage for biasing a bias to a second bias voltage, and each coupled between the second output node and the first bias voltage. In such a manner that each has a conductive path and each turns on either its associated pull-up transistor or its associated pull-down transistor in the digital data state to which each of said plurality of data lines is supplied. A plurality of pull-up transistors having a control terminal coupled to an associated one of the plurality of data lines, and coupled to the first and second output nodes. Generating a pass signal in response to the second output nodes being in the same logic state and the first and second output nodes being in different logic states. A circuit characterized in that it is provided with an output logic function unit which generates a fail signal in response to a certain thing. 2. The first transistor according to claim 1, wherein the pull-up device comprises a conduction path coupled between the first output node and a power supply node and a control terminal coupled to an enable line. The pull-down device has a second transistor having a conduction path coupled between the second output node and a reference supply node and having a control terminal coupled to the enable line. And each of the pull-up device and the pull-down device is rendered conductive in response to the enable line indicating that the circuit is enabled, and each of the pull-up device and the pull-down device is Characterized in that said enable line is rendered non-conductive in response to indicating that said circuit is disabled. Circuit to do. 3. The output logic function unit according to claim 2, wherein the output logic function unit receives the enable line at an input terminal, and the output logic function unit indicates that the circuit is to be enabled. In response to the states of the first and second output nodes, and in response to the enable line indicating that the circuit should be disabled. A circuit characterized by being disabled in responding to a condition. 4. The first forcing transistor of claim 3, wherein the first logic function unit further comprises a conduction path in parallel with the plurality of pull-down transistors and a gate coupled to the enable line. And the first force transistor is off in response to the enable line indicating that the circuit should be enabled, and the first force transistor has the enable line disabled for the circuit. Responsive to indicating that it should be, and the second logic function further comprises a conduction path in parallel with the plurality of pull-up transistors and a gate coupled to the enable line. And a second forcing transistor for enabling the enable line for the circuit. Disabled and the second force transistor is on in response to the enable line indicating that the circuit should be disabled. circuit. 5. The plurality of pull-down transistors according to claim 2, wherein each of the plurality of pull-down transistors in the first logic function unit is dimensioned to be significantly larger than the pull-up device, and the plurality of pull-down transistors in the second logic function unit. A circuit characterized in that each of the pull-up transistors is dimensioned to be significantly larger than the pull-down device. 6. The circuit of claim 1, wherein the pull-up transistor and the pull-down transistor are field effect transistors having opposite conductivity types. 7. A memory in an integrated circuit comprising an array of addressable memory cells, means for selecting a plurality of said memory cells in said array, said selected plurality of memory cells being provided. Means for sensing the storage state in the memory cell and delivering it to a plurality of data lines are coupled to the plurality of data lines and one of the states of the data lines is connected to a terminal. Means for transmitting to the plurality of data lines in parallel with the feeding means, and a data comparator for comparing the states of the plurality of data lines with each other are provided, The data comparator is coupled to the first logic function unit having a first output node, the second logic function unit having a second output node, and the first and second output nodes; And an output that produces a pass signal in response to the second output nodes being in the same logic state and a fail signal in response to the first and second output nodes being in different logic states. A logic function unit, the first logic function unit being coupled between the first output node and a first bias voltage corresponding to a first logic state, A first pull-up device for biasing to one bias voltage, each having a conduction path coupled between the first output node and a second bias voltage corresponding to a second logic state, and each of the plurality of the pull-up devices. A plurality of pull-down transistors having a control terminal coupled to one of the associated data lines of the second logic function section of the second logic function section and the second bias voltage section. Bound in between A pull-down device for biasing the second output node to a second bias voltage, and a conduction path each coupled between the second output node and the first bias voltage, and each of the plurality of conduction paths. An associated one of the plurality of data lines in such a manner that each of the plurality of data lines turns on either its associated pull-up transistor or its associated pull-down transistor in the transmitted digital data state. A memory having a plurality of pull-up transistors coupled to the memory. 8. The memory of claim 7, further comprising means for enabling the comparator in response to an external signal indicating that parallel test mode should be enabled. 9. The method of claim 8, wherein the enable means drives an enable line at its output, the enable line representing whether the parallel test mode is enabled or disabled; The pull-up device has a first transistor having a conduction path coupled between the first output node and a power supply node and having a control terminal coupled to the enable line, and the pull-down device comprises: A second transistor having a conduction path coupled between the second output node and a reference supply node and having a control terminal coupled to the enable line, the pull-up device and the pull-down device comprising: Each is rendered conductive in response to the enable line indicating that the circuit should be enabled. And the pull-up device and the pull-down device are each rendered non-conductive in response to the enable line indicating that the parallel test mode should be disabled. 10. The output logic functional unit according to claim 9, wherein the output logic functional unit receives the enable line at an input terminal, and the output logic functional unit indicates that the parallel test mode is enabled. In response to the states of the first and second output nodes, and the first and second outputs in response to the enable line indicating that parallel test mode should be disabled. A memory characterized in that it is disabled to respond to the state of the node. 11. The first logic function unit according to claim 10, further comprising a first forcing transistor having a conduction path in parallel with the plurality of pull-down transistors and having a gate coupled to the enable line. The first force transistor is off in response to the enable line indicating that parallel test mode should be enabled, and the first force transistor is configured to enable the enable line to parallel test. ON in response to indicating that the mode should be disabled, and the second logic function further comprises a conduction path in parallel with the plurality of pull-up transistors and to the enable line. A second forcing transistor having a gate coupled thereto, the second forcing transistor comprising: The enable line is off in response to indicating that parallel test mode should be enabled, and the second force transistor is responsive to the enable line indicating that parallel test mode is to be disabled. Memory that is turned on. 12. The plurality of pull-down transistors in the first logic function section according to claim 9, each of the plurality of pull-down transistors having a size significantly larger than that of the pull-up device, and the plurality of pull-down transistors in the second logic function section. A memory characterized in that each of the pull-up transistors is sized significantly larger than the pull-down device. 13. The memory according to claim 7, wherein the pull-up transistor and the pull-down transistor are field effect transistors having conductivity types opposite to each other. 14. A method of comparing the data states of a plurality of memory cells in a semiconductor memory, wherein a first node is biased to a first voltage, the first node being at a second voltage via a first plurality of transistors. Is also connected to
The first and second voltages correspond to different logic levels and each of the first plurality of transistors is conductive and responsive to the data line associated with it being at the first logic level. A control terminal coupled to an associated one of the plurality of data lines in a manner such that the associated data line is rendered non-conductive in response to being at the second logic level; A conductive one of the plurality of transistors pulls the first node to the second voltage and biases the second node to the second voltage, the second node further including a second plurality of transistors. Coupled to the first voltage through a transistor, each of the second plurality of transistors being conductive and associated with a data line associated therewith being at a second logic level. A control terminal coupled to an associated one of the plurality of data lines in a manner such that the line becomes non-conductive in response to being at the first logic level; One of the transistors in the conductive state pulls the second node to the first voltage and sends the data state of each of the plurality of memory cells to a plurality of data lines. Later, a signal representing a pass condition is generated in response to the first and second nodes being at the same logic level and a failure is generated in response to the first and second nodes being at different logic levels. A method comprising the steps of generating a signal representative of a pass condition. 15. The method of claim 14, further comprising receiving a signal indicating that parallel test mode should be enabled, and the biasing step is performed in response to the receiving step. 16. The method of claim 15, further comprising the step of generating an enable signal in response to the receiving step to bias the first node, the conduction being coupled between the first node and a first voltage. Turning on a first bias transistor having a path and biasing the second node turning on a second bias transistor having a conductive path coupled between the second node and a second voltage. A method characterized by. 17. The method of claim 16, further comprising receiving a signal indicating that parallel test mode should not be enabled and generating a disable signal in response to the signal, and responsive to the generation of the disable signal. A second force transistor having a conduction path coupled between the first node and a second voltage, turning on a first conduction transistor, and having a conduction path coupled between the second node and a first voltage. A method characterized by turning on. 18. A read / write memory in an integrated circuit, wherein a plurality of memory cells are provided, a decoder for selecting a memory cell according to an address value is provided, and data to be written in the selected memory cell. Is provided, a read / write terminal for receiving a write selection signal is provided, a differential data line for sending data to the memory cell is provided, and the differential data line is provided. A balancing transistor coupled between the two and having a control terminal for receiving a balancing signal, the sensing transistor delivering data from the input data terminal to the selected memory cell via the differential data line. / Write circuit is provided, and the detection / write circuit comprises a control terminal for receiving a write enable signal, A balance control circuit is provided for generating the balance signal in response to an external signal indicating the start of a cycle, and a write control for generating the write enable signal in response to the write select signal and in response to the balance signal. A memory provided with a circuit. 19. The memory cell of claim 18, wherein the plurality of memory cells are arranged in rows and columns, and the differential data lines are associated with and between each of the columns. A memory having a pair of bit lines with connected balanced transistors. 20. The sense amplifier according to claim 19, further comprising a sense amplifier for detecting a differential signal from a bit line associated with a column including a memory cell selected in a read operation, the differential data line further comprising: Connected between the differential input / output line and a pair of differential input / output lines connected to the sense amplifier and providing a differential signal corresponding to the detected differential signal from the bit line. And a sense amplifier balanced transistor having a control terminal coupled to receive the balanced signal. 21. A sense amplifier according to claim 18, further comprising a sense amplifier for detecting a differential signal from a bit line associated with a column including a memory cell selected in a read operation, wherein the differential data line is A pair of differential input / output lines connected to a sense amplifier and providing a differential signal corresponding to a data state of a selected memory cell, and the balanced input / output lines. A sense amplifier balanced transistor having a control terminal coupled to receive a signal. 22. The memory of claim 18, wherein the write control circuit disables the write enable signal during a time period when the balance signal is active. 23. The memory of claim 18, wherein the write control circuit disables the write enable signal during a read operation. 24. The memory according to claim 18, further comprising an address terminal for receiving the address value. 25. The memory of claim 24, wherein the external signal comprises a change in address value received at the address terminal. 26. The method of claim 18, further comprising a control terminal connected to one of the differential data lines and coupled to receive the balanced signal, the differential signal being responsive to the balanced signal. A memory having a precharge transistor for precharging a moving data line to a selected voltage. 27. A method of operating a read / write memory, wherein the memory sends / receives data from an input data terminal to a selected memory cell via a plurality of addressable memory cells and a differential data line. A circuit for balancing the differential data lines for a selected period of time in response to receiving an external signal indicative of the start of a memory access, and selecting a plurality of the plurality of data lines during the balancing step. An address value for selecting one of the memory cells, receiving a write signal and responsive to the end of the period of the balancing step to enable the sense / write circuit to decode the input data. A method comprising the steps of delivering to a memory cell selected by the step. 28. The method of claim 27, further comprising: after the start of the enabling step and in response to receiving an external signal indicative of the start of a second memory access.
A method characterized by disabling a write circuit. 29. The differential data line of claim 28, further comprising: after the initiation of the enable step and in response to receiving an external signal representative of the initiation of a second memory access, the differential data line for a selected period of time. Balancing, wherein the disabling step is responsive to the balancing step being responsive to receiving an external signal indicative of the initiation of the second memory access. 30. The method of claim 27, further comprising monitoring an address terminal of the memory to detect a transition therein, the external signal comprising detecting a transition at one of the address terminals. how to. 31. The pair of bit lines according to claim 27, wherein the plurality of memory cells are arranged in rows and columns and the differential data lines are associated with each of the plurality of memory cells. A method comprising: 32. The method of claim 31, wherein the differential data line further comprises a pair of input / output lines associated with the sense / write circuit. 33. The method of claim 27, wherein the differential data line has a pair of input / output lines associated with the sense / write circuit.