JPH05298887A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To enlarge the driving force of a word line driver by freely arranging the word line driver through the use of a word line jump wiring by means of time division so as to enlarge an adjacent word line driver interval. CONSTITUTION:The output of a low decoder 24 and the output of the word line driver 10 are alternately transmitted by time division in the word line jump wiring WLJ so that the driver 10 can be arranged at the both sides of a cell without increasing the wiring. That is, the low decoder 24 directly executes the output to the wiring WLJ, but, at this point of time, connection to a line WL is interrupted by a transistor 28 controlled by the output CBS from a column block decoder 22. Therefore, the wiring WLJ only executes the transmission of the low decoder output. Then, the word line driver can be freely arranged and the adjacent word line driver interval is enlarged so that the driving force of the word line driver can be enlarged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, more specifically a dynamic random access memory (DRA).
Drive circuit of the word line in M) and HV _CC (1/2
DRA for precharging the sense amplifier by V _CC )
Regarding M.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a conventional technique of a word line driving circuit portion in a DRAM. In the figure, the word line drivers 30A and 30B are supplied with a boosted potential from the word line driver power supply 32. That is, these word line drivers 3
When 0 is selected by the row decoder 34, the boosted potential is supplied from the selected word line driver 30 to the word line jump wiring WLJ and the word line WL.

The word line WL is usually formed of a high heat-resistant material such as Poly-Si, but since this material has a high resistance, the jump wiring WLJ made of metal makes contacts at regular intervals to reduce the resistance as a whole. Is going.
Since the jump wiring WLJ is arranged at the same pitch as the word line WL, another parallel wiring cannot be used in place of the jump wiring WLJ.

Further, FIG. 9 shows a prior art of a basic circuit of an HV _CC precharge type DRAM. As shown in the figure, the basic structure of the DRAM is a bit line pair BL,-
An equalizer 50, a memory cell array 52, a memory cell array, which eliminates the potential difference of BL (hereinafter, a symbol having a symbol "-" in the drawings is attached with a symbol "-" in this specification) A transfer gate TG for controlling the connection between 52 and the sense amplifier 62, an equalizer 54 for supplying a precharge potential of the bit line pair BL / -BL, and a sense amplifier 62.

Conventionally, a sense amplifier 62 in a DRAM is used.
Is composed of a flip-flop formed of a CMOS circuit as shown in FIG. FIG. 10 shows the relationship between the sense time for "0" read and "1" read in the sense amplifier 62 and the equalize potential V _EQ .

As shown in FIG. 10, the intersection of the "0" read graph and the "1" read graph is when the equalizing potential V _EQ is HV _CC , and the sense speed at this time is the fastest. Therefore, the sense speed is increased by setting the precharge potential to HV _CC .

[0007]

Returning to the prior art of the word line driving section described with reference to FIG. 3, in this case, the word line WL and the word line jump wiring WL are provided.
The word line driver 30 allows the memory cell array units 14-1 and 14- to reduce the number of wiring layer processes in J.
It is arranged on one side with respect to 2. If the driver 30 is arranged on only one side as described above, the word line pitch is inevitably narrowed in high integration, and it is difficult to design the word line driver 30 having a sufficient driving force.

To avoid this, if wiring can be provided from the row decoder 34 to the opposite side of the memory cell 14, the word line driver 30 can be arranged on both sides of the memory cell 14. For example, in JP-A-3-203892 and JP-A-3-203085, the word line driver 30 is arranged on both sides of the memory cell 14 in consideration of such a point, so that the arrangement pitch of the word line driver 30 can be set to the word line pitch. A conventional technique for doubling is disclosed.

However, although the word line jump wiring WLJ is not particularly described in these conventional techniques, if the word line jump wiring WLJ as shown in FIG. 3 is used, it is necessary to add a wiring layer. There is a drawback in that the number of steps is increased. This is because when the word line drivers 30 are simply arranged on both sides of the memory cell 14, either the word line WL or the word line jump wiring WLJ is used as a signal line for transmitting the output from the row decoder 34 to the word line driver 30. Because it cannot be used.

Further, in the conventional DRAM of the HV _CC precharge system described with reference to FIG. 9, N channel transistors are used as memory cells. Therefore, as shown in FIG. 11, the High-side signal "1" has a characteristic that it draws a sharp curve due to a junction leak and tends to lose the potential, and the Low-side signal "0" has a gentle curve and thus loses the potential easily. As described above, the potential of the signal stored in the memory cell becomes asymmetric with respect to the precharge level of HV _CC depending on the time between writing and reading.

Further, in this prior art, it reduces the stored potential V _m of the time from writing to reading longer "1", when the storage potential V _m becomes lower than the sense amplifier operation enable potential HV _CC + [Delta] V _m, Read error occurs. This defect is called a hold time defect.

In order to suppress the occurrence of the hold time failure, it is sufficient to reduce the sense time for "1" read. Therefore, as shown in FIG. 10, the precharge level V _{EQ is set} to HV.
If the potential is lower than _CC, there is a considerable effect. But,
In this way, when HV _CC is brought close to the ground level, the sensing time at "0" read becomes long,
There is a drawback that a read error is likely to occur when reading "0".

Further, in the prior art, the bit line pair BL /-
Since the BL is directly connected to the sense amplifier 62, the bit line capacitance becomes large including the sense amplifier capacitance, and the read output is reduced.

The present invention solves the drawbacks of the prior art of these semiconductor memory devices, improves the driving force by widening the arrangement pitch of the word line drivers to twice the word line pitch, and increases the number of steps by increasing the wiring layers. An object of the present invention is to provide a semiconductor memory device that does not increase and a semiconductor memory device that uses the HV _CC precharge method and has high reliability and a high sense amplifier operating speed.

[0015]

In order to solve the above-mentioned problems, the present invention has a word line driver for supplying a potential boosted by a word line driver power supply to a word line selected by a row decoder. In a semiconductor memory device that selects a memory cell corresponding to an address signal input from a driver, a word line driver and a row decoder are connected via a word line jump wiring,
The word line jump wiring is connected to the word line through a switch controlled by information on the column side in the address signal, notifies the word line driver of the selection output from the row decoder, and outputs the word line driver output to the switch. To the word line via. The row decoders are arranged on one side of the memory cells, and the word line drivers are arranged on the row decoder side and the opposite side thereof so as to be substantially arranged on both sides of the memory cells, and on the opposite side of the row decoder. The arranged word line driver is connected to the row decoder by the word line jump wiring.

Further, according to the present invention, in the semiconductor memory device for precharging HV _CC to the sense amplifier, the first equalize for precharging the precharge level on the bit line side at the precharge level V _EQ lower than HV _CC. Means and
Second to set the precharge level of the sense amplifier to HV _CC
And equalizing means for precharging the bit line side and the sense amplifier by the first and second precharging means.

Further, according to the present invention, the semiconductor memory device for precharging HV _CC to the sense amplifier is selected by inputting the HV _CC precharge level and the precharge level V _EQ lower than the HV _CC precharge level. Precharge potential output means for outputting any of these precharge levels in accordance with a signal, equalization means for inputting the precharge potential output from the precharge potential output means, and precharging the bit line according to the equalization signal, It has a first transfer gate and a second transfer gate, and the bit line side is precharged by the precharge level V _EQ by the precharge potential output means, the equalizing means, the first transfer gate and the second transfer gate. , the sense amplifier is pre-charged by the V _CC It is.

Further, according to the present invention, there is provided a word line driver for supplying the potential boosted by the word line driver power source to the word line selected by the row decoder, and the memory corresponding to the address signal inputted by this driver. In a semiconductor memory device in which HV _CC for selecting a cell is precharged to a sense amplifier, a word line driver and the row decoder are connected via a word line jump wiring. The word line jump wiring is connected to the word line through a switch controlled by the information on the column side in the address signal, notifies the word line driver of the selection output from the row decoder, and switches the output of the word line driver. The row decoder is arranged on one side of the memory cell, and the word line drivers are arranged on the row decoder side and the opposite side so as to be substantially arranged on both sides of the memory cell. The word line drivers arranged on the opposite side of the row decoder are connected by word line jump wiring. Further, in the present invention, the precharge level on the bit line side is precharged at the precharge level V _EQ lower than HV _CC , and the precharge level of the sense amplifier is precharged to HV _CC .

[0019]

According to the present invention, when the switch controlled by the information on the column side is off, the output from the row decoder is transmitted to the word line driver via the word line jump wiring. Next, when the signal from the word line driver power supply is input to the word line driver and the word line driver is selected, the word line driver enters the latch state and reaches the potential for driving the word line. Boost. When the word line driver is latched and the switch is turned on by the information on the column side, the boosted word line jump wiring and the word line are connected, and the memory cell connected to this word line starts operating. ..

According to the present invention, the sense amplifier is equalized by the second equalizing means located closer to the sense amplifier than the transfer gate, and the first equalizing means arranged closer to the memory cell than the transfer gate. Precharges the bit line side.

Furthermore, according to the present invention, the precharge potential output means sets the HV _CC precharge level during the equalization period of the sense amplifier according to the selection signal and the precharge level lower than the HV _CC precharge level during the equalization period of the bit line. The charge level V _EQ is output to the equalizing means. Also, during the equalizing period of the sense amplifier, the first transfer gate is turned on, and the sense amplifier is set to H level.
Precharged to V _CC precharge level. Further, during the equalizing period of the bit line, the second transfer gate is turned on and the bit line is precharged to the precharge level V _EQ .

[0022]

Embodiments of the semiconductor memory device according to the present invention will now be described in detail with reference to the accompanying drawings.

First, an embodiment of a semiconductor memory device according to the present invention will be described with reference to FIGS. FIG. 1 shows a DR as a semiconductor memory device characterized by a word line driving circuit.
It is a functional block diagram which shows the Example of the word line drive circuit in AM.

In the figure, word line drivers 10A and 10B, a word line driver power supply 12A, and a word line driver 10A and 10B are provided as word line driving units for the word line jump wiring WLJ and the word line WL corresponding to the input address signal.
12B, memory cells 14-1, 14-2, equalizer 1
6, a sense amplifier 18, a column decoder 20, a column block decoder 22, a row decoder 24 and a row predecoder 26 are shown. In addition, in this embodiment, in order to facilitate understanding of the present invention, a part of the semiconductor memory device according to the present invention is shown. That is, for example, a plurality of memory cells 14 are two-dimensionally arranged at the intersections of bit line pairs BL / -BL and word lines WL to form a memory cell array.

In the word line driver of this embodiment, the word line drivers 10A and 10B are the memory cells 14-
1 and 14-2 are arranged on both sides of the row decoder 24 and connected to the row decoder 24, and are also connected to the row predecoder 26 via the word line driver power supplies 12A and 12B having corresponding reference numerals. In this embodiment, a column block decoder 22 for inputting an address signal is also arranged, and this decoder 22 connects a transistor 28 for connecting a word line WL and a word line jump wiring WLJ.
-1 and 28-2 are connected to the gates.

In this embodiment, as shown in FIG. 1, the word line jump wirings WLJ are arranged so that the output of the row decoder 24 and the output of the word line driver 10 are alternately transmitted in a time division manner. The word line driver 10 can be arranged on both sides of the memory cell 14 without increasing the number of wiring layers.

In this embodiment, the output from the row decoder 24 is directly applied to the word line jump wiring WLJ, but at this time, the column block decoder 2 is used.
Transistor 2 controlled by output CBS from 2
8, the connection with the word line WL is cut off. Therefore, the word line jump wiring WLJ only transfers the row decoder output.

Next, when the signal from the word line driver power supply 12 is input to the word line driver 10 and the word line driver 10 is selected by the row decoder 24, the word line driver 10 latches. The state is entered, and the word line jump wiring WLJ is boosted to a potential for driving the word line WL.

When the word line driver 10 is in the latch state, the row decoder 24 is in the rest state so as not to be affected by the boosted potential, and the column block decoder output C
BS is output, the word line jump wiring WLJ and the word line WL are connected, and the operation of the memory cell 14 is started.

The word line driver 10 is a circuit that enters an operating state when the row decoder output and the word line driver power supply output are input at the same time and continues the operation until the word line driver power supply output is in the idle state. Figure 2
1 shows an example of a partial circuit of the functional block shown in FIG. 1. As shown in FIG. 1, each word line driver 10 can be composed of a CMOS flip-flop.

FIG. 4 shows the operation waveforms of this embodiment, and FIG. 5 shows the operation waveforms of the prior art shown in FIG. In the figure, “H” is a high level, “L” is a low level,
“B” indicates the boost level, respectively. In the conventional example, the period during which the word line WL is at the memory cell drive potential is determined by the output from the row decoder 34, but in this embodiment, the starting point is the column block decoder output CBS and the ending point is the word line driver power supply output PW. Determined by

During the period T ₁ when the word line jump wiring WLJ is used for transmitting the row decoder output, the load capacitance is small because the word line jump wiring WLJ is not connected to the word line WL. Therefore, high-speed signal transmission is possible, so that the signal transmission time can be extremely shortened and the influence on the access speed of the semiconductor memory device is small.

In this embodiment, the column block decoder 22 is used.
The transistor 28 connecting the word line jump wiring WLJ controlled by the word line WL and the word line WL is required. Therefore, since the word line WL connected to the word line jump wiring WLJ can be divided and connected, the power consumption can be reduced by reducing the number of operating memory cells.

In this embodiment, the word line driver can be arranged not only on both sides of the memory cell array but also in the memory cell array. Therefore, the driving capability can be improved by increasing the number of word line drivers connected to the word line jump wiring WLJ. It is possible to improve and shorten the access speed.

In the drawing used in this embodiment, one word line driver 1 is provided for the word line jump wiring WLJ.
Although 0 is connected, a plurality of word line drivers 10 are connected to the word line jump wiring WLJ, for example, and the row decoder 24 and the plurality of word line drivers 1 are connected.
0 may be connected by the word line jump wiring WLJ.

Next, an embodiment of the semiconductor memory device using the HV _CC precharge system will be described with reference to FIGS. 6 to 11.

FIG. 6 is a circuit diagram showing an embodiment of a semiconductor memory device in which the sense amplifier is precharged by HV _CC precharge. In the figure, bit line pair B
DR connected to L, -BL and directly related to this embodiment
A part of the peripheral circuit of the AM sense amplifier is shown, and in reality, a plurality of circuits shown in the figure are arranged.

The semiconductor memory device according to the present embodiment includes an equalizer 50, a memory cell array 52, an equalizer 54,
A sense amplifier 56 and an equalizer 58 are connected to the bit line pair BL, -BL as shown in the figure. In this embodiment, as compared with the conventional technique shown in FIG. 9, a transfer gate is included in the sense amplifier 56, and the equalizer 3 is provided.
Are arranged on the data line side.

That is, the sense amplifier 56 is opposed to the conventional sense amplifier 62 by the bit lines BL,-.
P-channel transistor P controlled by the potential of BL
₁ and P ₂ are the signal line SAP and the node N of the sense amplifier 56.
Connect between / and N. The signal line SAP is connected to the node N / -N.
Is high and there is a memory cell output of the memory cell array 52, a potential difference to be sensed appears due to the driving force difference between the transistors P _{1 and} P ₂ .

Since the bit line BL / -BL and the node N / -N are disconnected by the _two transistors N ₁ N ₂ before the end of sensing, the precharge level is BL / -BL.
And N / -N can be set separately. After the end of sensing, the transfer gate signal TG is set to High to rewrite the memory cells in the memory cell array 52.

An equalizer 58 for supplying HV _CC is provided on the sense amplifier side of the transfer gate TG, and a potential V lower than HV _CC is provided on the memory cell side of the gate TG.
There is an equalizer 54 that powers the _EQ .

V _EQ can be expressed by the following mathematical expression "Equation 1":

[0043]

[Equation 1]

At this time, the left side is the high-side read limit, and the right side is the low-side read limit. High-side reading is actually meaningless because it naturally deteriorates over time due to spontaneous discharge of the capacitor. By setting V _EQ to the low-side lower limit, a margin for spontaneous discharge can be provided in the high-side reading. In FIG. 7, the vertical axis represents the output of the memory cell,
A graph of V _EQ when the horizontal axis is time is shown,
The solid line in the figure indicates V _EQ = HV _CC , and the dotted line indicates V _EQ = ΔV _C (C _B
/ C _S +1) respectively.

[0045] This is because, if the loss charge due to natural discharge and Q _L, when the _{V EQ = HV CC, Q L} <V CC C S / 2-Δ
While V _C (C _S + C _B ), V _EQ = ΔV _C (C
_B / C _S +1) _{when, Q L <V CC C S} -2ΔV C (C
_S + C _B ), and in the latter case, it can be understood that about twice the spontaneous discharge can be tolerated.

As described above, even if the precharge level on the bit line side is lower than HV _{CC, the} precharge level of the sense amplifier 56 can be set to HV _{CC in} the present embodiment, so there is no problem in the sensing operation.

Further, in the conventional example of FIG. 9, the bit lines BL,
Since -BL and the sense amplifier 62 were directly connected, the actual cell output was reduced by the sense amplifier capacitance, but in the present embodiment, the sense amplifier 56 and the bit line B
L, -BL the sense amplifier capacity because it has been connected through the transistor P _1, P ₂ can be ignored.

Since there is another problem of noise in the value of V _EQ , it is desirable to make it about 20% larger than ΔV _C (C _B / C _S +1), and in reality there are circuit variations. , ΔV _C (C _B / C _S +1) <V _EQ <ΔV _C (C
_{The range of B} / C _S +1) × 1.4 is considered to be a practical value.

FIG. 8 shows another embodiment of the semiconductor memory device in which the sense amplifier is precharged by HV _CC precharge. In this embodiment, the circuit is omitted as compared with the embodiment shown in FIG. That is, in the embodiment shown in FIG. 6, the equalizer for HV _CC and the equalizer for V _EQ are provided separately, but in FIG. 8, two transfer gates TG _{1 are used.}
It is collected as one by making it TG ₂ .

That is, in this embodiment, the equalizer 50,
In addition to the memory cell array 52, the transfer gate 70 for inputting the gate signal TG ₁ and the selection output SEQ make it H
It is composed of an equalizing potential supply circuit 76 for supplying either V _CC or V _EQ to the equalizing 72 and a sense amplifier 74.

As a result, TG ₁ is High, TG ₂ is Low, and SE is equal during the equalizing period of the bit lines BL and -BL.
This is performed when Q is Low and EQ ₂ is High. Further, TG ₁ is Lo during the equalizing period of the sense amplifier 74.
w, TG ₂ is High, SEQ is High, EQ ₂ is H
It becomes high. As described above, also in this embodiment, it is possible to precharge different potentials.

In the present embodiment, the sense amplifier 74 also has two P-channel transistors omitted as compared with the sense amplifier 56 (FIG. 6), but it is almost the same except for the increase of the through current during the sensing operation. The operation of can be performed.

FIG. 12 shows a semiconductor memory device having both advantages shown in these embodiments by combining the embodiment shown in FIG. 2 and the embodiment shown in FIG. The description in the same figure is omitted because it overlaps with the description already given, but by combining in this way, it is possible to provide a highly reliable semiconductor memory device even when the semiconductor memory device is highly integrated. Becomes Although FIG. 12 shows an example in which FIG. 2 and FIG. 6 are combined, it is of course possible to combine FIG. 2 and FIG.

[0054]

As described above, according to the semiconductor memory device of the present invention having the feature of the word line driving section, the word line jump wirings are used in a time division manner so that the word line drivers can be arranged freely and the adjacent words can be arranged. Since the line driver interval can be increased, the driving force of the word line driver can be increased. Further, it becomes possible to connect a plurality of word line drivers to one word line, and the word line driving force can be further increased.

Further, according to the semiconductor memory device of the present invention which performs HV _CC precharge, the hold time defect is greatly increased by setting the precharge level of the bit line to ΔV _C (C _B / C _S +1). The precharge level of the sense amplifier can be maintained at HV _CC .
Therefore, since the bit line capacitance and the sense amplifier capacitance are completely cut off without lowering the sense speed, the effective bit line capacitance is reduced and the memory cell output is increased, so that a more stable operation of the semiconductor memory device is possible. Can be obtained.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing an embodiment of a semiconductor memory device having a feature of a word line driver according to the present invention;

FIG. 2 is a circuit diagram showing details of the semiconductor memory device shown in FIG.

FIG. 3 is a block diagram showing a conventional technique of a semiconductor memory device having a word line driving section;

FIG. 4 is an operation waveform diagram showing an example of operation in the embodiment of FIG.

5 is an operation waveform diagram of the conventional technique shown in FIG.

FIG. 6 is a circuit diagram showing an embodiment of an HV _CC precharge type semiconductor memory device according to the present invention;

7 is an explanatory diagram showing the relationship between memory cell output and spontaneous discharge in the embodiment of FIG.

FIG. 8 is a circuit diagram showing another embodiment of the semiconductor memory device which performs the HV _CC precharge method according to the present invention;

FIG. 9 is a circuit diagram of a semiconductor memory device that performs an HV _CC precharge method in the related art;

FIG. 10 is an explanatory diagram showing the relationship between the sense time and the equalizer voltage V _EQ in reading “0” or “1”;

FIG. 11 is an explanatory diagram showing the relationship between the storage potential V _m and the time during which the storage potential V _m is lost.

12 is an embodiment of a semiconductor memory device according to the present invention, which is a combination of the embodiment shown in FIG. 2 and the embodiment shown in FIG.

[Explanation of symbols]

 10A, 10B Word line driver 12A, 12B Word line driver power supply 14-1, 14-2 Memory cell 16 Equalizer 18 Sense amplifier 20 Column decoder 22 Column block decoder WL Word line WLJ Word line jump wiring 50, 54, 58, 72 Equalizer 52 memory cell array 56,74 sense amplifier 60,70 transfer gate 76 equalize potential supply circuit

Claims (5)

[Claims] 1. A semiconductor memory having a word line driver for supplying a potential boosted by a word line driver power supply to a word line selected by a row decoder, and selecting a memory cell corresponding to an address signal input from the driver. In the device, the word line driver and the row decoder are connected via a word line jump wiring, and the word line jump wiring is connected to the word line via a switch controlled by column-side information in the address signal. The word line driver is notified of the selected output from the row decoder, and the word line driver output is transmitted to the word line via the switch, and the row decoder is arranged on one side of the memory cell. The word line The drivers are arranged on the row decoder side and the opposite side so as to be arranged substantially on both sides of the memory cell, and the word line driver arranged on the opposite side of the row decoder is formed by the word line jump wiring. A semiconductor memory device connected to the row decoder. 2. A semiconductor memory device for precharging HV _CC to a sense amplifier, comprising: first equalizing means for precharging a bit line side precharge level at a precharge level V _EQ lower than HV _CC; Second equalizing means for setting the precharge level of HV _CC to HV _CC , and precharging the bit line side and the sense amplifier by the first and second precharging means. Semiconductor memory device. 3. A semiconductor memory device for precharging HV _CC to a sense amplifier, wherein an HV _CC precharge level and a precharge level V _EQ lower than the HV _CC precharge level are input and these precharge levels are input according to a selection signal. A precharge potential output unit for outputting any of the above, an equalizer unit for inputting the precharge potential output from the precharge potential output unit and precharging the bit line in accordance with the equalize signal, and a first transfer gate. A second transfer gate, the precharge potential output means, the equalizing means, the first
Of the semiconductor memory device, wherein the bit line side is precharged by a precharge level V _EQ and the sense amplifier is precharged by HV _CC by the transfer gate and the second transfer gate. 4. The semiconductor memory device according to claim 2, wherein when the sense amplifier sensitivity ΔV _C , the bit line capacitance C _B , and the memory cell capacitance C _S , the precharge level V _EQ is ΔV _C (C _B / C _S +1),
A semiconductor memory device having a value smaller than ΔV _C (C _B / C _S +1) × 1.4. 5. A HV _CC having a word line driver for supplying a potential boosted by a word line driver power supply to a word line selected by a row decoder and selecting a memory cell corresponding to an address signal input by this driver. In a semiconductor memory device in which a word line driver and the row decoder are connected via a word line jump wiring, and the word line jump wiring is controlled by information on the column side in the address signal. The row decoder is connected to the word line through a switch, notifies the word line driver of a selection output from the row decoder, and transmits the word line driver output to the word line through the switch. The memory cell The word line drivers are arranged on one side and on the opposite side of the row decoder so as to be substantially arranged on both sides of the memory cell, and the word line drivers are arranged on the opposite side of the row decoder. the word line driver are connected by the word line jump wiring, precharging the precharge level of the bit line side with precharged at HV _CC lower precharge level V _EQ, the precharge level of the sense amplifier to the HV _CC A semiconductor memory device comprising: