JPH0529545A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor integrated circuit device of small delay which can be appropriated, to a plurality of kinds of application environments also after manufacture is completed, and has a small number of input terminals. CONSTITUTION:An input circuit is provided with a plurality of bonding pads BPa, BPb. One bonding pad out of a plurality of the bonding pads is connected with a pin of a package mounting a semiconductor chip, and a signal is inputted from outside. In response to the input signal to the bonding pad, a corresponding active element (a transistor 2a or 2b) operates switching, and the input signal to the bonding pad is delivered to an ECL circuit 10. An active element (the transistor 2b or 2a) corresponding with a bonding pad in an open state is in an OFF state, and the ECL circuit 10 is electrically disconnected from the bonding pad.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device capable of selecting a specific input terminal from a plurality of input terminals in accordance with a use environment. ..

[0002]

2. Description of the Related Art Conventionally, a manufacturer of semiconductor integrated circuit devices needs to prepare a plurality of types of semiconductor integrated circuit devices according to the environment in which they are used, even if they have the same function. One of the reasons for this is that there are a plurality of types of packages on which semiconductor chips are mounted, for example.

Two typical types of packages are shown in FIGS. 5 and 6. Package PA1 shown in FIG.
Is called DIP, and the input / output pins are arranged along the long side thereof. Therefore, in the semiconductor chip SC1 mounted on such a package PA1, the input terminals, that is, the bonding pads, must be arranged along the long sides thereof so as to match the pin arrangement of the package. On the other hand, the package PA2 shown in FIG.
It is called a flat package, and the input / output pins are arranged along the short side. Therefore, the semiconductor chip SC2 mounted in such a package PA2
Must have bonding pads arranged along their short sides to match the pin arrangement of the package PA2. As described above, the manufacturer must prepare a plurality of types of semiconductor integrated circuit devices according to the type of package on which the semiconductor chip is mounted.

It is a heavy burden on the manufacturer side to manufacture a plurality of types of semiconductor integrated circuit devices despite having the same function. For example, each type of semiconductor integrated circuit device must be individually designed, and a production line must be provided for each type of semiconductor integrated circuit device. These impede the reduction of the product price due to mass production and provide the user with an expensive product. Therefore, manufacturers are required to be able to develop and manufacture a wide variety of products with a minimum of labor.

In order to meet the above requirements, in a recent semiconductor integrated circuit device, a plurality of types of bonding pads are arranged on a semiconductor chip, and an input circuit in the semiconductor integrated circuit device is arranged according to the environment in which it is used. There is one that switches the connection relationship between the bonding pad and the bonding pad. For example, as shown in FIG. 7, a bonding pad BP1 compatible with DIP and a bonding pad BP2 compatible with a flat package are provided on the semiconductor chip SC3. When the semiconductor chip SC3 is mounted on the DIP, the input circuit and the bonding pad BP1
When the semiconductor chip SC3 is mounted on a flat package, the input circuit and the bonding pad B are connected.
P2 is connected. As a result, one semiconductor integrated circuit device can be used in a plurality of environments, and the burden on the maker side and the user side due to an increase in product types can be reduced.

Conventionally, as a method of switching the connection relationship between the input circuit of the semiconductor integrated circuit device and the bonding pad, a method as shown in FIG. 8 or 9 has been adopted.

In the method shown in FIG. 8, the connection relationship between a plurality of types of bonding pads BP1 to BPn and the input circuit 1 is
This is switched in the wiring process. This method is called master slice.

In the method shown in FIG. 9, switches such as transfer gates TG1 to TGn are inserted between a plurality of types of bonding pads BP1 to BPn and the input circuit 1, and the bonding pads and the input circuit 1 are turned on / off. The connection relation of is switched. In this method, switching of the transfer gates TG1 to TGn is controlled by a switching control signal externally applied to another bonding pad BPC. Therefore, this method is called the Bonding option.

FIG. 10 is a circuit diagram showing an example of the configuration of the input circuit 1 shown in FIG. 8 or 9. The input circuit shown in FIG. 10 includes an ECL (emitter coupled logic) circuit 10. The ECL circuit 10 includes resistors 12 and 1
3, NPN bipolar transistors 14 and 15, and a constant current source 16. The resistor 12 is inserted between the power supply 11 and the collector of the transistor 14. Resistance 1
3 is inserted between the power supply 11 and the collector of the transistor 15. The emitters of the transistors 14 and 15 are commonly connected to the constant current source 16. A reference voltage is applied to the base of the transistor 15 via the terminal 17. This reference voltage is selected as an intermediate potential between the H level and the L level used in the ECL circuit. In front of the ECL circuit 10, the input transistor 2 and the constant current source 3 which are NPN bipolar transistors are provided.
Is provided. The collector of the transistor 2 is connected to the power supply 11. The emitter of transistor 2 is
It is connected to the constant current source 3 and also to the base of the transistor 14. The base of the transistor 2 is
It is connected to the bond pad selected by the master slice or bonding option.

Next, the operation of the input circuit shown in FIG. 10 will be described. A signal externally applied to a bonding pad (not shown) is input to the base of the transistor 2.
The transistor 2 adjusts the signal input to the bonding pad to a level easy to use in the ECL circuit, and then transmits the signal to the base of the transistor 14. When the input signal given to the transistor 14 is at H level, the transistor 1
4 is turned on. Therefore, power supply 11 → resistor 12 →
Collector / emitter of transistor 14 → constant current source 16
A current path that flows is formed, and the transistor 15 is turned off. At this time, from the output node N1 provided at the collector of the transistor 14, an L level internal signal /
A is obtained, and an H-level internal signal A is obtained from the output node N2 provided at the collector of the transistor 15. These complementary internal signals / A and A are applied to a predetermined circuit (not shown) formed inside the semiconductor integrated circuit device. On the other hand, when the input signal applied to the base of the transistor 14 is L level, the transistor 14 is turned off. Therefore, a current path that flows from the power supply 11 → the resistor 13 → the collector / emitter of the transistor 15 → the constant current source 16 is formed. At this time, an H level internal signal / A is obtained from the output node N1, and the output node N2
From, an L-level internal signal A is obtained.

FIG. 11 is a circuit diagram showing another structure of the input circuit 1 shown in FIG. 8 or 9. The input circuit shown in FIG. 11 includes a CMOS inverter 20. The CMOS inverter 20 includes a P-channel MOS transistor 22.
And an N-channel MOS transistor 23. The source of the transistor 22 is connected to the power supply 21. The drain of the transistor 22 is
Connected to the drain of. The source of the transistor 23 is connected to the ground 24. The gates of transistors 22 and 23 are connected to the bond slice selected by the master slice or bonding option described above.

Next, the operation of the input circuit shown in FIG. 11 will be described. When the input signal externally applied to the bonding pad (not shown) is at the H level, the transistor 22 is turned off and the transistor 23 is turned on.
Therefore, the internal signal / A obtained from the output node N3 provided at the connection point between the transistors 22 and 23 is L
It becomes a level. On the other hand, when the input signal applied to the bonding pad is L level, the transistor 22 is turned on and the transistor 23 is turned off. Therefore, H level internal signal / A is obtained from output node N3. In this way, from the output node N3, the internal signal / A obtained by inverting the input signal applied to the bonding pad is obtained. This internal signal / A is applied to a predetermined circuit (not shown) formed inside the semiconductor integrated circuit device.

[0013]

When the switching of the bonding pads is realized by the mask option, that is, the master slice method as shown in FIG. 8, various problems occur. The first problem is that in the master slice method, since switching is performed in the wiring process, a plurality of sets of masks for manufacturing are required for the same process, resulting in high design and manufacturing costs. The second problem is that it cannot be diverted to another usage environment after manufacturing is completed.

On the other hand, when the bonding pad is switched by the bonding option as shown in FIG. 9, there is an advantage that it can be diverted to another usage environment even after the manufacturing is completed. However, in the bonding option, since the transfer gate is inserted in series in the signal input path from the bonding pad to the input circuit 1, the transfer of the input signal is delayed due to the internal resistance and parasitic capacitance of the transfer gate. There is a problem. In the bonding option method,
There is a problem in that a bonding pad BPC for inputting a switching control signal to each transfer gate is separately required, and the number of bonding pads on the semiconductor chip increases.

In order to solve the above problems in the bonding option system, a method of directly connecting a plurality of bonding pads BP1 to BPn to one input circuit 1 can be considered. However, in such a method, each bonding pad itself becomes a large capacitive load and is connected to the input circuit 1. Therefore, also in this case, there is a problem that the delay time increases and the load capacitance increases when viewed from the outside. Occurs.

Therefore, an object of the present invention is to provide a semiconductor integrated circuit device which can be diverted to a plurality of use environments even after completion of manufacturing, has a small delay, and does not require a bonding pad for inputting a switching control signal. Is to provide.

[0017]

A semiconductor integrated circuit device according to the present invention has a plurality of input terminals and operates in response to signals externally input to these input terminals. Further, the semiconductor integrated circuit device of the present invention includes an input circuit connected to the plurality of input terminals, generating an internal signal, and outputting the internal signal from the output node. The input circuit includes a plurality of active elements provided for each of the connected input terminals. Each active element becomes non-conductive when no signal is input to the corresponding input terminal, electrically disconnects the input node from which no signal is input and the output node, and connects to the corresponding input terminal. When a signal is input, switching operation is performed in response to this signal. The input circuit creates an internal signal based on the signal transmitted by the switching operation of the active element.

[0018]

In the present invention, of the plurality of active elements included in the input circuit, only the active element corresponding to the input terminal to which the signal is input performs the switching operation. Then, an internal signal is created based on the signal transmitted by the switching operation of the active element. On the other hand, the active element corresponding to the input terminal to which no signal is input is in a non-conducting state, and electrically cuts off between the input terminal to which no signal is input and the output node. As described above, in the present invention, the switching and selection of the bonding pads are automatically performed, and it is not necessary to control the switching and selection of the bonding pads from the outside. for that reason,
There is no need to provide a bonding pad for introducing the switching control signal unlike the conventional semiconductor integrated circuit device adopting the bonding option method. Further, the semiconductor integrated circuit device of the present invention can be diverted to a plurality of types of usage environments even after the manufacturing is completed. Further, since the corresponding active element electrically cuts off between the input terminal to which no signal is input and the output node of the input circuit, the capacitive load of the non-selected bonding pad is connected to the input circuit. Not done. As a result, the delay in the operation of the input circuit due to the increase in capacitance is reduced.

[0019]

1 is a circuit diagram showing the configuration of an input circuit portion in a semiconductor integrated circuit device according to an embodiment of the present invention. In the embodiment shown in FIG. 1, the ECL circuit 10 generates the internal signals / A and A. The configuration of the ECL circuit 10 is similar to that of the ECL circuit 10 shown in FIG. In the embodiment shown in FIG. 1, two types of bonding pads are arranged on the semiconductor chip in order to adapt to at least two types of use environments. Therefore, ECL
The circuit 10 has two bonding pads BPa and BPb.
Internal signal based on the signal input to either
A and A are generated. The bonding pad BPa is, for example, a DIP bonding pad, and the bonding pad BPb is, for example, a flat package bonding pad. Bonding pad BPa is connected to the base of the corresponding input transistor, that is, NPN bipolar transistor 2a. Bonding pad BPb is connected to the corresponding input transistor, that is, the base of NPN bipolar transistor 2b. Each collector of the transistors 2a and 2b is connected to the power supply 11. The emitters of the transistors 2a and 2b are commonly connected to the constant current source 3, and
It is connected to the base of the transistor 14 in the ECL circuit 10. That is, in the embodiment shown in FIG. 1, the emitter outputs of the transistors 2a and 2b are wired-ORed and then input to the ECL circuit 10.

Next, the operation of the embodiment shown in FIG. 1 will be described. Now, it is assumed that the bonding pad BPa is connected to a pin having a package (not shown) on which a semiconductor chip is mounted and the bonding pad BPb is in an open state. In this case, the transistor 2b is completely off because there is no path for supplying the base current. On the other hand, transistor 2a performs a switching operation in response to a signal externally input to bonding pad BPa. Therefore, a signal obtained by level-shifting the input signal of the bonding pad BPa by the base-emitter voltage (about 0.8 V) of the transistor 2a is input to the base of the transistor 14 in the ECL circuit 10. Therefore, the ECL circuit 10 has the bonding pad BP.
It operates in response to the input signal of a and generates internal signals / A and A corresponding to the input signal.

Contrary to the above, the bonding pad BPb
Is connected to a pin on the package and the bonding pad BPa is open, the transistor 2a
Is completely turned off, and the transistor 2b performs the switching operation in response to the input signal of the bonding pad BPb. Therefore, the ECL circuit 10 operates in response to the input signal of the bonding pad BPb,
Internal signals / A and A corresponding to this input signal are generated.

The operation of the ECL circuit 10 is exactly the same as that of the ECL circuit 10 shown in FIG. 10, and the description thereof will be omitted.

As described above, in the embodiment shown in FIG. 1, the bonding pads can be automatically switched without receiving any control from the outside. That is, the bonding pad in the open state is electrically separated from the ECL circuit 10, and only the input signal of the bonding pad connected to the pin of the package is given to the ECL circuit 10. As a result, the capacitive load of the unused bonding pad is disconnected from the input circuit, and the operation delay due to the increase in load capacitance is reduced. Further, since it is not necessary to introduce the switching control signal from the outside, the bonding pad BP for inputting the switching control signal as shown in FIG.
It is not necessary to provide C. As a result, the number of bonding pads on the semiconductor chip does not increase, and the size of the semiconductor chip can be reduced. Furthermore, the embodiment shown in FIG. 1 can be adapted to a plurality of types of use environments even after the completion of manufacturing by changing the bonding pads connected to the pins of the package.

Preferably, as shown by a dotted line in FIG. 1, a high resistance element Ra is provided between the base of the transistor 2a and the ground, and a high resistance element Rb is provided between the base of the transistor 2b and the ground. You may do it. These high resistance elements Ra and Rb serve to stabilize the base potential of the corresponding transistor 2a or 2b to the ground potential when the bonding pad BPa or BPb is in the open state.

Although the embodiment shown in FIG. 1 shows the case where two kinds of bonding pads are provided for one input circuit, it is possible to provide more bonding pads for one input circuit. is there. In this case, the number of input transistors corresponding to the increased number of bonding pads may be provided in parallel with the transistors 2a and 2b.

FIG. 2 is a circuit diagram showing a structure of an input circuit portion in a semiconductor integrated circuit device according to another embodiment of the present invention. In the embodiment shown in FIG. 1, the ECL circuit 10 is provided after the emitter outputs of the transistors 2a and 2b are wired-OR.
However, in the embodiment shown in FIG. 2, the emitter outputs of the transistors 2a and 2b are independently EC.
It is input to the L circuit 10 '. Therefore, in the ECL circuit 10 ', two sets of NPN bipolar transistors 14a, 1 are provided between the output node N1 and the constant current source 16.
4b are provided in parallel. The emitter output of the transistor 2a is given to the base of the transistor 14a. The emitter output of the transistor 2b is given to the base of the transistor 14b. The other structure of the ECL circuit 10 'is the same as that of the ECL circuit 10 shown in FIG. 1, and the corresponding portions bear the same reference numerals. Further, the transistors 2a and 2b are individually provided with constant current sources 3a and 3b, respectively. The constant current source 3a is connected to the emitter of the transistor 2a. The constant current source 3b is connected to the emitter of the transistor 2b.

Next, the operation of the embodiment shown in FIG. 2 will be described. It is now assumed that the bonding pad BPa is connected to a pin on the package and the bonding pad BPb is in an open state. In this case, since the transistor 2b has no path for supplying the base current, it is completely off. Therefore, the base potential of the transistor 14b has dropped to the L level, and the transistor 14b is completely off. On the other hand, the transistor 2a performs a switching operation in response to a signal externally input to the bonding pad BPa. Therefore,
A signal obtained by level-shifting the input signal of the bonding pad BPa by the base-emitter voltage of the transistor 2a is applied to the base of the transistor 14a. In this case, the ECL circuit 10 'includes the resistors 12 and 13, the transistors 14a and 15 and the constant current source 16 in FIG.
An ECL circuit equivalent to the ECL circuit 10 shown in is formed. The ECL circuit operates in response to an input signal to bonding pad BPa and generates internal signals / A and A corresponding to the input signal.

Contrary to the above, the bonding pad BPb
Is connected to a certain pin of the package and the bonding pad BPa is open, the transistor 2a is completely turned off, and the transistor 2b performs a switching operation in response to the input signal of the bonding pad BPb. Therefore, in the ECL circuit 10 ', the transistor 14a is turned off, and the resistors 12, 13 and
The transistors 14b and 15 and the constant current source 16 form an ECL circuit equivalent to the ECL circuit 10 shown in FIG. This ECL circuit operates in response to an input signal to bonding pad BPb and generates internal signals / A and A corresponding to this input signal.

The embodiment shown in FIG. 2 also has the same effect as the embodiment shown in FIG. If the number of bonding pads provided for one input circuit increases,
Transistor 2a, constant current source 3a, transistor 14a
(Or, a circuit equivalent to the circuit formed by the transistor 2b, the constant current source 3b, and the transistor 14b) may be increased by the number of sets corresponding to the increased number of bonding pads.

FIG. 3 is a circuit diagram showing a structure of an input circuit portion in a semiconductor integrated circuit device according to still another embodiment of the present invention. In the embodiment shown in FIG. 3, the internal signal / A is generated by the CMOS inverter. The input circuit shown in FIG. 3 has P-channel MOS transistors 22a and 22b.
And N-channel MOS transistors 23a and 23b,
High resistance elements 25a and 25b are included. Transistor 22
a and 22b are inserted in parallel between the power supply 21 and the output node N3. The transistors 23a and 23b are inserted in series between the output node N3 and the ground 24. The respective gates of the transistors 22a and 23a are connected to the bonding pad BPa and also connected to the power supply 21 via the high resistance element 25a. Each gate of the transistors 22b and 23b has a bonding pad B
It is connected to Pb and is also connected to the power supply 21 via the high resistance element 25b.

Next, the operation of the embodiment shown in FIG. 3 will be described. First, the operation when the bonding pad BPa is connected to a certain pin of the package and the bonding pad BPb is in an open state will be described. In this case, the potentials of the gates of the transistors 22b and 23b are the same as those of the high resistance element 25.
It is raised to the power supply potential via b. Therefore, the transistor 22b is off and the transistor 23b is on. At this time, the transistors 22a, 2
3a forms a CMOS inverter that operates in response to an input signal of the bonding pad BPa. The transistor 23b forms a simple current path between the CMOS inverter and the ground 24. When the input signal to the bonding pad BPa is at H level, the transistor 22a is turned off and the transistor 23a is turned on. Therefore, an L level internal signal / A is obtained from output node N3. On the contrary, the bonding pad BP
When the input signal to a is at L level, the transistor 22a
Is on and the transistor 23a is off. Therefore, from the output node N3, an H level internal signal /
A is obtained.

Contrary to the above, the bonding pad BPb
Is connected to a pin on the package and the bonding pad BPa is open, the transistors 22a, 2a
Each gate potential of 3a becomes a power supply potential. Therefore, the transistor 22a is turned off and the transistor 23a is turned on. At this time, the transistors 22b and 23b
Form a CMOS inverter that operates in response to an input signal to the bonding pad BPb. The transistor 23a includes the transistor 22b and the transistor 23.
It simply forms a current path with b. When the input signal to the bonding pad BPb is at H level, the transistor 22b is turned off and the transistor 23b is turned on. Therefore, an L level internal signal / A is obtained from output node N3. On the other hand, the bonding pad BPb
When the input signal to is at L level, the transistor 22b is turned on and the transistor 23b is turned off. Therefore, H level internal signal / A is obtained from output node N3.

As described above, the embodiment shown in FIG.
Similarly to the embodiment shown in FIG. 2, only the bonding pad to which a signal is input is automatically selected without being controlled by the outside. The open bonding pad is completely cut off from the output path of the internal signal. Therefore, the embodiment shown in FIG.
The effect is exactly the same as that of the embodiment shown in FIG.

In the embodiment shown in FIG. 3, two bonding pads are provided for one input circuit, but when a larger number of bonding pads are provided for one input circuit, Depending on the number of bonding pads to be added, the number of P-channel MOS transistors inserted in parallel between power supply 21 and output node N3 and N inserted in series between output node N3 and ground 24.
The number of channel MOS transistors should be increased.

FIG. 4 is a circuit diagram showing a structure of an input circuit portion in a semiconductor integrated circuit device according to still another embodiment of the present invention. The embodiment shown in FIG. 4 is similar to the embodiment shown in FIG.
Is occurring. The input circuit of the embodiment shown in FIG. 4 includes P-channel MOS transistors 22a and 22b, N-channel MOS transistors 23a and 23b, and a high resistance element 2.
5a and 25b are included. Transistors 22b and 22a
Are inserted in series between the power supply 21 and the output node N3. The transistors 23a and 23b are connected to the output node N
3 and the ground 24 are inserted in parallel. The gates of the transistors 22a and 23a are connected to the bonding pad BPa and also connected to the ground 24 via the high resistance element 25a. Transistors 22b and 2
Each gate of 3b is connected to the bonding pad BPb and is also connected to the ground 24 through the high resistance element 25b.

Next, the operation of the embodiment shown in FIG. 4 will be described. First, when the bonding pad BPa is connected to a pin on the package and the bonding pad BPb is open, the gate potentials of the transistors 22b and 23b are lowered to the ground potential via the high resistance element 25b. Therefore, the transistor 22b is on and the transistor 23b is off. At this time, the transistors 22a and 23a are connected to the bonding pad BPa.
Form a CMOS inverter that operates in response to an input signal to the. The transistor 22b forms a simple current path between the CMOS inverter and the power supply 21. The CMOS inverter formed by the transistor 22a and the transistor 23a has a bonding pad BP.
It operates in response to an input signal to a, and outputs an internal signal / A which is an inverted signal of the input signal from the output node N3.

On the other hand, the bonding pad BPb is connected to a pin on the package, and the bonding pad BPa
Is open, the gate potentials of the transistors 22a and 23a are lowered to the ground potential via the high resistance element 25a. Therefore, the transistor 22a is turned on and the transistor 23a is turned off. At this time,
With the transistor 22b and the transistor 23b,
A CMOS inverter that operates in response to an input signal to bonding pad BPb is formed. Transistor 2
2a forms a mere current path between the transistor 22b and the transistor 23b. The CMOS inverter formed by the transistor 22b and the transistor 23b operates in response to the input signal to the bonding pad BPb, and outputs the internal signal / A which is the inverted signal of the input signal from the output node N3.

As described above, in the embodiment shown in FIG. 4, only the bonding pad to which a signal is input is selected without receiving any control from the outside, and the other bonding pads and the output path of the internal signal are selected. Electrically cut off the space. Therefore, the embodiment shown in FIG. 4 has the same effect as the embodiment shown in FIGS.

In the embodiment shown in FIG. 4, two bonding pads are provided for one input circuit, but when a larger number of bonding pads are provided for one input circuit, Power supply 21 and output node N3
If the number of P-channel MOS transistors inserted in series between and and the number of N-channel MOS transistors inserted in parallel between the output node N3 and the ground 24 are increased by the number corresponding to the increased number of bonding pads. Good.

[0040]

As described above, according to the present invention, it is possible to divert to a plurality of types of use environments even after the completion of manufacturing.
Further, the bonding pad connected to the input circuit can be automatically selected, and there is no need to input a switching control signal from the outside. Therefore, the number of input terminals on the semiconductor chip can be reduced. Further, since the input terminal to which no signal is input is electrically cut off from the output node of the input circuit, the load capacitance connected to the input circuit is reduced and the delay is reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of another embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of still another embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of still another embodiment of the present invention.

FIG. 5 is a diagram showing an example of a package in which a semiconductor integrated circuit device is mounted.

FIG. 6 is a diagram showing another example of a package in which a semiconductor integrated circuit device is mounted.

FIG. 7 is a diagram showing an arrangement example of bonding pads of a semiconductor chip for supporting a plurality of types of packages.

FIG. 8 is a schematic diagram for explaining a method of switching semiconductor integrated circuit devices by a master slice method.

FIG. 9 is a schematic diagram for explaining a method of switching a semiconductor integrated circuit device by a bonding option.

FIG. 10 is a circuit diagram showing an example of a configuration of an input circuit in a semiconductor integrated circuit device.

FIG. 11 is a circuit diagram showing another example of the input circuit in the semiconductor integrated circuit device.

[Explanation of symbols]

10, 10 ': ECL circuit 2a, 2b, 14, 14a, 14b, 15: NPN bipolar transistor 12, 13, 25a, 25b, Ra, Rb: High resistance element 11,21: Power supply 3,3a, 3b, 16: Constant current source 17: Terminals for inputting reference voltage N1 to N3: Output nodes BPa, BPb: Bonding pads 22a, 22b: P-channel MOS transistors 23a, 23b: N-channel MOS transistors

Claims (1)

Claim: What is claimed is: 1. A semiconductor integrated circuit device having a plurality of input terminals, which operates in response to a signal input to the input terminals from the outside, the connection being made to the plurality of input terminals. And generate an internal signal,
An input circuit for outputting the internal signal from an output node is provided, the input circuit includes a plurality of active elements provided for each of the connected input terminals, and each active element corresponds to the corresponding When a signal is not input to the input terminal, it is in a non-conducting state and electrically cuts off between the input terminal to which no signal is input and the output node, and the signal is input to the corresponding input terminal. In this case, the semiconductor integrated circuit device performs a switching operation in response to the signal, and the input circuit creates the internal signal based on a signal transmitted by the switching operation of the active element.