JPH05292537A - Offset cancel circuit - Google Patents

Abstract

PURPOSE:To correct an offset (the deviation of a reference level) of an input signal having plural color components. CONSTITUTION:Detecting circuits 26R, 26G, an 26B detect color data of respective color components from data of the digitally converted input signal, Integrating circuits 28R, 28G, and 28B integrate these detected color data to calculate the average value. An addition/subtraction circuit 32 subtracts the average value of color data from data of the input signal. Thus, an offset cancel circuit 1 eliminates the offset component included in the input signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an offset cancel circuit for correcting a difference in reference level of a video signal having a plurality of color components, for example, offset cancel suitable for use in a video device such as a digital electronic still camera. Regarding the circuit.

[0002]

2. Description of the Related Art In recent years, image equipment such as a digital electronic still camera has been developed which converts an image into an electric signal by an image pickup element such as a solid-state image pickup element and stores it in a memory card.

The video signal input to the circuit from the solid-state image pickup device of such a video device is, for example, an analog video signal such as an RGB signal obtained through a color filter on the image pickup cell array. The color signals of the R signal, G signal, and B signal are dot-sequentially input to each channel of the circuit, subjected to signal processing such as level adjustment and clamping, and converted into digital data by an A / D converter. Especially, the high-precision circuit of this A / D converter is very expensive.
It has been performed that each color signal is converted into a single line and the single A / D converter sequentially converts the single color signal into digital data.

The obtained digital data is then subjected to digital image processing such as gamma correction, and finally stored in a memory card. As is well known, this gamma correction is to correct the difference between the input characteristics of the video input system and the display characteristics of the display device such as CRT included in the video output system. The lever correction process is performed. The gamma curve representing the characteristics of this correction processing is set so that the amplification factor becomes high especially in the region where the level of the input signal is low, that is, in the low luminance region.

[0005]

However, in the conventional circuit mounted on the digital electronic still camera as described above, the reference level between the signals of each color of the RGB signal is changed due to the variation of the elements of each channel of RGB in the circuit system. (Offset) occurs. The linearized video signals of each color component are digitized by the A / D converter while their reference levels are deviated. Then, gamma correction is applied to this digital data. At this time, since the gamma correction processing is performed on the data having the shifted reference level, this offset is amplified together with the signal and is superimposed on the regular color signal as the color shift data. In particular, this color shift data is remarkably generated in the data of the low luminance region where the amplification factor (gamma gain) of gamma correction is high. This allows
This caused deterioration of color reproducibility of low-luminance images. To prevent this color misregistration from occurring, RGB for each channel
Offset adjustment is performed to match the signal reference level. However, this offset adjustment needs to be performed accurately, and it is required that the variation with time is small, and moreover, this adjustment is performed manually.

It is an object of the present invention to solve the problems of the prior art and to provide an offset cancel circuit which does not require manual and highly accurate adjustment.

[0007]

In order to solve the above-mentioned problems, the present invention provides an offset cancel circuit for correcting the difference in reference level of a video signal having a plurality of color components. A detection unit for extracting data for each color component from the image data, an average calculation unit for calculating an average value of the clamp levels of the data for each color component, and a correction for receiving the video signal and correcting the offset of the video signal based on the average value. And means.

Further, the correction means may include a calculation means for subtracting the average value from the video signal data.

Further, the correction means generates amplification means for correcting the DC level of the video signal of the corresponding color component according to the DC voltage corresponding to the control input, and correction data for correcting the offset from the average value. Correction data generating means, conversion means for converting the correction data into an analog voltage, and feedback means for feeding back the analog voltage to the control input of the amplifying means as a DC voltage.

Further, the circuit may include a multiplexing means for converting the video signals amplified by the plurality of amplifying means into one line.

Further, this circuit is preferably provided with a digital converting means for converting the video signal linearized by the multiplexing means into digital data.

[0012]

According to the offset cancel circuit of the present invention,
A plurality of video signals are converted into a single line and digitized. next,
Digital data including an offset component is extracted for each color component, and an average value of the clamp level of the data is calculated for each of the extracted data. The offset is corrected based on the average value of this clamp level.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of an offset cancel circuit according to the present invention will now be described in detail with reference to the accompanying drawings. 1 and 2 show the configuration of an embodiment of a digital electronic still camera to which an offset cancel circuit 1 according to the present invention is applied. Referring to FIGS. 1 and 2, the offset cancel circuit 1 multiplexes a video signal, which is picked up by the image pickup input circuit 12 and output as an RGB signal of three primary color signals, by a multiplexer 14 and is multiplexed. This is a circuit that converts the signal into digital data by the A / D converter 22. Then, this circuit detects the offset component included in the obtained digital data by the detection circuit 26 and the integration circuit 2.
8. Cancels each color data by the selector 30 and the adder / subtractor circuit 32, and substantially does not include the offset component R
This is a circuit that generates GB data. The RGB data output from the adder / subtractor circuit 32 is subjected to gamma correction processing in the gamma correction circuit 34, and then subjected to processing such as digital image processing, and finally stored in the memory card. It In the following description, parts not directly related to the present invention will not be shown and described, and the reference numerals of signals will be shown by the reference numbers of the connection lines in which they appear.

The signal generation circuit 10 has a function of supplying various reference signals (not shown) to the respective parts of the digital electronic still camera in synchronization with a free-running reference clock. In particular, the signal generation circuit 10 outputs the color separation pulse SP _R for extracting the R signal representing red at its output 90R and the G signal representing green at its output 90G as shown in FIGS. 3 (B) to 3 (D). color separation pulses SP _G for extracting, has a function of generating each color separation pulses SP _B for extracting the B signal representing the blue output 90B. In addition, the signal generation circuit 10
As shown in FIG. 3 (A), the output 92 has a function of generating a clamp pulse CP which becomes high level in synchronization with the blanking period of the video signal, and a function of generating a clock CK at its output 94. ing.

The image pickup input circuit 12 includes a CCD image pickup device (not shown), and has a function of receiving an image formed on the image pickup surface of the CCD image pickup device through a color filter and converting it into an electric signal. This circuit receives the reference signal from the signal generation circuit 10, generates a transfer clock, supplies it to the CCD image sensor, and drives it.It also reads the RGB signal corresponding to the color filter from the CCD image sensor and outputs it. Amplifies its output 10
It has a function of outputting each color signal of 0R to R signal, output 100G to G signal, and output 100B to B signal to the multiplexer 14 in parallel.

The multiplexer 14 operates from the image pickup input circuit 12
It receives RGB signals in parallel and responds to the color separation pulses SP _R , SP _G and SP _B supplied from the signal generation circuit 24, and inputs them.
It is a circuit that sequentially switches the R signal from 100R, the G signal from input 100G, and the B signal from input 100B to linearly output the RGB signal to its output 102 (time-axis multiplex) and outputs it. This output
One side of 102 is connected to the buffer 18, and the other side is grounded via the capacitor 16. In this way, the multiplexer 14, the capacitor 16 and the buffer 18 sample each color signal by the switch function of the multiplexer 14 in response to the color separation pulses SP _R , SP _G and SP _B , and hold this color signal in the capacitor 16. Then, a sample hold circuit for outputting from the buffer 18 is configured. The output 104 of this buffer 18 is connected to the clamp circuit 20.

The clamp circuit 20 is the output of the buffer 18.
This is a circuit that clamps the RGB signals that are linearized and transferred from 104. The clamp circuit 20 is connected to the A / D converter 22 via its output 106, and has a function of receiving the clamp pulse CP output from the signal generation circuit 24 during the blanking period of the RGB signal and clamping the RGB signal, It has a level shift function for adjusting the pedestal level of the signal input during this clamp period to the input range of the A / D converter 22 connected to the output 106.

The A / D converter 22 is an analog / digital converter that converts the voltage of the analog RGB signal input to its input 106 into digital data. The A / D converter 22 uses the clock CK supplied from the signal generation circuit 10.
In response to the above, the RGB signal is sampled, this value is quantized, and for example, 10-bit digital data is generated and output as RGB data with a quantization level of 1024 levels. The digitized RGB data is output to the addition / subtraction circuit 32 shown in FIG. 1 connected via the bus 110. Further, a bus 112 of, for example, lower 4 bits of this bus 110 is branched from the bus 110 and connected to the detection circuit 26 shown in FIG.

The detection circuit 26R is an RGB circuit appearing on the bus 112.
This is a circuit for detecting R data from data. Detection circuit 26
R has a gate function to output the data of the bus 112 from the output 114R of the 4-bit bus when the clamp pulse CP and the color separation pulse SP _R are both supplied from the signal generation circuit 10. The detection circuit 26R is a circuit that detects the R data in the clamp period and transfers this data to the integration circuit 28 via the output 114R. Similarly, color separation pulses SP _{G and} SP _B are respectively supplied to detect G data and B data, and the integrating circuit 28 is output via outputs 114 G and 114 B, respectively.
There are detection circuits 26G and 26B for transferring to the.

The integrating circuit 28R is a circuit that integrates the R data transferred from the detecting circuit 26R and generates average data representing the average value of these data. The integrating circuit 28R is
The function of integrating the R data of the clamp period input to the input 114R, the function of calculating the average of the R data of the period, and the data of the calculated result until the next clamp pulse CP is input. During the period, the correction data is transferred to the selector 30 via the output 116R of the 4-bit bus. Similarly, the color separation pulses SP _{G and} SP _B are respectively supplied to generate correction data of G data and B data, which are transferred to the selector 30 through the outputs 116G and 116B, respectively. It is equipped.

Selector 30 has inputs 116R, 116G and 116B.
And a color separation pulse SP supplied from the signal generation circuit 10
These inputs and their outputs 11 in response to _R , SP _G and SP _B
It has a bus switching function that switches the connection with 8 in sequence. The output 118 of the 4-bit bus is connected to the adder / subtractor circuit 32.

The adder / subtractor circuit 32 is an arithmetic circuit which has an input 110 and an input 118, calculates data transferred to these inputs, and outputs the result to its output 130. More specifically, the adder / subtractor circuit 32 synchronizes the 10-bit data input to the input 110 with the 4-bit correction data transferred from the selector 30 and input to the input 118, and subtracts them. Prepare As a result, the data is digitally processed and the offset between the RGB color signals is corrected by the correction data, that is, the average value of the reference levels, so that the processing by the gamma correction circuit 34 connected to the output 130 is stably performed. It

The gamma correction circuit 34 is a circuit for correcting the difference between the input characteristic of the image pickup system and the display characteristic of, for example, a CRT. The gamma correction circuit 34 has a function of inputting the data in which the offset between the color signals has been corrected by the adder / subtractor circuit 32 to its input 120 and performing accurate gamma correction on this data. The data that has undergone gamma correction is output 122
Is output to the memory card, and thereafter, various signal processing is performed and finally stored in the memory card.

The operation of the offset cancel circuit 1 in the present embodiment having the above-mentioned structure will be described below with reference to FIG. In the figure, the waveform of each signal in the blanking period of the video signal is shown. First, when the power is turned on, the signal generation circuit 10 outputs the output 90
Color separation pulse from R, output 90G and output 90B respectively
SP _R , SP _G and SP _B are output, the clamp pulse CP is output from the output 92, and the clock CK is output from the output 94.

The image pickup input circuit 12 converts an image formed on the image pickup surface of the CCD image pickup element through a color filter into an electric signal, and outputs 100R to R signal, 100G to G signal output,
The output 100B outputs each color signal of the B signal. The color signals output from the image pickup input circuit 12 are switched between RGB color signals by color separation pulses SP _R , SP _G, and SP _B input to a multiplexer 14 shown in FIGS. 3B to 3D. Further, while each color signal is held for a certain period of time by the capacitor and buffer 18 connected to the output 102 thereof, for example, as shown in FIG. 3 (E), a linearized signal is generated in which each RGB color signal appears in sequence. To be done. This RGB signal is input to the input 104 of the clamp circuit 20, and, for example, the level shown by the broken line in this figure is clamped as the clamp level.

Next, the clamp level of this RGB signal is A
The output level of the clamp circuit 20 is output at a value that makes the input level of the / D converter 22 zero, for example. A / D
The converter 22 receives the RGB signal and outputs the signal.
RGB input based on the clock CK supplied from 10
The signal is sequentially converted into digital data, and the output 110 outputs digital RGB data in parallel. One of the output RGB data is transferred to the addition / subtraction circuit 32,
On the other hand, the lower 4-bit data of this data is branched and input to the detection circuits 26R, 26G and 26B, respectively.
Entered in. RGB color detection circuits 26R, 26G and 26B
Further, the clamp pulse CP and the corresponding color separation pulses SP _R , SP _G and SP _B are respectively inputted, and when both of these pulses become significant, the data of the color signal is outputted. For example, in the case of the detection circuit 26R, the clamp pulse CP and the color separation pulse SP _R are both input,
Of the data appearing at the input 112, the data of the R signal is detected and output as a 4-bit digital data 114R
Is output to. In this manner, the data output from the detection circuit 26R is output in synchronization with the color separation pulse SP _R as shown in FIG. 3 (F), which is represented by 4-bit 16-step data. Similarly, the lower 4-bit data of the G data and B data signals are sequentially output from the output 114G and the output 114B.

The data output from the detection circuits 26R, 26G and 26B are input to the integration circuits 28R, 28G and 28B by the input 114R,
Input to 114G and 114B respectively. Then, in each circuit, the input data is integrated over the clamp period and the average thereof is calculated. This calculation result is output from the output 116R as correction data while the average is calculated until the next clamp pulse CP is input, as shown in FIG. 3 (G), for example. Similarly, the lower 4-bit data of the G signal and the B signal are also sequentially output as correction data from the output 116G and the output 116B.

The data output from the outputs 116R and 116G and the output 116B are input to the selector 30, respectively. At this time, the color separation pulses SP _R , SP output from the signal generation circuit 10
The input is sequentially selected and switched in synchronization with _G and SP _B , and the correction data of the RGB data is sequentially transferred from the output 118 of the selector 30 to the adder / subtractor circuit 32. on the other hand,
The 10-bit RGB data is input 110 to the adder / subtractor circuit 32.
The correction data input from the selector 30 and transferred from the selector 30 is subtracted from this RGB data, and the output 12
The difference is sequentially output from 0. As a result, the output 120 of the adder / subtractor circuit 32 during the clamp period is maintained at a constant level by correcting the offset between the color data as shown in FIG. The correction data of each color is sequentially subtracted from the video signal data transferred after the blanking period, and the difference is output from the output 120. Therefore, the output 120 of the adder / subtractor circuit 32 outputs data that does not substantially include the offset component.

The data in which the offset component between the RGB signals has been canceled by the adder / subtractor circuit 32 in this way is input to the input 120 of the gamma correction circuit 34. Then, the gamma correction is accurately performed by accurately matching the correction curve of the digital gamma correction. Thereafter, this data is subjected to various kinds of signal processing and finally stored in the memory card.

Next, another embodiment in which the offset cancel circuit 2 according to the present invention is applied to a digital electronic still camera will be described with reference to FIGS. This offset cancel circuit is a circuit for generating RGB data that does not include an offset component from the RGB signal output from the image pickup input circuit 12 as in the embodiment shown in FIGS. 1 and 2. The configuration of the signal generation circuit 10, the image pickup input circuit 12, the multiplexer 14, the clamp circuit 20, the A / D converter 22, and the gamma correction circuit 34 in FIG. 4 may be the same as the circuit of the embodiment shown in FIG. In the example, the A / D converter
The difference is that a feedback clamp circuit that feeds back the data of the lower 4 bits of the output of 22 to the input side is configured. More specifically, the offset cancel circuit 2 of this embodiment includes a buffer 38 in addition to these circuits,
The differential amplifier 40, the detection integration circuit 42, the correction data generation circuit 44, the D / A converter 46, the resistor 48, and the capacitor 50.
And are provided for each RGB data.

Outputs 100R, 100G and 10 of the imaging input circuit 12
0B is connected to the non-inverting inputs (+) of differential amplifiers 40R, 40G and 40B, respectively. On the other hand, differential amplifiers 40R, 40
G and 40B are equipped with inverting inputs (-) 130R, 130G and 130B, and have the function of outputting according to the difference between the signals input to the inverting input (-) and the non-inverting input (+), respectively. .. These outputs 132R, 132G and 132B are connected to the multiplexer 14. The output 134 of the multiplexer 14 is connected to the clamp circuit 20, and its output 136 is connected to the buffer 38 that amplifies the signal output from the clamp circuit 20. The buffer 38 is a preamplifier for appropriately inputting an RGB signal to the A / D converter 22 connected to its output 138. The A / D converter 22 is connected to the gamma correction circuit 34 via a 10-bit bus 140. Furthermore, the bus 142 of the lower 4 bits is branched,
It is connected to the detection integration circuits 42R, 42G and 42B shown in FIG.

The detection integration circuit 42R appears on the bus 142.
This circuit detects R data from RGB data, integrates the R data, and generates average data representing the average value of these data. The detection integration circuit 42R is a signal generation circuit.
A circuit for supplying a clamp pulse CP and a color separation pulse SP _R from 10 to detect R data in the clamp period and generate average data representing an average value of the R data. Also,
The detection integration circuit 42R may have the same configuration as the circuit in which the detection circuit 26R shown in FIG. 1 and the integration circuit 28R are combined. The generated average data is transferred to the correction data generation circuit 44R connected to this output 144R. Similarly, a detection integration circuit which is supplied with color separation pulses SP _G and SP _B to detect G data and B data, generates respective average data, and transfers these average data to the correction data generation circuits 44G and 44B. Equipped with 42G and 42G.

The correction data generation circuit 44R is a detection integration circuit.
This is a circuit for generating data for correcting the offset from the R data transferred from 42R. Specifically, the correction data generation circuit 44R inputs the average data including the offset calculated by the detection integration circuit 42R to the input 144R and generates 4-bit correction data so that the average data becomes a predetermined reference value. Has a function to output this correction data 146R
It is a circuit that transfers to the D / A converter 46R connected to. The correction data generation circuits 44G and 44B for generating the correction data of the G data and the B data are also configured in the same manner.

The D / A converter 46R is a digital / analog converter that converts the 4-bit correction data input to its input 146R into an analog voltage. For details, see D / A
The converter 46R is a circuit that converts the correction data transferred from the correction data generation circuit 44R into an analog voltage based on the clock CK supplied from the signal generation circuit 10 and outputs this correction voltage to its output 148R. is there. This output 14
8R is the inverting input 130R of the differential amplifier 40R through the resistor 48R.
It is connected to the. In addition, the inverting input 130R is a capacitor
Grounded through 50R. Capacitor 50R has terminal 13
It has a function of storing and storing the voltage applied to 0R. These detection integration circuit 42R, correction data generation circuit 44R
The D / A converter 46R and the resistor 48R form a feedback path of the differential amplifier 40. As a result, when the voltage stored in the capacitor 50R rises, the differential amplifier 40R
The input potential difference is relatively reduced to lower the level of its output 132R. Conversely, when the stored voltage drops, the input potential difference of the differential amplifier 40R is made relatively large and its output
Raise the level of 132R. Thus, these circuits are
Correction data is generated from the lower 4 bits of data output from the D converter 22R, the correction data is converted to an analog voltage, stored in the capacitor 50R, and fed back negatively to the differential amplifier 40R. Is composed of. The D / A converters 46G and 46B, the resistors 48G and 48B, and the capacitors 50G and 50B, which generate the correction voltages for the G data and the B data, are similarly configured.

The operation of the offset cancel circuit 2 in this embodiment having the above structure will be described below with reference to FIG. In the same figure, the waveform of each signal in the clamp period of the blanking period is shown. First, when the power is turned on, the signal generation circuit 10 operates as shown in FIG.
As shown in (C) to (E), the color separation pulses SP _R , SP _G and
SP _B is output, the clamp pulse CP is output from the output 92, and the clock CK is output from the output 94, as shown in FIG.

The color signals of the output 100R, the output 100G to the G signal, and the output 100B to the B signal of the image pickup input circuit 12 are output, and these color signals are input to the non-inverted inputs of the differential amplifiers 40R, 40G and 40B. Each is entered in 100. On the other hand, the signal input to the inverting input 130 is generated as follows.

First, the non-inverting input 100 of the differential amplifier 40
An output corresponding to the difference between each RGB color signal input to the input terminal and the voltage of the inverting input 130 is output from the output 132 and input to the multiplexer 14. The multiplexer 14 linearizes these input signals to generate a signal in which the RGB color signals sequentially appear, and this signal is output from the output 134 thereof. This linearized RGB signal is sent to the clamp circuit 20
To be clamped and amplified by the buffer 38. In this way, as shown in FIG. 6 (B), each color signal
RGB are sequentially generated, and a predetermined DC voltage is added to the RGB signal to generate a signal adjusted to a predetermined input level of the A / D converter 22. This RGB signal is input to the input 138 of the A / D converter 22 and converted into 10-bit digital data. Of this data, the lower 4-bit data of the bus 140 is detected and integrated via the bus 142 by the detection integration circuit 42.
Transferred to R, 42G and 42B.

For example, the detection integration circuit 42R receives the clamp pulse CP and the color separation pulse SP _R and selects and inputs the R data from the 4-bit RGB data transferred to the input 142. The R data detected by being input to the detection integrating circuit 42R appears every time the color separation pulse SP _R is input, as shown in FIG. 6 (F) in which digital numerical values are shown in steps. The R data thus input is integrated every time the color separation pulse SP _R is input over the clamp period, and the average thereof is calculated. This calculated average data is output from its output 144R for a certain period, for example, as shown by the broken line in FIG. 6 (G), until the next clamp pulse is input.

Average data is input to the correction data generation circuit 44R, and based on this average data, the level of the R data input during the clamp period becomes a predetermined reference value, for example, as shown in FIG. 6 (G). Correction data is generated as shown and output from its output 146R. The correction data is D
It is input to the input 146R of the / A converter 46R and converted to an analog voltage. This correction voltage is applied from the D / A converter 46R to the resistor 48R to charge the capacitor 50R. At this time, this charging voltage is supplied to the inverting input 130R of the differential amplifier 40R to form a feedback loop. Similarly, the other color data are also detected by the detection integration circuits 42G and 42B, and the average data of these are generated each time. Then, the correction data generation circuits 44G and 44B generate correction data, and this data is fed back to the differential amplifier 40 as an analog correction voltage by charging the capacitor 50 via the resistor 50.

A correction voltage was applied to the inverting inputs 130R, 130G and 130B of the differential amplifiers 40R, 40G and 40B, respectively, and applied to their non-inverting inputs 100R, 100G and 100B.
The difference from the RGB signal is amplified and its output 132R, 132G and
The signal voltage of the same level is output from each of 132B.
These voltages are linearized by the multiplexer 14, clamped by the clamp circuit 20, and input to the buffer 38. The input signal voltage is amplified, output from the buffer 38, and converted into digital data by the A / D converter 22. Then, as shown in FIG. 6 (H), A
Output from the / D converter 22.

In this way, during the clamp period, the clamp level during the blanking period of the video signal input from the imaging input circuit 12 to the non-inverting inputs 100R, 100G and 100B of the differential amplifiers 40R, 40G and 40B is , The correction voltage generated for each color signal and fed back is its inverting input 130R, 130G
And input to 130B and their outputs 132R, 132G and 13
It is output after being corrected to a certain level from 2B. And
This correction voltage is applied to capacitors 50R, 50G and 50G, respectively.
It is stored in B and held until the clamp period of the next blanking period. After this clamp period ends, the RGB signal representing the image picked up from the image pickup input circuit 12 becomes a non-inverting input 100R, 100G of the differential amplifiers 40R, 40G and 40B.
Input to 100B and also inverting inputs 130R, 130G and 13
The correction voltage stored in the capacitors 50R, 50G and 50B is applied to 0B. Therefore, the differential amplifiers 40R, 40G and
The offset between the color signals output from 40B is corrected, and the color signals having substantially no difference in offset component between the color signals are output from the outputs 132R, 132G and 132B. The output color signals are supplied to the multiplexer 14
Is output as a single line at the output 134. The linearized RGB signal is clamped by the clamp circuit 20, a DC component is added, and further amplified by the buffer 38. Then, this RGB signal is input to the A / D converter 22 and converted into 10-bit digital data.
This converted digital data is transferred to the gamma correction circuit 34 via the bus 140, and thereafter, the same operation as that of the embodiment shown in FIGS. 1 and 2 is performed.

At this time, the lower 4-bit data of the bus 140 is branched, but the detection integration circuit 42 for each color data is used.
Since the clamp pulse CP is not input to R, 42G and 42B, these color data are not detected. In particular, in this embodiment, since the offset-corrected signal is input to the A / D converter 22, the input range (dynamic range) of the A / D converter 22 can be effectively used.

As described above, in any of the embodiments of the present invention, a plurality of color signals of a video signal are linearized and digitized. Clamp level data for the clamp period is detected for each color signal from the digitized video signal, and correction data for correcting the offset is generated from this data. Since the offset generated between the color signals is substantially eliminated based on the correction data, the color shift component included in the video signal data can be canceled. As a result, in the subsequent gamma correction process, it is possible to improve the color balance of the video signal data in the low luminance region and prevent the deterioration of the color reproducibility. Moreover, the circuit for inputting the video signal does not have to be manually and accurately adjusted to cancel the offset.

The embodiments described here are for explaining the present invention, and the present invention is not necessarily limited to this.

[0045]

As described above, according to the offset cancel circuit of the present invention, the data of each color component of the digitized video signal is extracted and the average value of the clamp level of the data is calculated. Since the correction means corrects the offset generated between the color signals based on the average value of these clamp levels, it is possible to cancel the deviation of the reference level included in the data of this video signal. As a result, in the subsequent gamma correction process, it is possible to improve the color balance of the video signal data in the low luminance region and prevent the deterioration of the color reproducibility. Moreover, there is an excellent effect that the offset can be canceled in the circuit for inputting the video signal without manual adjustment.

[Brief description of drawings]

FIG. 1 is a diagram showing a part of an embodiment of a digital electronic still camera to which an offset cancel circuit according to the present invention is applied.

FIG. 2 is a diagram showing the remaining portion of the embodiment shown in FIG.

FIG. 3 is a timing chart showing an operation of each unit of the offset cancel circuit shown in FIGS. 1 and 2.

FIG. 4 is a diagram showing a part of another embodiment of a digital electronic still camera to which an offset cancel circuit according to the present invention is applied.

5 is a diagram showing the remaining portion of the embodiment shown in FIG.

6 is a timing chart showing an operation of each unit of the offset cancel circuit shown in FIGS. 4 and 5. FIG.

[Explanation of symbols]

 1 Offset cancellation circuit 10 Signal generation circuit (SSG) 12 Imaging input circuit 14 Multiplexer 16 Capacitor 18 Buffer 20 Clamp circuit 22 A / D converter 26R, 26G, 26B Detection circuit 28R, 28G, 28B Accumulation circuit 30 Selector 32 Addition / subtraction circuit 34 Gamma Correction circuit

Claims (5)

[Claims] 1. An offset cancel circuit for correcting a difference between reference levels of video signals having a plurality of color components, the circuit comprising: detection means for extracting data for each color component from data of the video signal; Offset canceling means comprising: an average calculating means for calculating an average value of clamp levels of data for each component; and a correcting means for receiving the video signal and correcting an offset of the video signal based on the average value. circuit. 2. The offset cancel circuit according to claim 1, wherein the correction unit includes a calculation unit that subtracts the average value from the data of the video signal. 3. The offset cancel circuit according to claim 1, wherein the correction unit is provided corresponding to the plurality of color components, and each of the corresponding color components corresponding to a DC voltage corresponding to a control input. A plurality of amplifying means for correcting the DC level of the video signal, a correction data generating means for generating correction data for correcting the offset from the average value, a converting means for converting the correction data into an analog voltage, and the analog An offset cancel circuit, comprising: feedback means for feeding back a voltage as the DC voltage to a control input of the amplifying means corresponding to the plurality of color components. 4. The offset cancel circuit according to claim 3, wherein the circuit includes a multiplexing unit that linearizes the video signals amplified by the plurality of amplifying units. 5. The offset cancel circuit according to claim 4, wherein the circuit includes digital conversion means for converting the video signal linearized by the multiplexing means into digital data. circuit.