JPH05292410A - High-vision receiver - Google Patents

High-vision receiver

Info

Publication number
JPH05292410A
JPH05292410A JP4085213A JP8521392A JPH05292410A JP H05292410 A JPH05292410 A JP H05292410A JP 4085213 A JP4085213 A JP 4085213A JP 8521392 A JP8521392 A JP 8521392A JP H05292410 A JPH05292410 A JP H05292410A
Authority
JP
Japan
Prior art keywords
input
circuit
output
decoder
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4085213A
Other languages
Japanese (ja)
Inventor
Toshiaki Kitahara
敏明 北原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP4085213A priority Critical patent/JPH05292410A/en
Publication of JPH05292410A publication Critical patent/JPH05292410A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To connect a MUSE decoder outside without considerably increasing the number of terminals by using the decoder video signal output terminal of the conventional high-vision receiver for both of inputs and outputs and providing a changeover switch. CONSTITUTION:This device is provided with an AFC pulse input terminal 16, AFC pulse detection circuit 17 to automatically detect AFC pulses, input/output changeover switch 12, input/output discriminating circuit 18 to discriminate and switch signals from these two circuits, and video signal switching circuit 11 and corresponding to a signal from the input/output discriminating circuit, a decoder input/output circuit switches video signals from an inside simplified MUSE decoder 10 and an outside MUSE decoder 1 and impresses those video signals to a signal processing circuit 9.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は簡易型MUSEデコーダ
内蔵型の高品位テレビジョン受信機(以下、ハイビジョ
ン受信機と記す)のデコーダ入出力回路に関するもので
ある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoder input / output circuit for a high-definition television receiver (hereinafter referred to as a high-definition receiver) having a built-in simple MUSE decoder.

【0002】[0002]

【従来の技術】従来のMUSEデコーダ内蔵型ハイビジ
ョン受信機においては、MUSEデコーダの映像信号の
帯域が簡易型MUSEデコーダに比べて高いため、わざ
わざ外部MUSEデコーダ入力端子を設ける必要はな
い。
2. Description of the Related Art In a conventional high-definition receiver with a built-in MUSE decoder, since the band of the video signal of the MUSE decoder is higher than that of the simple MUSE decoder, it is not necessary to purposely provide an external MUSE decoder input terminal.

【0003】以下に従来のMUSEデコーダ内蔵型ハイ
ビジョン受信機のデコーダ関連端子について、図4を用
いて説明する。図4に示すように、デコーダ関連端子は
映像出力端子2、3、4及び音声出力端子5、6、7、
8の出力端子のみを有し、入力端子は設けられていな
い。
Decoder-related terminals of a conventional high definition receiver with a built-in MUSE decoder will be described below with reference to FIG. As shown in FIG. 4, the decoder-related terminals are video output terminals 2, 3, 4 and audio output terminals 5, 6, 7,
It has only 8 output terminals and no input terminals.

【0004】[0004]

【発明が解決しようとする課題】しかしながら上記の構
成では、内蔵されているデコーダが簡易型MUSEデコ
ーダの場合、簡易型MUSEデコーダの映像信号の帯域
がMUSEデコーダの映像信号の帯域に及ばないため、
画質の面で見劣りがする。また、デコーダ入力端子がな
いため、外部にMUSEデコーダを接続することができ
ないという欠点がある。
However, in the above configuration, when the built-in decoder is the simple MUSE decoder, the band of the video signal of the simple MUSE decoder does not reach the band of the video signal of the MUSE decoder.
It is inferior in terms of image quality. Further, since there is no decoder input terminal, there is a drawback that the MUSE decoder cannot be connected to the outside.

【0005】本発明は上記の欠点に鑑み、デコーダの映
像信号出力端子を入出力兼用端子とすることで、端子数
を増やすことなく外部にMUSEデコーダを接続できる
ことを目的とする。
In view of the above drawbacks, it is an object of the present invention to connect the MUSE decoder to the outside without increasing the number of terminals by using the video signal output terminal of the decoder as an input / output terminal.

【0006】[0006]

【課題を解決するための手段】上記問題を解決するため
に、本発明のハイビジョン受信機用デコーダ入出力回路
は、従来のハイビジョン受信機のデコーダ映像出力端子
を入出力兼用としユーザーがスイッチを切り替えること
で外部にMUSEデコーダを接続できるようにするもの
である。
In order to solve the above problems, a decoder input / output circuit for a high-definition receiver according to the present invention uses a decoder video output terminal of a conventional high-definition receiver as an input / output and a user switches a switch. This allows the MUSE decoder to be connected to the outside.

【0007】また、請求項2の発明は、上記ハイビジョ
ン受信機の構成のように、自動周波数制御(Autom
atic Frequenncy Control:以
下AFCと示す)パルス入力端子と検出回路と入出力判
別回路を組み合わせることでユーザーが外部入力に切り
替えていても、外部MUSEデコーダからの映像信号が
入力されない場合、つまり、外部MUSEデコーダから
のAFCパルスが検出されない場合、自動的に内蔵され
ている簡易型MUSEデコーダの映像に切り替えること
ができるデコーダ入出力回路を有するハイビジョン受信
機である。
According to a second aspect of the present invention, the automatic frequency control (Autom) is provided as in the configuration of the high-definition receiver.
Attic Frequency Control (hereinafter referred to as AFC) When the video signal from the external MUSE decoder is not input even when the user switches to external input by combining the pulse input terminal, the detection circuit, and the input / output determination circuit, that is, the external MUSE This is a high-definition receiver having a decoder input / output circuit that can automatically switch to the image of the built-in simplified MUSE decoder when an AFC pulse from the decoder is not detected.

【0008】また、請求項3の発明は、受信機本体に、
MUSE信号入力端子があり、しかも子画面機能を有す
る場合のためのもので、通常MUSE受信時には簡易型
MUSEデコーダまたはMUSEデコーダからのAFC
パルスをBSチューナに与えるため、BSチューナの動
きを拘束してしまうが、上記の請求項2の発明にMUS
E信号入力端子とAFCパルス切り替え回路と制御回路
を組み合わせることで、MUSE信号源からの映像を親
画面に映す際、内蔵の簡易型MUSEデコーダの映像を
使用し、また、簡易型MUSEデコーダからのAFCパ
ルスをAFCパルス切り替え回路でストップさせること
で、BSチューナの動きをフリーにさせることにより、
子画面にBSチューナのNTSC出力を映すまたは親子
逆の表示ができるようにしたものである。
According to the invention of claim 3, in the receiver main body,
This is for the case where there is a MUSE signal input terminal and also has a sub-screen function, and during normal MUSE reception, a simplified MUSE decoder or an AFC from the MUSE decoder
Since the pulse is given to the BS tuner, the movement of the BS tuner is restricted.
By combining the E signal input terminal, the AFC pulse switching circuit, and the control circuit, when the image from the MUSE signal source is displayed on the main screen, the image of the built-in simple type MUSE decoder is used, and the simple type MUSE decoder By stopping the AFC pulse with the AFC pulse switching circuit, by freeing the movement of the BS tuner,
The NTSC output of the BS tuner is displayed on the child screen or the parent and child display can be reversed.

【0009】[0009]

【作用】本発明は上記した構成により、簡易型MUSE
デコーダ内蔵のハイビジョン受信機に端子数を大きく増
やすことなく外部にMUSEデコーダを接続する事がで
きる。
The present invention has the above-mentioned configuration and is of a simplified type MUSE.
It is possible to connect a MUSE decoder to the outside without greatly increasing the number of terminals in the HDTV receiver with a built-in decoder.

【0010】[0010]

【実施例】以下、本発明の一実施例について図面を参照
しながら説明する。図1、図2、図3、図4で示される
同一番号及び同一符号の部品または手段は同一のものを
示す。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. The same reference numerals and parts or means shown in FIGS. 1, 2, 3, and 4 indicate the same parts.

【0011】(実施例1)図1は本発明の第1の実施例
を示すブロック図である。 簡易型MUSEデコーダ1
0からの映像信号Aは入出力切り替えスイッチ12が出
力に設定されている場合は、双方向の映像信号切り替え
回路11を通して信号処理回路9及び映像入出力端子1
3、14、15に出力される。ハイビジョン受信機の外
部のMUSEデコーダ1が映像入出力端子13、14、
15に接続されていれば、ユーザーガ入出力切り替えス
イッチ12を入力側にすることで映像信号切り替え回路
11が切り替えられて、前記MUSEデコーダ1の信号
が信号処理回路9に入力されることになる。
(First Embodiment) FIG. 1 is a block diagram showing a first embodiment of the present invention. Simple MUSE decoder 1
When the input / output switch 12 is set to output the video signal A from 0, the signal processing circuit 9 and the video input / output terminal 1 are passed through the bidirectional video signal switching circuit 11.
It is output to 3, 14, and 15. The MUSE decoder 1 external to the HDTV receiver has video input / output terminals 13 and 14,
If it is connected to 15, the video signal switching circuit 11 is switched by setting the user input / output selector switch 12 to the input side, and the signal of the MUSE decoder 1 is input to the signal processing circuit 9. ..

【0012】(実施例2)次に、本発明の第2の発明の
一実施例について図2を参照しながら説明する。
(Embodiment 2) Next, an embodiment of the second invention of the present invention will be described with reference to FIG.

【0013】図2において図1の構成の他に、入出力切
り替えスイッチ12と映像信号切り替え回路11との間
に入出力判別回路が追加され、また、AFCパルス入力
端子16とAFCパルス検出回路17が追加されている
点である。ハイビジョン受信機外部のMUSEデコーダ
1からのAFCパルスの検出信号と入出力切り替えスイ
ッチ12からの信号とを入出力判別回路18で判別する
ことにより、入出力切り替えスイッチ12が入力側でも
MUSEデコーダ1の電源がOFF等の理由により、A
FCパルスが検出されない場合には内蔵の簡易型MUS
Eデコーダ10からの映像信号を優先して信号処理回路
9に与えることができる。
In FIG. 2, in addition to the configuration of FIG. 1, an input / output discrimination circuit is added between the input / output changeover switch 12 and the video signal changeover circuit 11, and an AFC pulse input terminal 16 and an AFC pulse detection circuit 17 are provided. Is added. The AFC pulse detection signal from the MUSE decoder 1 outside the HDTV receiver and the signal from the input / output selector switch 12 are discriminated by the input / output discriminating circuit 18, so that the input / output selector switch 12 is on the input side. A due to the power being off, etc.
Built-in simplified MUS when FC pulse is not detected
The video signal from the E decoder 10 can be given priority to the signal processing circuit 9.

【0014】(実施例3)次に、本発明の第3の発明の
一実施例について図3を参照しながら説明する。
(Embodiment 3) Next, an embodiment of the third invention of the present invention will be described with reference to FIG.

【0015】図3において図2の構成と異なる部分は、
MUSE信号入力端子19とAFCパルス切り替え回路
20と制御回路21が追加されている点であり、前記制
御回路21からの制御信号は入出力判別回路18にも入
力される。これはMUSE信号入力端子19と子画面機
能を受信機に有している場合に対応したもので、MUS
EVTR等のMUSE信号源からの信号を画面に映す場
合簡易型MUSEデコーダ10を使用するため制御回路
21から制御信号を入出力判別回路18に与え、簡易型
MUSEデコーダ10からの映像信号を信号処理回路9
に与えるよう強制的に切り替えるものである。またこの
とき、AFCパルスが簡易型MUSEデコーダから出力
されるが、これをBSチューナ22に与えるとその動き
を拘束してしまうため、子画面にBSのNTSC出力を
表示できなくなるので、それを防ぐためAFCパルス切
り替え回路20で、AFCパルスを強制的にストップさ
せ、BSチューナの動きを自由にする。これは、親子の
画面が逆の場合も同様である。
3 is different from that of FIG. 2 in that
The MUSE signal input terminal 19, the AFC pulse switching circuit 20, and the control circuit 21 are added, and the control signal from the control circuit 21 is also input to the input / output determination circuit 18. This corresponds to the case where the receiver has the MUSE signal input terminal 19 and the sub-screen function.
When a signal from a MUSE signal source such as an EVTR is displayed on the screen, a control signal is supplied from the control circuit 21 to the input / output determination circuit 18 in order to use the simplified MUSE decoder 10, and the video signal from the simplified MUSE decoder 10 is processed. Circuit 9
It is forcibly switched to give to. At this time, the AFC pulse is output from the simplified MUSE decoder, but if this is given to the BS tuner 22, its movement is restricted, and the NTSC output of the BS cannot be displayed on the inset screen. This is prevented. Therefore, the AFC pulse switching circuit 20 forcibly stops the AFC pulse and frees the movement of the BS tuner. This is the same when the parent and child screens are reversed.

【0016】[0016]

【発明の効果】本発明は上記した構成により、簡易型M
USEデコーダ内蔵のハイビジョン受信機に端子数を大
きく増やす事なく外部にMUSEデコーダを接続する事
ができる。
The present invention has the above-described structure and is of a simplified type M
It is possible to connect the MUSE decoder to the outside without greatly increasing the number of terminals in the HDTV receiver with a built-in USE decoder.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例におけるハイビジョン受信機
のデコーダ入出力回路のブロック図
FIG. 1 is a block diagram of a decoder input / output circuit of a high-definition receiver according to an embodiment of the present invention.

【図2】本発明の第2の発明の一実施例におけるハイビ
ジョン受信機のデコーダ入出力回路のブロック図
FIG. 2 is a block diagram of a decoder input / output circuit of a high-definition receiver in one embodiment of the second invention of the present invention.

【図3】本発明の第3の発明の一実施例におけるハイビ
ジョン受信機のデコーダ入出力回路のブロック図
FIG. 3 is a block diagram of a decoder input / output circuit of a high-definition receiver in one embodiment of the third invention of the present invention.

【図4】従来のハイビジョン受信機の映像及び音声出力
部のブロック図
FIG. 4 is a block diagram of a video and audio output unit of a conventional high-definition receiver.

【符号の説明】[Explanation of symbols]

1 MUSEデコーダ 10 簡易型MUSEデコーダ 11 映像信号切り替え回路 12 入出力切り替えスイッチ 16 AFCパルス入力端子 17 AFCパルス検出回路 18 入出力判別回路 1 MUSE Decoder 10 Simple MUSE Decoder 11 Video Signal Switching Circuit 12 Input / Output Changeover Switch 16 AFC Pulse Input Terminal 17 AFC Pulse Detection Circuit 18 Input / Output Discrimination Circuit

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 映像信号切り替え回路と入出力切り替え
スイッチとを有し、前記切り替えスイッチの信号によ
り、内部の簡易型MUSEデコーダと外部のMUSEデ
コーダの映像信号とを切り替え、信号処理回路にその映
像信号を与えるデコーダ入出力回路を備えるハイビジョ
ン受信機。
1. A video signal changeover circuit and an input / output changeover switch are provided, and a video signal of an internal simplified MUSE decoder and an external MUSE decoder is changed over by a signal of the changeover switch, and the video is outputted to a signal processing circuit. A high-definition receiver equipped with a decoder input / output circuit that gives signals.
【請求項2】 AFCパルス入力端子と、パルスを検出
するAFCパルス検出回路と、入出力切り替えスイッチ
と、前記AFCパルス検出回路または前記入出力切り替
えスイッチからの信号を判別し切り替える入出力判別回
路と、映像信号切り替え回路とを有し、前記入出力判別
回路からの信号により、内部の簡易型MUSEデコーダ
と外部のMUSEデコーダの映像信号とを切り替え、信
号処理回路にその映像信号を与えるデコーダ入出力回路
を備えるハイビジョン受信機。
2. An AFC pulse input terminal, an AFC pulse detection circuit that detects a pulse, an input / output changeover switch, and an input / output determination circuit that determines and switches a signal from the AFC pulse detection circuit or the input / output changeover switch. A decoder input / output having a video signal switching circuit, which switches between a video signal of an internal simplified MUSE decoder and an external MUSE decoder according to a signal from the input / output determination circuit, and supplies the video signal to a signal processing circuit. HDTV receiver with circuit.
【請求項3】 AFCパルス入力端子と、パルスを検出
するAFCパルス検出回路と、入出力切り替えスイッチ
と、前記AFCパルス検出回路または前記入出力切り替
えスイッチからの信号を判別し切り替える入出力判別回
路と、映像信号切り替え回路と、MUSE信号入力端子
と、AFCパルス切り替え回路と、制御回路を有し、前
記入出力判別回路からの信号により、内部の簡易型MU
SEデコーダと外部のMUSEデコーダの映像信号とを
切り替え、信号処理回路にその映像信号を与え、また前
記入出力判別回路と前記制御回路からの信号によりAF
Cパルスも切り替えBSチューナに与えることのできる
デコーダ入出力回路を備えるハイビジョン受信機。
3. An AFC pulse input terminal, an AFC pulse detection circuit for detecting a pulse, an input / output changeover switch, and an input / output discrimination circuit for discriminating and switching a signal from the AFC pulse detection circuit or the input / output changeover switch. , A video signal switching circuit, a MUSE signal input terminal, an AFC pulse switching circuit, and a control circuit, and an internal simplified MU is provided by a signal from the input / output determination circuit.
The SE decoder and the video signal of the external MUSE decoder are switched, the video signal is given to the signal processing circuit, and AF is performed by signals from the input / output determination circuit and the control circuit.
A high-definition receiver equipped with a decoder input / output circuit that can also switch C pulses to the BS tuner.
JP4085213A 1992-04-07 1992-04-07 High-vision receiver Pending JPH05292410A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4085213A JPH05292410A (en) 1992-04-07 1992-04-07 High-vision receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4085213A JPH05292410A (en) 1992-04-07 1992-04-07 High-vision receiver

Publications (1)

Publication Number Publication Date
JPH05292410A true JPH05292410A (en) 1993-11-05

Family

ID=13852305

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4085213A Pending JPH05292410A (en) 1992-04-07 1992-04-07 High-vision receiver

Country Status (1)

Country Link
JP (1) JPH05292410A (en)

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