JPH05291533A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the matching to a MOS structure device by providing a memory cell using voltage control type negative resistance characteristics between a gate voltage and a gate current of a MOS transistor. CONSTITUTION:A source electrode S and a substrate BG of a MOS transistor including a memory cell are connected to 0V (ground). A power voltage VCC is applied to a gate electrode G through a resistor R. The gate electrode G of the cell is addressed by a bit line BL, a word line WL and a transfer transistor QTR. When information is written to the memory cell, the cell of a given address is selected by the transfer transistor QTR and a high or low voltage is applied to the gate electrode G of the MOS transistor by the bit line BL and a gate current IG is held to either high or low stable point. Also, erasure of information written is performed by applying a negative voltage to the gate electrode G similarly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a memory cell utilizing the voltage controlled negative resistance characteristic of the gate voltage and gate current of a MOS transistor.

[0002]

2. Description of the Related Art Generally, a negative process element is divided into a voltage control type and a current control type, and from the shape of their IV characteristics,
The former is said to be N characteristic type, and the latter is said to be S characteristic type.

FIGS. 5A and 5B are characteristic explanatory views of the negative resistance element. The IV characteristic shown in FIG. 5A is a current control type and is called an S characteristic type because of its shape.
The pnpn switch is a typical example. In addition, FIG.
The IV characteristic shown in is a voltage control type and is called an N characteristic type because of its shape.
The everbase current) is well known.

[0004]

However, all of the above-mentioned conventionally known negative resistance elements are bipolar elements, and their compatibility with the MOS structure elements which have been diversified in recent years is poor, so that they are mainly composed of MOS elements. There is a problem that it cannot be used for integrated circuits. In view of the above circumstances, it is an object of the present invention to provide a semiconductor device having a memory cell that utilizes the voltage-controlled negative resistance characteristics of the gate voltage and gate current of a MOS transistor.

[0005]

In a semiconductor device including a memory cell according to the present invention, a voltage control type negative resistance characteristic between the gate voltage and the gate current of a MOS transistor is used. Further, in this case, a capacitor was connected between the gate electrode of the MOS transistor and the substrate.

[0006]

6A and 6B are gate voltage-gate current characteristic diagrams of a typical NMOS transistor. In this figure, 21 is a p-type semiconductor substrate, 22 is a source region, 23 is a drain region, 24 is a gate insulating film, and 25 is a gate electrode.

As shown in FIG. 6A, a source region 22 and a drain region 2 are formed on a p-type semiconductor substrate 21.
3 of the sub-micron NMOS transistor in which the gate electrode 25 is formed with the gate insulating film 24 interposed therebetween and the voltage V _S of the source region 22 and the p-type semiconductor substrate 2
With the voltage V _BG of 1 being 0 V (ground) and a constant voltage V _DS being applied between the source region 22 and the drain region 23, the gate voltage V _GS between the source region 22 and the gate electrode 25 is changed from 0 V. Going up.

As described above, when the gate voltage V _GS is increased from 0 V, the gate current I _G does not reach the voltage V _DS between the source region 22 and the drain region 23, as shown in FIG. 6B. It shows an N characteristic type negative resistance characteristic that rises and reaches a maximum value, then falls, reaches a minimum value, and then rises again. This example shows the characteristics of the NPMOS transistor, but the polarity,
A tendency similar to the above is shown only when the positive and negative of the current are reversed.

This gate current is mainly caused by injection of hot electrons into the gate electrode.
The cause of the characteristic type negative resistance characteristic will be described.

The causes of the gate current are: Electrons in the channel obtain energy by an electric field in the direction along the channel (channel horizontal electric field), and have energy larger than the height of the energy barrier at the interface between the semiconductor substrate (Si) and the gate insulating film (SiO ₂ ). Only hot electrons cross the energy barrier and are injected into the gate oxide film (channel hot electron (CHE) injection).

2. Channel electrons, which gained high energy by a large horizontal electric field near the drain, generate electron-hole pairs by collision ionization with the lattice or avalanche multiplication, and these electrons or holes become hot and are injected into the oxide film. (Drain avalanche hot carrier (D
AHC) injection)

3. When a substrate bias voltage is applied and a thick depletion layer is formed on the surface of the substrate under the gate electrode, electrons injected into the depletion layer from the substrate side or electrons generated in the depletion layer are The substrate is accelerated by the electric field of 1 to become hot, and is injected into the gate oxide film (substrate hot carrier (SHE) injection).

However, among the factors that generate these gate currents, channel hot electrons (CHE)
The injection is overwhelmingly large compared to other factors. Here, as shown in FIG. 6B, the gate current is V _GS = V
Consider the reason why the gate voltage near _{DS has a} maximum value.

FIGS. 7A and 7B are explanatory views of channel hot electron injection. Like in FIG. 6, reference numerals in this figure are 21 p-type semiconductor substrate, 22 source region (S), 23 drain region (D), 24 gate insulating film (GOX), and 25 gate electrode (G). ).

In this NMOS transistor, as shown in FIGS. 7A and 7B, a source region 22 and a drain region 23 are formed on a p-type semiconductor substrate 21, and a gate is provided between them. A gate electrode 25 is formed via an insulating film (GOX) 24.

The voltage V _S of the source region 22 and the voltage V _BG of the p-type semiconductor substrate 21 of this NMOS transistor are 0V.
The gate voltage V _GS between the source region 22 and the gate electrode 25 is increased from 0 V in a state where (ground) and a constant voltage V _DS is applied between the source region 22 and the drain region 23.

[Gate current in the range of V _GS <V _DS ] (see FIG. 7A)
When the gate voltage V _GS is increased from 0 V in the range of V _GS <V _DS , the gate current sharply increases as shown in FIG. 6 (B). When V _GS <V _DS , the hot electron injection region that reaches the gate electrode and becomes the gate current is located slightly closer to the source side than the drain end, and when the gate voltage rises, this injection region becomes horizontal. This is because the directional electric field E _y moves to the larger drain side.

That is, in this gate voltage region, since the vicinity of the drain is pinched off, the electric field E _y in the horizontal channel direction rapidly increases from the channel region near the pinch off point toward the drain end. Therefore, moving the injection region to the drain side is more effective for hot electron injection than the reduction of the horizontal electric field E _y of the channel at the drain end due to the increase of the gate voltage, and it works more effectively for hot electron injection. Will increase.

Further, the direction of the vertical electric field E _x in Si-SiO ₂ interface, but the drain terminal is the direction that prevents the injection of electrons into the oxide film, the electrons into the oxide film toward the source side It will help inject. Therefore, the hot electron injection region is considered to be a region between the point where the direction of the vertical electric field E _x changes and the point where the channel horizontal direction electric field E _y reaches the critical electric field required for hot electron injection.

[Gate current in the range of V _GS > V _DS ] (see FIG. 7B)
After reaching the maximum value at V _GS ≈V _DS , V _GS >
When the gate voltage is raised within the range of V _DS, the gate current I _G sharply decreases. Not pinched off channel at the drain end in this case, since the Si-SiO ₂ interface channel vertical field E _x always also has a direction to assist the hot electron injection, happen hot electron injection is the most drain end Is.

The maximum electric field E _{y in the} channel horizontal direction at the drain end decreases as the gate voltage V _GS increases, so that the number of hot electrons having sufficient energy to be injected into the oxide film also decreases, and The current also decreases. Then, when the gate voltage V _GS is further increased, the gate current has a minimum value.

Up to now, we have considered the electrons that have sufficient energy to be injected into the oxide film by accelerating only the horizontal electric field E _y . However, as it increases the gate voltage V _GS, the number of hot electrons having sufficient energy to be injected into the accelerated and oxide film Si-SiO ₂ interface channel vertical field E _x is increased, the gate current I _G increases again.

As described above, the submicron MOS
Since the transistor has a voltage control type negative resistance characteristic (N characteristic type negative characteristic), a memory cell can be realized by utilizing this characteristic.

[0024]

EXAMPLES Examples of the present invention will be described below. (First Embodiment) FIGS. 1A and 1B are diagrams of the first embodiment.
It is explanatory drawing of a molysel. FIG. 1 (A) shows the message of this embodiment.
FIG. 1B shows a schematic configuration of a molycell. _G-V
_GSThe voltage-controlled negative resistance characteristic of is shown.

Although FIG. 1A shows the memory cell of the first embodiment which is composed of one MOS transistor, the source electrode S of the MOS transistor constituting the memory cell and the substrate BG.
0V (ground) is applied to the gate electrode, and the resistor R is applied to the gate electrode G.
A power supply voltage V _CC is applied through the gate electrode G of this cell is addressed by a bit line BL, a word line WL and a transfer transistor Q _TR .

To write information to this memory cell, a cell at a predetermined address is selected by the transfer transistor Q _TR , and a high voltage or a low voltage is applied to the gate electrode G of the MOS transistor by the bit line BL, as shown in FIG. The gate current I _{G in the} characteristic shown in B) is set to High and Lo.
It is performed by holding either of two stable points of w and associating their states with "1" or "2".

Further, the read of the written information is performed by selecting a cell at a predetermined address by the transfer transistor Q _TR and detecting the voltage of the gate electrode G of the MOS transistor by a sense amplifier connected to the bit line BL. Be seen.

Further, erasing written information is as follows.
This is performed by selecting a cell at a predetermined address by the transfer transistor Q _TR and applying a negative voltage to the gate electrode G of the MOS transistor by the bit line BL.

2A to 2D are explanatory views of the manufacturing process of the semiconductor device of the first embodiment. In this figure, 1 is a p-type silicon substrate, 2 is a field oxide film, 3 is a protect oxide film, 4 is boron (B), 5 is a channel, 6 is a gate oxide film, 7 is a polycrystalline silicon film, and 8 is tungsten. Silicide film, 9 is a silicon oxide film, 10 is a gate electrode, 11 is a through oxide film, 12 is phosphorus (P), and 13 is n.
^- layer, 14 a sidewall, 15 through oxide film, 1
6 is arsenic (As), and 17 is an n ⁺ layer. The method of manufacturing the semiconductor device of this embodiment will be described with reference to the process explanatory drawings.

First step (see FIG. 2A) <1 of p-type silicon (Si) substrate 1 having a resistivity of 10 Ωcm
A field oxide film 2 for element isolation is formed on the 00> surface, and a protect oxide film 3 is formed on the field oxide film 2. Then, boron (B) 4 is ion-implanted at an acceleration energy of 25 keV to obtain a dose amount of 8 A channel 5 of × 10 ¹¹ cm ^-2 is formed.

Second step (see FIG. 2B) After the protective oxide film 3 is peeled off, a gate oxide film 6 having a thickness of 140 Å is formed by thermal oxidation, and a polycrystal having a thickness of 1200 Å is formed thereon by a CVD method. A silicon film 7 is formed, a tungsten silicide (WSi) film 8 having a thickness of 1000 Å and a silicon oxide (SiO 2) having a thickness of 500 Å are formed on the silicon film 7.
₂ ) Form the film 9.

Third step (see FIG. 2C) The silicon oxide film 9, the tungsten silicide film 8 and the polycrystalline silicon film 7 are patterned to form a gate electrode 10. After that, a through oxide film 11 is formed on the entire surface,
Phosphorus (P) 12 is ion-implanted at an acceleration voltage of 60 keV to form an n ⁻ layer 13 with a dose amount of 3 × 10 ¹³ cm ⁻² .

Fourth Step (see FIG. 2D) A silicon oxide film for a side wall is formed thereon by a CVD method and patterned by RIE to form a side wall 14. Through oxide film 15 on it
Then, arsenic (As) 16 is ion-implanted at an acceleration voltage of 70 eV to form an n ⁺ layer 17 having a dose amount of 4 × 10 ¹⁵ cm ⁻² .

3A and 3B are explanatory views of the MOS transistor used in the first embodiment. In this figure, 21 is a p-type substrate, 22 and 23 are n ^- layers, and 24 and 25.
Is an n ⁺ layer, 26 is a gate oxide film, and 27 is a gate electrode.

The MOS transistor used in the first embodiment shown in FIG. 3A has n ⁻ layers 22 and 23 having a dose of 3 × 10 ¹³ cm ⁻² relative to the surface of the p-type substrate 21. N ⁺ layers 24 and 25 having a dose amount of 4 × 10 ¹⁵ cm ⁻² are formed,
A gate oxide film 26 having a thickness of about 140Å is formed thereon, and a gate electrode 27 having a width of 20 μm and a length of 0.8 μm is formed thereon.

FIG. 3B shows the MO shown in FIG.
The characteristics of the gate voltage and the gate current obtained by device simulation using the impurity distribution of the S transistor as input data are shown. As can be seen from this figure, the gate voltage and gate current of the MOS transistor shown in FIG. 3A have a voltage control type negative resistance characteristic. The measured results also showed almost the same characteristics.

(Second Embodiment) FIGS. 4A and 4B show the second embodiment.
It is explanatory drawing of the memory cell of 2nd Example. Figure 4 (A)
4B shows a schematic configuration of the memory cell of the embodiment of FIG.
That I _cap-V_capShowing the negative resistance characteristic of voltage control type
There is.

FIG. 4 (A) shows a memory cell of this embodiment which is composed of one MOS transistor. 0V (ground) is applied to the source electrode S of the MOS transistor and the substrate BG which constitute the memory cell, The power supply voltage V _CC is applied to the gate electrode G through the resistor R, and
A capacitor C is connected between this gate electrode and ground, and the gate electrode G of this cell is connected to the transfer transistor Q _TR.
Connected to the bit line BL via the transfer transistor Q
_The word line WL is connected to the gate electrode of _TR . In addition, the column selection transistor Q is connected to the bit line BL.
_The write amplifier W / A and the sense amplifier S / A are connected via _CS .

In this memory cell, since the gate voltage V _GS in the first embodiment is applied to the capacitor C, the voltage control between the capacitor voltage V _cap and the capacitor current I _cap as shown in FIG. 2B is performed. Mold negative resistance characteristics are obtained. By utilizing the two stable points of this characteristic, the write amplifier W / A writes information, and the sense amplifier S /
Information read by A and written by the bit line BL can be erased.

In this embodiment, the capacitor C is provided on the gate electrode G of the MOS transistor forming the memory cell.
Therefore, the voltage of the gate electrode G can be held by the capacitor voltage V _cap even when the power supply of the circuit is cut off for a short time.

Although the memory cell according to this embodiment is increased in size by the area required to form the capacitor C, it can be miniaturized as compared with the conventional RAM using six transistors.

[0042]

As described above, according to the present invention,
Good compatibility with MOS structure elements that are widely used in recent years,
It is possible to provide a memory cell having a MOS structure of a voltage control type negative resistance characteristic that can be incorporated in an integrated circuit mainly composed of MOS, and it makes a great contribution to the technical field of an information processing device or the like.

[Brief description of drawings]

1A and 1B are explanatory views of a memory cell of a first embodiment.

FIG. 2A to FIG. 2D are views for explaining the manufacturing process of the semiconductor device of the first embodiment.

3A and 3B are explanatory diagrams of a MOS transistor used in the first embodiment.

4A and 4B are explanatory views of a memory cell according to a second embodiment.

5A and 5B are characteristic explanatory diagrams of a negative resistance element.

6A and 6B are gate voltage-gate current characteristic diagrams of a typical NMOS transistor.

7A and 7B are explanatory views of channel hot electron injection.

[Explanation of symbols]

1 p-type silicon substrate 2 field oxide film 3 protect oxide film 4 boron (B) 5 channel 6 gate oxide film 7 polycrystalline silicon film 8 tungsten silicide film 9 silicon oxide film 10 gate electrode 11 through oxide film 12 phosphorus (P) 13 n ⁻ layer 14 sidewall 15 through oxide film 16 arsenic (As) 17 n ⁺ layer

Claims (2)

[Claims] 1. A semiconductor device comprising a memory cell using a voltage control type negative resistance characteristic between a gate voltage and a gate current of a MOS transistor. 2. The semiconductor device according to claim 1, further comprising a memory cell in which a capacitor is connected between the gate electrode of the MOS transistor and the substrate.