JPH0529152B2 - - Google Patents
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- Publication number
- JPH0529152B2 JPH0529152B2 JP62067790A JP6779087A JPH0529152B2 JP H0529152 B2 JPH0529152 B2 JP H0529152B2 JP 62067790 A JP62067790 A JP 62067790A JP 6779087 A JP6779087 A JP 6779087A JP H0529152 B2 JPH0529152 B2 JP H0529152B2
- Authority
- JP
- Japan
- Prior art keywords
- gate
- bias
- magnetic material
- magnetic
- junction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000696 magnetic material Substances 0.000 description 37
- 230000004907 flux Effects 0.000 description 13
- 238000010586 diagram Methods 0.000 description 11
- 239000010410 layer Substances 0.000 description 10
- 230000005415 magnetization Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910000889 permalloy Inorganic materials 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000002269 spontaneous effect Effects 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000013016 damping Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 230000035699 permeability Effects 0.000 description 2
- 238000012827 research and development Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Electronic Switches (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はジヨセフソン集積回路装置に係り、特
に回路の高集積化、高速動作に好適なジヨセフソ
ン集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a Josephson integrated circuit device, and particularly to a Josephson integrated circuit device suitable for highly integrated circuits and high-speed operation.
従来、ジヨセフソン集積回路の論理素子および
メモリ素子の構成方法については、アイ・ビー・
エム、ジヤーナル オブ リサーチ アンド デ
イベロツプメント、24（1980年）第113頁から第
129頁（IBM Journal of research and
development，Vol.24（1980）pp.113−129）にお
いて論じられている。特にジヨセフソン接合素子
と超電導インダクタより成る閉回路で構成された
量子干渉計回路は入力信号に対する感度が高いこ
と、低消費電力であること、入出力信号の分離が
良いことなど利点を有することから種々のジヨセ
フソン集積回路を構成する要素部品として用いら
れている。
Conventionally, methods for configuring logic and memory elements in Josephson integrated circuits have been described by IBM.
M., Journal of Research and Development, 24 (1980), pp. 113-
129 pages (IBM Journal of research and
development, Vol. 24 (1980) pp. 113-129). In particular, a quantum interferometer circuit consisting of a closed circuit consisting of a Josephson junction element and a superconducting inductor has various advantages such as high sensitivity to input signals, low power consumption, and good separation of input and output signals. It is used as an elemental component in Josephson's integrated circuits.
第２図は量子干渉計回路の基本的な回路である
２接合磁気量子干渉計ゲートの等価回路を示す。
同図において×印はジヨセフソン接合素子、Ｌ１
は閉ループを構成するインダクタンス、Ｌ２は入
力信号線のインダクタンスでありＬ１と磁気的に
結合している。Rdはダンピング抵抗である。接
合にバイアス電流IBを与えた状態で入力信号線よ
り制御信号ICを印加する。第３図はこのときのIC
と接合の臨界電流との関係を示すしきい値特性図
である。同図において“−１”、“０”、“１”は閉
ループ内に取り込んでいる磁束量子数を示し、こ
れに対応して周期構造を持つ。図中の０→Ａ→Ｂ
で示すようにあらかじめバイアス電流IBを与えて
おき、次に制御信号ICを印加するとゲートはスイ
ツチする。 FIG. 2 shows an equivalent circuit of a two-junction magnetic quantum interferometer gate, which is a basic circuit of a quantum interferometer circuit.
In the same figure, the x mark is the Josephson junction element, L1
is an inductance constituting a closed loop, and L2 is an inductance of the input signal line, which is magnetically coupled to L1. R d is the damping resistance. A control signal I C is applied from the input signal line while applying a bias current I B to the junction. Figure 3 shows I C at this time.
FIG. 3 is a threshold characteristic diagram showing the relationship between and the critical current of the junction. In the figure, "-1", "0", and "1" indicate the number of magnetic flux quanta taken into the closed loop, and a corresponding periodic structure is obtained. 0→A→B in the diagram
As shown in , a bias current I B is applied in advance, and then when a control signal I C is applied, the gate is switched.
上記量子干渉計回路では入力信号を磁気的結合
によつて入力するため、入出力信号の分離は良い
反面、少なくとも１量子磁束φ0（2.07×
10-15Wb）を発生させるためのインダクタンスが
必要なためゲートの専用面積を縮小することが困
難であること、およびインダクタンスによる遅延
があるためゲートの高速動作に制限があることな
どの問題があつた。
In the quantum interferometer circuit described above, input signals are input through magnetic coupling, so separation of input and output signals is good, but at least one quantum magnetic flux φ 0 (2.07×
10 -15 Wb) is required, which makes it difficult to reduce the area dedicated to the gate, and there is a delay due to inductance, which limits the high-speed operation of the gate. Ta.
本発明の目的は量子干渉計回路のインダクタン
スを低減し、このためゲートの専用面積の縮小化
および高速動作化が可能なゲートの構成方法を提
供することにある。 SUMMARY OF THE INVENTION An object of the present invention is to provide a method of configuring a gate that can reduce the inductance of a quantum interferometer circuit, thereby reducing the area dedicated to the gate and increasing the speed of operation.
上記目的は、量子干渉計回路の閉ループ部分に
鎖交するような磁束を発生する磁気回路を磁性体
によつて構成し、入力信号を直流バイアスするこ
とにより、達成される。
The above object is achieved by configuring a magnetic circuit using a magnetic material to generate a magnetic flux that interlinks with the closed loop portion of the quantum interferometer circuit, and applying a direct current bias to the input signal.
磁性体による直流バイアス磁界は第３図におい
て入力信号を０→Ｃで示すようにバイアスする働
きを持つ。それによつて、バイアス電流IBを与え
たとき、動作点はC′の位置に設定される。ゲート
は制御信号ICによつてC′→Ｂの経路を取れば、ス
イツチする。従つて、入力信号電流によつて発生
する磁束はＡ→C′の分だけ少くてもゲートをスイ
ツチさせることができる。磁束は電流とインダク
タンスの積であるから入力信号電流を一定とすれ
ば、スイツチに必要な磁束の少なくなつた分だけ
ゲートのインダクタンスを減らすことができる。
従つてインダクタンスを構成する部分の専用面積
を少なくしてゲートの縮小化を図ることができ
る。
The DC bias magnetic field created by the magnetic material has the function of biasing the input signal as shown by 0→C in FIG. Thereby, when bias current I B is applied, the operating point is set at position C'. The gate is switched by taking the path C'→B according to the control signal I C. Therefore, the gate can be switched even if the magnetic flux generated by the input signal current is as small as A→C'. Since magnetic flux is the product of current and inductance, if the input signal current is constant, the gate inductance can be reduced by the amount of magnetic flux required for the switch.
Therefore, it is possible to reduce the area dedicated to the portion constituting the inductance, thereby reducing the size of the gate.
またゲートのスイツチング時間は制御信号ICが
第３図に示すしきい値曲線を横切るまでの時間を
短かくすることによつて短縮化できる。この時間
は磁性体による直流バイアスを行つたことにより
入力信号がＡ→C′の立上りに必要とした時間分だ
け短縮化されるので、ゲートの高速動作化が可能
である。 Furthermore, the gate switching time can be shortened by shortening the time it takes for the control signal I C to cross the threshold curve shown in FIG. Since this time is shortened by the time required for the input signal to rise from A to C' by applying a DC bias using a magnetic material, it is possible to operate the gate at high speed.
〔実施例〕 以下、本発明の実施例を図面により説明する。〔Example〕 Embodiments of the present invention will be described below with reference to the drawings.
第１図は磁性体によつて入力信号の直流バイア
スを与える量子干渉計回路の基本的な構成方法を
示す。同図において、符号１は基板、符号２は基
板絶縁層、符号３は接地面層、符号４，９、およ
び１１は層間絶縁層であり、磁性体８は下部電極
５、トンネル障壁層６、上部電極７および配線層
１０によつて構成される閉ループに鎖交する磁束
を与えるように設ける。その際、磁性体自身も閉
ループを構成し、磁性体の外部に磁束の洩れのな
い、すなわち磁化の閉じた構造にすることが望ま
しい。第１図中の・，×は磁化の向きを示す。こ
のような磁化の閉じた磁性体構造は基板面に平行
な一軸異方性を有する硬磁性体薄膜（例えばパー
マロイ、Co）などによつて実現することができ
る。 FIG. 1 shows a basic construction method of a quantum interferometer circuit that applies a DC bias to an input signal using a magnetic material. In the figure, 1 is a substrate, 2 is a substrate insulating layer, 3 is a ground plane layer, 4, 9, and 11 are interlayer insulating layers, and a magnetic material 8 is a lower electrode 5, a tunnel barrier layer 6, It is provided so as to provide a magnetic flux that interlinks with the closed loop formed by the upper electrode 7 and the wiring layer 10. In this case, it is desirable that the magnetic body itself constitutes a closed loop and that there is no leakage of magnetic flux to the outside of the magnetic body, that is, that the magnetization is closed. . and × in Fig. 1 indicate the direction of magnetization. Such a magnetic structure with closed magnetization can be realized by a hard magnetic thin film (for example, permalloy, Co) having uniaxial anisotropy parallel to the substrate surface.
次に、直流バイアス磁界（第３図０→Ｃ）の設
定値を決めたときに、これを実現するための磁性
体パターンの設計は、磁性体のＢ−Ｈ曲線を用い
て行われる。第４図は磁性体のＢ−Ｈ曲線の一例
である。同図でBSは飽和磁化を示し、これは磁
性体中の自発磁化MSに等しい。今、第３図の直
流バイアス０→Ｃを与える磁束をφとすれば、磁
性体の断面積Ｓが、
Ｓ＝φ／MS (1)
となるように磁性体のパターン寸法設計を行えば
良い。 Next, when the set value of the DC bias magnetic field (0→C in FIG. 3) is determined, the magnetic material pattern for realizing this is designed using the B-H curve of the magnetic material. FIG. 4 is an example of a B-H curve of a magnetic material. In the figure, B S indicates saturation magnetization, which is equal to spontaneous magnetization M S in the magnetic material. Now, if the magnetic flux that gives the DC bias 0→C in Figure 3 is φ, then if the pattern dimensions of the magnetic material are designed so that the cross-sectional area S of the magnetic material becomes S=φ/M S (1) good.
若干の設計例を以下に示す。例えば、磁性体と
してパーマロイを用いた場合、MS＝1.08〔Wb／
m2〕であるから、バイアス磁束φをφ0／２に設
定すると、式(1)よりパーマロイの断面積Ｓは0.9
×10-3μm2となる。従つてパーマロイの蒸着膜厚
を10nmとすれば、パターン幅を0.1μmに設計す
れば良い。 Some design examples are shown below. For example, when permalloy is used as the magnetic material, M S = 1.08 [Wb/
m 2 ], so if the bias magnetic flux φ is set to φ 0 /2, the cross-sectional area S of permalloy is 0.9 from equation (1).
×10 -3 μm 2 . Therefore, if the permalloy vapor deposition film thickness is 10 nm, the pattern width may be designed to be 0.1 μm.
ここで磁性体を用いて入力信号の直流バイアス
を行つた場合、磁性体のある部分の磁界Ｂは入力
信号電流によつて生じた磁界Ｈによりμ0H（μ0は
真空の透磁率）だけしか増加しない。すなわち入
力信号電流源から見たゲートのインダクタンスを
考える際には、磁性体のある部分も透磁率μ0の物
質で置き換えて良い。このため磁性体があるため
にインダクタンスが増加し、結果として回路の動
作が遅くなることはない。以上が磁性体により直
流バイアス磁界を与えたジヨセフソン回路の基本
的構成方法である。 If a magnetic material is used to apply a DC bias to the input signal, the magnetic field B in a certain part of the magnetic material will be reduced by μ 0 H (μ 0 is the magnetic permeability of vacuum) due to the magnetic field H generated by the input signal current. only increases. That is, when considering the inductance of the gate as seen from the input signal current source, a certain portion of the magnetic material may also be replaced with a material with magnetic permeability μ 0 . Therefore, the presence of the magnetic material does not increase the inductance and, as a result, slow down the operation of the circuit. The above is the basic construction method of a Josephson circuit in which a DC bias magnetic field is applied using a magnetic material.
次に上記直流バイアスの方法を用いた応用実施
例を以下に示す。第一の応用実施例は３接合量子
干渉計ゲートの構成である。第５図は３接合量子
干渉計ゲートの等価回路を示す。同図において×
印はジヨセフソン接合素子、Ｌ１，Ｌ２は閉ルー
プを構成するインダクタンス、Ｌ３，Ｌ４は入力
信号線のインダクタンスであり各々Ｌ１，Ｌ２と
磁気的に結合している。Rdはダンピング抵抗で
ある。第６図は３接合量子干渉計ゲートの代表的
なしきい値特性の一例を示す。第３図に示した２
接合量子干渉計ゲートに比べてしきい値の谷間
（フロアーと呼ばれる）を深くかつ広く取ること
ができるため、より動作マージンの広いゲートの
回路設計が可能である。３接合量子干渉ゲートは
ジヨセフソン接合および超電導インダクタにより
２つの閉ループを構成しており入力信号電流によ
り通常、同じ向きの磁束が各ループに鎖交するよ
うな設計を行う。３接合量子干渉計ゲートの場合
も直流バイアスの与え方は２接合量子干渉計ゲー
トと同様の考えで行うことができる。第７図は磁
性体を用いた直流バイアスの与え方の一例を示
す。３接合干渉計ゲートの場合、通常２つの磁性
体を用いて直流バイアスを設定する。同図のφ1，
φ2は各磁性体の保持する磁束である。このとき
各ループを鎖交する磁束はφ1，φ2−φ1となる。
従つて例えば回路定数の対称なゲートを構成する
場合、φ2＝2φ1となるような設計を行えば良い。
磁性体の膜厚は通常一定であるからφ2を与える
磁性体パターンの幅を２倍にすれば上記目的を達
成することができる。このように磁性体を用いて
直流バイアスを与える場合、２つの磁性体のパタ
ーン幅を適当に選ぶことによつて２つの閉ループ
に任意の直流バイアスを設定することが可能であ
る。 Next, an application example using the above DC bias method will be shown below. The first application example is a three-junction quantum interferometer gate configuration. FIG. 5 shows an equivalent circuit of a three-junction quantum interferometer gate. In the same figure ×
The mark is a Josephson junction element, L1 and L2 are inductances forming a closed loop, and L3 and L4 are inductances of input signal lines, which are magnetically coupled to L1 and L2, respectively. R d is the damping resistance. FIG. 6 shows an example of typical threshold characteristics of a three-junction quantum interferometer gate. 2 shown in Figure 3
Compared to a junction quantum interferometer gate, the threshold valley (called a floor) can be made deeper and wider, so it is possible to design a gate circuit with a wider operating margin. A three-junction quantum interference gate is designed such that two closed loops are formed by a Josephson junction and a superconducting inductor, and magnetic flux in the same direction is usually linked to each loop depending on the input signal current. In the case of a three-junction quantum interferometer gate, the DC bias can be applied in the same way as the two-junction quantum interferometer gate. FIG. 7 shows an example of how to apply a DC bias using a magnetic material. In the case of a three-junction interferometer gate, two magnetic bodies are typically used to set the DC bias. φ 1 in the same figure,
φ 2 is the magnetic flux held by each magnetic body. At this time, the magnetic fluxes interlinking each loop are φ 1 and φ 2 −φ 1 .
Therefore, for example, when constructing a gate with symmetrical circuit constants, it is sufficient to design such that φ 2 =2φ 1 .
Since the film thickness of the magnetic material is usually constant, the above objective can be achieved by doubling the width of the magnetic material pattern that provides φ 2 . When applying a DC bias using magnetic materials in this manner, it is possible to set arbitrary DC biases to the two closed loops by appropriately selecting the pattern widths of the two magnetic materials.
次に第二の応用実施例として上記直流バイアス
方法を用いたゲートを使用したスレーブフリツプ
フロツプの構成例を示す。第８図はスレーブフリ
ツプフロツプの回路図である。同図８０１，８０
２は磁性体で直流バイアスを与えた３接合量子干
渉計ゲート、８０３，８０４は２重巻きの入力信
号線を設けた３接合量子干渉計ゲート、８０５は
交流電源からの給電抵抗、８０６は負荷抵抗、８
０７は交流電源である。スレーブフリツプフロツ
プでは２つの３接合量子干渉計ゲートに直流バイ
アスを与える必要がある。本実施例ではこの直流
バイアスを磁性体で与えることが可能となつた。 Next, as a second applied example, a configuration example of a slave flip-flop using a gate using the above DC bias method will be shown. FIG. 8 is a circuit diagram of a slave flip-flop. Same figure 801, 80
2 is a three-junction quantum interferometer gate with a magnetic material and a DC bias, 803 and 804 are three-junction quantum interferometer gates with double-wound input signal lines, 805 is a power supply resistance from an AC power supply, and 806 is a load. resistance, 8
07 is an AC power supply. In the slave flip-flop, it is necessary to apply a DC bias to the two three-junction quantum interferometer gates. In this embodiment, it has become possible to apply this DC bias using a magnetic material.
以上示したごとく本発明によれば、磁性体によ
り直流バイアスを与えることによつて、量子干渉
計ゲートを構成するインダクタンスを小さくする
ことができるのでゲートの専有面積を縮小化しか
つその動作速度を速くする効果があり、ジヨセフ
ソン集積回路の高集積、高速動作化に有効であ
る。第９図は本発明の効果の一例を定量的に示す
図である。同図ａは磁性体による入力信号のバイ
アス率とゲートのインダクタ構成部分の専用面積
の縮小率との関係、同図ｂは入力信号のバイアス
率とゲートのスイツチング時間との関係を示す。
同図よりバイアス率を上げるに従つてゲートの専
有面積を縮小化し、かつ動作速度を高速化できる
ことが分つた。
As described above, according to the present invention, the inductance constituting the quantum interferometer gate can be reduced by applying a DC bias using a magnetic material, thereby reducing the exclusive area of the gate and increasing its operating speed. This has the effect of increasing the degree of integration and high speed operation of Josephson integrated circuits. FIG. 9 is a diagram quantitatively showing an example of the effect of the present invention. Figure a shows the relationship between the bias rate of the input signal due to the magnetic material and the reduction rate of the area dedicated to the inductor component of the gate, and Figure b shows the relationship between the bias rate of the input signal and the switching time of the gate.
It is clear from the figure that as the bias rate is increased, the area occupied by the gate can be reduced and the operating speed can be increased.
さらに実施例に示したごとく、本発明によれば
従来信号入力インダクタンスを介して直流電源に
より与えていた入力信号バイアスを磁性体を挿入
するだけで、しかも磁性体のパターン幅を変える
ことにより任意のバイアス設定が可能となつた。
またバイアス信号入力を行うためのパツドおよび
配線を行う必要がないため、回路設計も容易であ
る。 Furthermore, as shown in the embodiments, according to the present invention, the input signal bias, which was conventionally given by a DC power supply via a signal input inductance, can be changed by simply inserting a magnetic material, and by changing the pattern width of the magnetic material. Bias setting is now possible.
Furthermore, since there is no need to provide pads and wiring for inputting bias signals, circuit design is also easy.
もう１つの本発明の効果として磁性体を用いる
ことによつて極めて変動の少ない直流バイアスを
提供できることがあげられる。第１０図は磁性体
の自発磁化MSの温度変化を示す。一般にMSは温
度を下げるに従つて増大する。しかしキユーリー
点TCに対してTC／２以下の温度ではその変化は
極めて小さく、特にジヨセフソン集積回路を動作
させるような極低温下ではMSの変化は1K当り
0.01％以下である。このことは磁性体による直流
バイアス方法が、温度の変化に対して極めて変動
の少ないバイアスを与えることを意味するもので
ある。 Another effect of the present invention is that by using a magnetic material, it is possible to provide a DC bias with extremely little fluctuation. FIG. 10 shows the temperature change of the spontaneous magnetization M S of the magnetic material. Generally, M S increases as the temperature is lowered. However, at temperatures below T C /2 with respect to the Curie point T C , the change is extremely small, and especially at extremely low temperatures such as those at which Josephson integrated circuits are operated, the change in M S is approximately 1 K.
Less than 0.01%. This means that the direct current bias method using a magnetic material provides a bias that is extremely stable against changes in temperature.
第１図は本発明による磁性体を用いた直流バイ
アスの基本的構成を示す断面図、第２図は２接合
量子干渉計ゲートの等価回路図、第３図は２接合
量子干渉計ゲートのしきい値特性図、第４図は磁
性体のＢ−Ｈ曲線、第５図は３接合量子干渉計ゲ
ートの等価回路図、第６図は３接合量子干渉計ゲ
ートのしきい値特性図、第７図は本発明の一実施
例の磁性体を用いて直流バイアスを行つた３接合
量子干渉計ゲートの構成を示す断面図、第８図は
本発明の一実施例の磁性体を用いて直流バイアス
を行つたゲートを使用したスレーブフリツプフロ
ツプの構成図、第９図は本発明の効果の一例を定
量的に示す図、第１０図は磁性体の自発磁化の温
度依存性の一例を示す図である。
１…基板、２…基板絶縁層、３…接地面層、
４，９，１１…層間絶縁層、５…下部電極、６…
トンネル障壁層、７…上部電極、８…磁性体、１
０，１２…配線層。
Fig. 1 is a sectional view showing the basic configuration of a DC bias using a magnetic material according to the present invention, Fig. 2 is an equivalent circuit diagram of a two-junction quantum interferometer gate, and Fig. 3 is an equivalent circuit diagram of a two-junction quantum interferometer gate. Threshold characteristic diagram, Figure 4 is the B-H curve of a magnetic material, Figure 5 is an equivalent circuit diagram of a 3-junction quantum interferometer gate, Figure 6 is a threshold characteristic diagram of a 3-junction quantum interferometer gate, Fig. 7 is a cross-sectional view showing the structure of a three-junction quantum interferometer gate that uses a magnetic material according to an embodiment of the present invention to provide a DC bias, and Fig. 8 shows a structure in which a DC bias is applied using a magnetic material according to an embodiment of the present invention. A configuration diagram of a slave flip-flop using a biased gate, FIG. 9 is a diagram quantitatively showing an example of the effect of the present invention, and FIG. 10 is an example of the temperature dependence of spontaneous magnetization of a magnetic material. FIG. 1... Substrate, 2... Substrate insulating layer, 3... Ground plane layer,
4, 9, 11... interlayer insulating layer, 5... lower electrode, 6...
Tunnel barrier layer, 7... Upper electrode, 8... Magnetic material, 1
0, 12...Wiring layer.
１ レーザー管が外套管及びこれの内部に挿入さ
れたセラミツクス製のプラズマ放電管からなる金
属蒸気レーザー発振装置において、前記プラズマ
放電管を、円筒状外管部とこの外管部内にスライ
ド可能に嵌合された円管状内管部とで構成すると
ともに、前記内管部を軸方向に所要間隔で分割さ
れた複数個の分割体により構成し、各分割体の内
周面に、金属蒸気発生用の金属小片を係止させる
ための環状凹部を、軸方向に多数設けてなること
を特徴とする金属蒸気レーザー発振装置。
２ 前記各分割体が、熱歪に強く電気絶縁性の良
い材料、例えば窒化硼素、酸化アルミニウム、窒
1. In a metal vapor laser oscillation device in which a laser tube is composed of an outer tube and a ceramic plasma discharge tube inserted into the outer tube, the plasma discharge tube is slidably fitted into a cylindrical outer tube portion and into this outer tube portion. The inner tube part is composed of a plurality of divided bodies divided at required intervals in the axial direction, and the inner circumferential surface of each divided body is provided with a metal vapor generating plate. A metal vapor laser oscillation device characterized in that a large number of annular recesses are provided in the axial direction for locking small metal pieces. 2 Each of the divided bodies is made of a material that is resistant to thermal strain and has good electrical insulation properties, such as boron nitride, aluminum oxide, and nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62067790A JPS63234571A (en) | 1987-03-24 | 1987-03-24 | Josephson integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62067790A JPS63234571A (en) | 1987-03-24 | 1987-03-24 | Josephson integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63234571A JPS63234571A (en) | 1988-09-29 |
| JPH0529152B2 true JPH0529152B2 (en) | 1993-04-28 |
Family
ID=13355099
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62067790A Granted JPS63234571A (en) | 1987-03-24 | 1987-03-24 | Josephson integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63234571A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5710753B2 (en) * | 1974-10-23 | 1982-02-27 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5710753U (en) * | 1980-06-20 | 1982-01-20 |
-
1987
- 1987-03-24 JP JP62067790A patent/JPS63234571A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5710753B2 (en) * | 1974-10-23 | 1982-02-27 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63234571A (en) | 1988-09-29 |
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