JPH05291425A - Semiconductor package and its production - Google Patents

Abstract

PURPOSE:To maintain junction parts under excellent conditions by using package constituting components that have specific thermal expansion coefficients so as to be conformed. CONSTITUTION:The board ratio of Cu/Mo/Cu of the clad material for a base board 11 is 1:3:1-1:1:5'. The thermal expansion coefficients of the clad material, a cap 16 and glass 13 are 6.0-6.8 (X10<-6>/ deg.C), 6.3-7.4 (X10<-6>/ deg.C) and 7.1 (X10<-6>/ deg.C). The thermal expansion coefficients of a wind frame 15 and a lead frame 12 are 6.2 (X10<-6>/ deg.C), and the greatest common measure for the conformity of the thermal expansion coefficients of the members is calculated. A leak on the glass 13 is prevented and the excellent conditions are maintained for the junction parts between the members by using the cap 16, wind frame 15, lead frame 12 and the glass 13 which have the thermal coefficients of 6.0-7.5 (X10<-6>/ deg.C).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sardip type semiconductor package in which a lead frame is glass-welded to a base substrate for bonding semiconductor chips, and a method for manufacturing the same.

[0002]

2. Description of the Related Art Generally, this type of semiconductor package is
As shown in FIG. 6, the lead frame 2 is glass-welded to the alumina ceramic base substrate 1 with the low-melting glass 3, the semiconductor chip 4 is bonded to the base substrate, and wire bonding is performed. The glass 3 is glass-welded and hermetically sealed.

In order to improve heat dissipation, Japanese Patent Laid-Open No. 3-8362 discloses a base material using a clad material of Cu and an iron-based metal or a brazed product. Of the clad materials,
As a three-layer clad material which can be manufactured by a relatively simple method, Invar / Cu / Invar or the like having an intermediate layer of Cu using Invar (Fe-Ni alloy) having a small coefficient of thermal expansion, or JP-A-58-67049 discloses a powder sintered material containing W or Mo and Fe, Ni, Cu as main components.

Further, as a semiconductor package for a high frequency device which requires heat dissipation, as shown in FIG. 7, Cu is used.
After the semiconductor chip 4 is joined to the semiconductor package in which the lead frame 2 is assembled by brazing to the frame 7 made of alumina ceramic in which the wiring layer is formed by W metallization using the -W alloy as the base substrate 6 and wire bonding is performed, generally, Kovar (Fe- It is solder-sealed with a Ni-Co) cap 8. Further, in the type in which the base substrate 6 and the frame 7 are brazed, a brazing material may flow on the chip bonding surface of the base during brazing, and chip bonding failure may occur. Therefore, as shown in FIG. 8, step processing is performed on the chip bonding surface of the base substrate 9 and the brazing surface.

[0005]

By the way, in recent years, Ga
With the spread of information communication devices using high-frequency elements such as As, the demand for semiconductor packages suitable for high-frequency elements that are inexpensive and have excellent heat dissipation is increasing. In response to this demand, the cerdip package using the alumina ceramics shown in FIG. 6 as a base substrate is inexpensive, but on the other hand, the heat radiation property higher than that of the alumina ceramics is required, and the characteristic impedance of the lead portion is controlled. Since it does not exist, it is not suitable for high frequency devices.
Further, there is a defect that the sealing temperature of glass sealing is high and it is not suitable for a GaAs element. In addition, in FIG.
The Cu-W alloy used for the base substrate is heavy and unfavorable for reducing the weight of electronic devices, the material itself is expensive, and steps and polishing are expensive, and the package plating is Au plating from the manufacturing process. Therefore, there is a drawback that it becomes expensive.

Therefore, the present invention has been made in view of the above-mentioned conventional drawbacks, and an object of the present invention is to provide a semiconductor device which is lightweight, inexpensive, excellent in heat dissipation, and suitable for a high frequency element. It is to provide a semiconductor package used for this.

[0007]

In order to achieve this object, a semiconductor package according to the present invention has a base substrate which is matched with thermal expansion of a semiconductor chip and has good heat conduction, which is lightweight, inexpensive and easy to process. A good Cu / Mo / Cu three-layer clad material is used. When the Cu / Mo / Cu clad material and the dissimilar material are joined at a high temperature such as brazing, deformation is likely to occur. Therefore, glass or an adhesive capable of joining at a low temperature is used. Further, the thickness of the glass or the adhesive and the lead size (width, thickness) are controlled, and the lead frame is made of a metal capable of matching the thermal expansion with the glass or the adhesive. Further, the wind frame is made of a base substrate, a metal capable of matching thermal expansion with glass, and a ceramic with metallization. In addition, the semiconductor device according to the present invention is such that only the portions necessary for die bonding, wire bonding, and sealing are Au plated, and then exterior plating is performed. Further, as the sealing cap, glass or metal capable of matching thermal expansion with the adhesive is used.

[0008]

In the present invention, the base substrate is made of Cu / Mo /
Since the clad material of Cu is used, the thermal expansion of the semiconductor chip can be matched, the thermal conductivity is good, and the weight and cost are low. Further, by assembling the package with glass or an adhesive, the base substrate can be made flat, which is lightweight and inexpensive, and deformation due to the assembly can be prevented. By controlling the glass thickness and the lead size (width, thickness), the characteristic impedance of the wiring portion is matched with the characteristic impedance of the semiconductor chip, which is suitable for a high frequency element. The Au plating is applied only to the necessary portions, and the Au coating is not applied to the glass or adhesive coating portions of the base substrate, the lead frame, and the wind frame, so that the adhesion with the glass or the adhesive is improved and the reliability is improved. Since metal or metallized ceramic is used for the wind frame, it can be sealed by soldering or seam welding and is suitable for GaAs devices.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a semiconductor package according to the present invention,
(A) is a side sectional view, (b) is an overall perspective view before mounting the cap, FIG. 2 also shows a base substrate, (a) is a plan view, (b) is a side sectional view, and FIG. 3 is also a base. The manufacturing method of a board | substrate is shown, (a) is a sectional side view, (b) is a whole perspective view, FIG. 4 similarly shows the manufacturing method of a wind frame,
(A) is a side sectional view and (b) is an overall perspective view.

In these figures, reference numeral 11 denotes a base substrate, which is composed of a three-layer clad material of Cu / Mo / Cu. As for the method of plating the base substrate 11, when the outer shape of the base substrate 11 is small as in the present invention, the barrel method is used after processing to a predetermined size, but the plating by the parrel method is not precise. Therefore, in this embodiment, the rack method is used for plating. However, since plating by the rack method requires electrode removal, workability deteriorates if plating is performed after processing to a predetermined size. For this reason, in this embodiment, Ni plating 18 is applied to the entire surface of a large member that has not been processed to have a predetermined size, and then punching is performed to have a predetermined size, as shown in FIG. At this time, the side surface of the stamped base substrate 11 becomes the base material, but as described later, since the exterior plating with Sn is applied, a metal layer is formed and problems such as corrosion do not occur. After the Ni plating 18 is applied, masking is performed so that only the chip bonding portion is exposed, and Au plating 19 is applied.

Reference numeral 15 is a wind frame made of a metal of 45 alloy (Fe-Ni system). For the same reason as the method of manufacturing the base substrate 11 described above, the manufacturing method of the wind frame 15 is as follows. First, as shown in FIG. Only the upper surface, which is the surface, is Au-plated, and the joint portion of the glass 13 is not Au-plated. Au
After applying the plating 19, it is punched to a predetermined size. Also in this case, the side surface is the base material. The wind frame 15 may be made of ceramics. In this case, first, a metal powder such as tungsten or molybdenum is printed on the surface of the unfired ceramics, and it is fired at the same time as the ceramics to be metalized. , Metallization ensures solder wettability.

The cap 16 is made of 45 alloy (Fe-Ni).
It is formed of a plate (NS-5). A lead frame 12 is made of a 45 alloy (Fe-Ni), and Au is spot-plated only on a wire bonding portion for electrical connection with the semiconductor chip 14. Base 11
And the lead frame 12, and the lead frame 12 and the wind frame 15 are welded by the low melting point glass 13.

After the encapsulation, exterior plating with Sn is applied. The degree of freedom in selecting the type of plating layer, which was limited to Au plating, because the influence of temperature when mounting a semiconductor element can be ignored compared to the case of performing exterior plating in advance by performing exterior plating after sealing. Will increase.

Further, an Au layer is applied to the surface portions of the chip joint portion of the base substrate 11, the wire bond portion of the lead frame 12 and the cap joint portion of the wind frame 15,
The surface of the bonding portion of the glass 13 of the base substrate 11 has A
Since the u layer is not applied, the base substrate 1 is removed by removing Au having poor wettability with glass or adhesive.
In No. 1, the adhesion with glass or adhesive is improved and reliability is increased.

Here, in the semiconductor package having the above structure, the low melting point glass 13 having the thermal expansion coefficient of 7.1 × 10 ⁻⁶ / ° C., the window frame 15, and the lead frame 12
45 alloy (Fe-Ni) is used, the thickness of the window frame 15 is 0.5 mm, the thickness of the lead frame 12 is 0.125 mm, and the thickness of the base substrate 11 is 0.5 mm.
mm, by changing the Cu / Mo / Cu plate thickness ratio,
A temperature cycle test of 65 ° C./175° C. × 20 cycles was performed to evaluate airtightness.

As a result, most of those having a plate thickness ratio of 1: 1: 1 failed to leak, but the plate thickness ratio was 1: 3 :.
No leakage failure occurred in the case of 1 to 1: 5: 1.
As shown in FIG. 9, when the plate thickness ratio is 1: 3: 1 to 1: 5: 1, the thermal stress to the glass is less than 2 kg / mm ² and the glass 13 leaks. This is because it is assumed that nothing will be done.

Further, Cu / Mo / Cu of the base substrate 11
Using a semiconductor package having a plate thickness ratio of 1: 5: 1, a 45 alloy (Fe-Ni) plate (NS-5) having a plate thickness of 0.125 mm and a Kovar (F
(e-Ni-Co) board was solder-sealed and the warpage after sealing was measured. As a result, the 45 alloy (Fe—Ni) plate did not warp, but the Kovar (Fe—Ni—Co) plate generated 10 μm / 14 mm warpage. In this semiconductor package, a 45 alloy (Fe-N
i) By using a plate, warpage due to sealing can be prevented and reliability is improved.

Here, the cap 16, the wind frame 15, and the lead frame 1 which constitute each part of the package.
By matching the thermal expansion coefficients of the glass 13, the glass substrate 13, and the base substrate 11, it is possible to prevent peeling at the joint portion of each constituent member and leakage failure of the mating member. Table 1 shows the coefficient of thermal expansion of the members used for the construction of each part of the package. As described above, the Cu / Mo / Cu plate thickness ratio is 1: 3:
It is the glass 13 that the clad material of 1 to 1: 5: 1 is used.
It is a necessary condition for preventing the leakage failure of No. 1, but the range of its thermal expansion coefficient is 6.0 to 6.8 (× 10 ⁻⁶ / ° C.).

[0019]

[Table 1]

The thermal expansion coefficient of the cap 16 is 6.3.
~ 7.4 (× 10 ^-6 / ° C), the thermal expansion coefficient of the wind frame 15 and the lead frame 12 is 6.2 (× 10 ^-6 / ° C)
℃), the thermal expansion coefficient of the glass 13 is 7.1 (× 10 ^-6 /
Therefore, considering the greatest common divisor for matching the thermal expansion coefficients of these members, the thermal expansion coefficients of the cap 16, the wind frame 15, the lead frame 12, and the glass 13 are 6.0 to 7.5 ( By using a material of × 10 ⁻⁶ / ° C.), it is possible to prevent the glass 13 from leaking and to keep the joint portion between the respective members in a good state. Instead of the glass 13, an adhesive made of resin mixed with a filler having a low coefficient of thermal expansion such as quartz glass may be used.

FIG. 5 shows a second embodiment of the present invention,
(A) is a side sectional view of a main part, and (b) is a plan view of a lead part. In these figures, the relative permittivity (εr) of 11.8
Glass thickness (B) between the base substrate 11 and the wind frame 15 using the low melting point glass 13 (catalog value)
The standing wave ratio (VSWR) was measured by changing the lead width (W) and the lead thickness (T). That is, the microstrip line 17 made of alumina ceramic having a characteristic impedance of 50Ω is joined to the package shown in FIG. 5 by solder, electrically connected by wire bond (A1 wire of φ20 μm), and measured using a network analyzer. In the measurement, VS which looks at the reflection characteristic in the RF characteristic
WR (S ₁₁ ) was used. The results are shown in Table 2.

[0022]

[Table 2]

The standing wave ratio (VSWR) is, for example, 50Ω.
When the impedance matching between the coaxial cable and the transmission line part of the package is not taken, the standing wave is the value obtained by dividing the maximum value of the voltage amplitude of this standing wave by the minimum value.
Generally, it is desirable that VSWR be 1.3 or less in a high frequency package. As shown in Table 2, when the wind frame 15 was made of alumina ceramics, a practical value of VSWR was obtained when the lead width (W) was about 0.33 mm. When the window frame 15 is made of metal, the thickness (B) of the glass 13 between the base substrate 11 and the window frame 15 is set to 0.6 mm, and the lead width (W) is set to 0.15 mm. Practical VS
The value of WR can be obtained.

In FIG. 10, the lead thickness (T) is 0.125.
If it is less than or equal to mm (0.1 mm in this embodiment), VS
It is the figure which showed the relationship of glass thickness (B) -relative permittivity ((epsilon) r) -lead width (W) for WR becoming 1.3.
In this figure, with the curves obtained by variously changing the lead width (W) as boundaries, the upper region shows VSWR of 1.3.
The areas are as follows: Being in this region is a practical condition, and the relative permittivity (ε
r) is 14 or less, the lead width (W) is set to 0.
When the thickness (B) of the glass is 2 mm or less and the thickness (B) of the glass is 0.6 mm or more, the thickness (B) of the glass can be a practical thickness for manufacturing.

After soldering with the cap 16,
The outer portions of the base substrate 11, lead frame 12, wind frame 15 and cap 16 are Sn-plated. Thus, by plating the exterior with Sn, it is possible to obtain a semiconductor device which is inexpensive, has excellent heat dissipation and is suitable for a high frequency element. The thicknesses of the base substrate, the wind frame, and the cap can be appropriately selected without being limited to the values in the embodiment, and solder plating is not limited to Sn as the exterior plating, and needless to say. That is not the case.

[0026]

As described above, according to the present invention, since the base substrate is made of the Cu / Mo / Cu clad material, which is capable of obtaining the thermal expansion and matching of the semiconductor chip and having good heat conduction, and is inexpensive, It is inexpensive and has excellent heat dissipation. In addition, Cu / Mo
Since the / Cu plate thickness ratio is selected to be 1: 3: 1 to 1: 5: 1, the thermal stress on the glass can be reduced, thereby preventing leakage failure. Furthermore, the coefficient of thermal expansion of each part constituting the package is 6.0 to 7.5 (× 10 ⁻⁶ /
It is possible to prevent warping and leak defects at the joints between each member by using the ones whose temperature is
The joint part can be maintained in a good state.

Further, by controlling the glass thickness and the lead size (width, thickness), the characteristic impedance matching with the semiconductor chip can be achieved, and the semiconductor package which is inexpensive and has excellent heat dissipation and which is suitable for a high frequency element can be provided. Obtainable. Further, since only the necessary portion is plated with Au, the adhesion between the base substrate and the glass is improved, and the reliability of the product is improved. Further, the base substrate and the wind frame are plated with Ni on the entire material, then Au is plated on the surface of the necessary portion, and then punched into a predetermined size, and finally the metal cap is joined to the wind frame. Since the outer plating is applied after the sealing, it is possible to produce a highly dense plating with high productivity.

[Brief description of drawings]

FIG. 1 shows a semiconductor package according to the present invention, (a)
Is a side cross-sectional view, and (b) is an overall perspective view with a cap removed.

FIG. 2 shows a base substrate of a semiconductor package according to the present invention, (a) is a plan view and (b) is a side sectional view.

3A and 3B show a method of plating a base substrate of a semiconductor package according to the present invention, wherein FIG. 3A is a side sectional view and FIG. 3B is an overall perspective view.

4A and 4B show a method of plating a wind frame of a semiconductor package according to the present invention, wherein FIG. 4A is a side sectional view and FIG.

5A and 5B show a second embodiment of a semiconductor package according to the present invention, FIG. 5A is a side sectional view of a main part, and FIG. 5B is a plan view of a lead part.

FIG. 6 is a side sectional view of a conventional semiconductor package.

FIG. 7 is a side sectional view of a fifth example of a conventional semiconductor package.

FIG. 8 is a side sectional view of a sixth example of a conventional semiconductor package.

FIG. 9 is a diagram showing changes in the maximum stress on glass with respect to the Cu / Mo / Cu plate thickness ratio of the clad material in the semiconductor package according to the present invention.

FIG. 10 shows a semiconductor package according to the present invention, in which V
It is the figure which showed the relationship of glass thickness-relative permittivity-lead width which makes SWR 1.3.

[Explanation of symbols]

 11 Base Substrate 12 Lead Frame 13 Low Melting Glass 14 Semiconductor Chip 15 Wind Frame 16 Cap 17 Microstrip Line 18 Ni Plating 19 Au Plating

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Reference number within the agency FI Technical indication location H01L 23/50 G 9272-4M (72) Inventor Isao Kitamura 8-1-1 Tsukaguchihonmachi, Amagasaki City, Hyogo Prefecture No. 1 Sanryo Electric Co., Ltd. Production Technology Laboratory (72) Inventor Masanobu Ohara 8-1-1 Tsukaguchihonmachi, Amagasaki City, Hyogo Prefecture Sanryo Electric Co., Ltd. Production Technology Laboratory (72) Inventor Mitsuyuki Takada Amagasaki, Hyogo Prefecture 8-1, 1-1, Honmachi, Tsukaguchi, Ichi

Claims (10)

[Claims] 1. A structure in which a lead frame is bonded to a base substrate to which a semiconductor chip is bonded by glass or an adhesive, and a window frame formed in a frame shape so as to surround the semiconductor chip is bonded by glass or an adhesive. In the above semiconductor package, a Cu / Mo / Cu three-layer clad material is used for the base substrate. 2. The semiconductor package according to claim 1, wherein the clad material has a Cu / Mo / Cu plate thickness ratio of 1: 3: 1 to 1: 5: 1. 3. The semiconductor package according to claim 2, wherein the glass or the adhesive has a coefficient of thermal expansion of 6.0 to 6.0.
It is 7.5 × 10 ⁻⁶ / ° C., and the thermal expansion coefficient of the lead frame and the wind frame is 6.0 to 7.5 × 10 ^−6.
A semiconductor package characterized by being a metal of / ° C. 4. The semiconductor package according to claim 2, wherein the wind frame is metallized alumina ceramics. 5. A lead frame is adhered to a base substrate to which a semiconductor chip is joined by glass or an adhesive, and a window frame made of metal and formed in a frame shape so as to surround the semiconductor chip is adhered by glass or an adhesive. In the semiconductor package constituted by, the glass or the adhesive has a relative dielectric constant of 14 or less, a lead thickness of 0.125 mm or less, and a thickness of 0.6 mm or more, and at least the glass or the window frame is made of glass or A semiconductor package having a lead width of 0.20 mm or less in a portion bonded with an adhesive. 6. A lead frame is bonded to a base substrate to which a semiconductor chip is bonded with glass or an adhesive, and a window frame made of metal and formed in a frame shape so as to surround the semiconductor chip is bonded with glass or an adhesive. In the semiconductor package configured as described above, an Au layer is applied to the surface portions of the chip joint portion of the base substrate, the wire bond portion of the lead frame and the cap joint portion of the wind frame, and Au of the surface portion of the glass of the base substrate or the adhesive application portion A semiconductor package having a layer removed. 7. The semiconductor package according to claim 6, wherein the entire base substrate material is plated with Ni, and then the surface portion of the chip bonding portion is plated with Au, and then processed into a base substrate having a predetermined size. A method of manufacturing a semiconductor package characterized by the above. 8. The semiconductor package according to claim 6, wherein the entire wind frame material is plated with Ni.
A method for manufacturing a semiconductor package, characterized in that a surface portion to which the cap is joined is subjected to Au plating, and then processed into a wind frame having a predetermined size. 9. A semiconductor package according to claim 7, wherein a semiconductor chip is mounted on the semiconductor package, a metal cap is bonded to a wind frame and sealed, and then external plating is applied. Production method. 10. The semiconductor device according to claim 9, wherein
A semiconductor package characterized in that a metal cap joined to a wind frame is a metal having a coefficient of thermal expansion of 6.0 to 7.5 × 10 ⁻⁶ / ° C., and the metal cap and a base substrate are electrically connected.