JPH05290600A - Method for testing memory - Google Patents

Abstract

PURPOSE:To provide a method for testing a memory correcting unevenness between the access operation of respective cells at each step without adding a special control circuit for changing a clock frequency. CONSTITUTION:As a test pattern for testing the function of the memory, a march pattern is used which includes the write step of a back ground writing (1) or (0) successively to individual cell of the memory and other step reading storage information from individual cell of the memory successively and comparing it with a required value and succeedingly writing the inverted information of the required value to the same cell. At this time, the march pattern is constituted so that the number of times of access performed to individual cell at the write step of the back ground and the number of times of access performed to individual cell at other step are the same plural number of times.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory test method for functionally testing a memory.

[0002]

2. Description of the Related Art A writable / readable LSI memory (RA
Various test patterns have been developed in order to perform the functional test of M) [Reference (1) Tamamoto; "Testability Design Method in Memory", Information Processing, vol. 30, no.1
2, pp1467-1472 (1989), and reference (2) M, Franklin.
et al .: “Built-in self-testing of random-access
memories ", Computer, vol.123, no.10, pp45-56 (Oct.1
990)]. When the number of words that can be stored in the RAM is represented by N, the test patterns are classified into the following classes according to the test pattern length [see reference (1)]. N-based pattern (pattern length is proportional to N) N ^1.5-based pattern (pattern length is proportional to N ^1.5) N ² system pattern (pattern length is an example that Hisuru in N ²⁾ towards the long pattern is, It is capable of detecting various types of faults and has excellent fault detection capability, but it increases the test time. For this reason, N-type patterns having a short pattern length are used in the mass production stage.
Above all, the March pattern is often used as a standard pattern for functional tests because it can detect all fixed failures and has the highest failure detection rate among N-type patterns [References (2) and (3) Nikkei Micro. Device, pp53-62 (May
1987), document (4) H.M. Koike et.al .: “ABIST
scheme using microprogram ROM for large capaci
ty memories ", in Proc. International Test Con
ference, pp815-822 (Sept. 1990)]. Therefore, when the test circuit is mounted on the chip and the test is automatically performed inside the chip, it is necessary to use the march pattern in order to guarantee the same fault detection rate as the external test using the tester. However, the march pattern is a complicated pattern among the N-type patterns, and a complicated test circuit is required.

Here, the outline of the March pattern and the reason why a complicated test circuit is required will be clarified. Outline of March Pattern and Problems The execution procedure of the March pattern consists of the following 6 steps in total as shown in FIG. First step : The operation of W "0" for writing "0" to all cells is performed in order from the cell of the lowest address to the cell of the highest address (background "0" write). Second step : The following continuous read operation and write operation are sequentially performed from the cell of the lowest address to the cell of the highest address. That is, the stored information is read from the cell of interest, and it is checked whether the read result matches the expected value (correct value) "0" R "0"
Do the operation. Then, the operation of W "1" for writing "1" to the same cell is performed. Therefore, in this second step, the operation of R "0" -W "1" is performed. Third step : The following continuous read and write operations are performed in order from the highest address cell to the lowest address cell. That is, the stored information is read from the cell of interest, and the read result is the expected value “1”.
The operation of R "1" is performed to check whether or not Next, "0" is written in the same cell. Therefore, in this third step, the operation of R "1" -W "0" is performed. Fourth step : Writing "1" to all cells in order from the cell of the lowest address to the cell of the highest address (writing of background "1"). Fifth step : The following continuous read operation and write operation are sequentially performed from the cell of the lowest address to the cell of the highest address. That is, the stored information is read from the cell of interest, and it is checked whether the read result matches the expected value (correct answer value) “1”. Next, "0" is written in the same cell. Therefore, in this fifth step, the operation of R "1" -W "0" is performed. Sixth step : The following continuous read operation and write operation are sequentially performed from the cell of the highest address to the cell of the lowest address. That is, the stored information is read from the cell of interest and the read result is the expected value “0”.
Check for a match. Then, "1" is written in the same cell. Therefore, in this sixth step, the operation of R "0" -W "1" is performed.

A counter is used to generate an address, input data, control signal, etc. of a test circuit using a March pattern [Reference (4), Reference (5) S. K. Jain
et.al .: “Built-in self-testing of embedded memor
ies ", IEEE Design & Test of computers, vol.
3, no. 5, pp 27-37 (Oct. 1986), see) However, the output of the counter is not used as it is, and it is necessary to process the counter output in order to obtain a necessary signal. The reasons for this are listed below. In address generation, the 3rd and 6th steps are down-counting from the cell of the highest address to the cell of the lowest address, while in other steps, the cells of the lowest address are changed to the cells of the highest address. It is an up-count towards. In the background writing in the first step and the fourth step, the writing operation is continuous, but in the other steps, the reading operation and the writing operation are alternately performed. In background writing, each cell is selected once, whereas in other steps, each cell is selected twice in succession.

Regarding these, and can be solved by introducing a step designation address. This method has already been reported as an example of a circuit configuration for generating a checker board pattern, which is one type of memory test pattern [Reference (5)]. The step designation address is, as shown in FIG. 3, a 3-bit signal assigned to each step to identify which step it is. That is, 6 from the first step to the sixth step
Six types of 3-bit signals from "000" to "101" are sequentially assigned to the steps. This step-designated address uses the counter output of the higher 3 bits than the counter output used to generate the most significant bit of the address. The method of generating the signal required for the march pattern is described in detail. If the step designation address is represented by S2, S1, S0 in order from the upper bit, the address Ai (i = 0 to N-1) and the write control signal WEN required in the march pattern are expressed by the following logic using the counter output. Can occur.

[Equation 1]

[Equation 2] Here, Ti: counter output (T0 is the least significant bit, T1, T2, ... Ascending sequentially in the following order) WEN: Write operation at low level, read operation at high level. Further, in the equations (1) and (2), “to” represents inversion (for example,
S2 is an inverted signal of S2),

[Outer 1] Represents exclusive OR.

[0006]

However, the above problem needs to be changed in the frequency of the clock for operating the counter, and cannot be solved only by processing the counter output. Therefore, as an example, as shown in FIG. 4, a configuration has been reported in which a clock frequency conversion circuit having the following two functions is added [reference (5)]. (1) A function for identifying which step it is (specifically, a function for confirming that the address has become the highest or lowest address). (2) A function of reducing the frequency of the clock supplied to the counter to 1/2 in the second, third, fifth, and sixth steps. FIG. 5 shows an example of the waveforms of the first and second steps when this configuration is used, taking the number of words N = 4 as an example. Certainly, the problem can be solved by using this configuration, but there is a problem that the amount of hardware increases due to the necessity of the clock frequency conversion circuit. For example, in the example of Document (5), a ROM storing microcode is used as the clock frequency conversion circuit, and about 150 transistors are used even if this ROM is configured.

An object of the present invention is to provide a memory test method which can solve the above problems without adding a special control circuit for changing the clock frequency.

[0008]

In order to achieve the above object, in the present invention, the background writing procedure is changed so that even in the first and fourth steps, individual cells are formed as many times as in the other steps. It uses the March pattern to access.

[0009]

By using the test pattern created according to the present invention, it is possible to perform the test at the same clock frequency for all steps. Therefore, no special control circuit for adjusting the clock frequency is required, and the amount of hardware is reduced as compared with the conventional type.

[0010]

FIG. 1 shows an embodiment of the present invention. The difference from the conventional example is that the same data is continuously written twice in the same cell at the time of background writing. In this way, the same cell is always accessed twice in succession over all steps, so there is no need to change the clock frequency depending on the step. Therefore, the frequency conversion circuit required in the conventional type is not necessary. The purpose of the background writing is to write "0" in the first step and "1" in the fourth step for all cells. Therefore, as shown in FIG. 1, in each of the first and fourth steps, 2
Performing the write operation continuously each time increases the time required for the test by 20%, but does not reduce the failure detection capability. Particularly, in the case of a RAM (built-in RAM) mounted on a custom LSI and used, the storage capacity is several tens.
Many of them are less than K words, and the test time is originally short. Therefore, a 20% increment does not pose any problem. Also, by mounting a test circuit, it is possible to test simultaneously with other blocks. In this case, the RAM test time often does not fall within the critical pulse of the test time of the entire custom LSI.

In the background writing step,
There are also the following advantages in writing data to individual cells twice in succession. When actually mounting a test circuit, the test enable signal TE is used to distinguish between the test mode and the normal operation mode. Here, let us consider a state where TE rises and enters the test mode. Here, it is assumed that there is a phase difference D as shown in FIG. 2 between the rising edge of the clock and the rising edge of TE. Further, the counter is assumed to be of a type that counts up each time the clock rises. Then, as shown in FIG.
The first cycle of steps is narrower than the other cycles. Therefore, if the conventional marching pattern is used, there is a possibility that the writing time for the least significant word cannot be secured sufficiently. To avoid this problem, the clock and T
It is necessary to add a limiting condition to the timing at which E rises. This control condition complicates the test procedure. However, in the test pattern of the present invention, writing is continuously performed twice for each cell. Therefore, for the lowest word, even if the sufficient write time cannot be secured in the first cycle, a sufficient write time can be secured in the second cycle. Therefore, there is no need to set any restrictions on the timing at which the clock and TE rise.

The concept of the present invention is not limited to the case of performing the operation twice consecutively, as shown below. In the literature [3], the marching pattern is improved in order to increase the failure detection rate. In this improved marching pattern, one cell is continuously accessed three times (read operation → write operation → read operation) in the second, third, fifth, and sixth steps. Even in such a case, the idea of the present invention is used to realize an improved march pattern generation circuit without using a frequency conversion circuit, by individually accessing each cell three times in the first and fourth steps. You can Also,
The number of steps is not limited to six, and the march pattern can be defined to include more steps.

[0013]

As described above, by using the memory Tethospatan produced according to the present invention, it is possible to reduce the amount of hardware required for generating a test pattern while maintaining a high fault detection capability.

[Brief description of drawings]

FIG. 1 is a diagram showing a test pattern used in an example of the present invention.

FIG. 2 is a signal waveform example diagram for explaining an advantage of the present invention.

FIG. 3 is a test pattern diagram used in a conventional test method.

FIG. 4 is a diagram illustrating a conventional test circuit configuration example.

FIG. 5 is a waveform example diagram of a conventional test circuit configuration.

[Explanation of symbols]

 WEN write control signal A0, A1 address signal

Claims (1)

[Claims] 1. As a test pattern for functional testing of a memory, a background writing step of sequentially writing "1" or "0" to individual cells of the memory, and sequentially storing information from individual cells of the memory. In a method of testing a memory using a marching pattern, which comprises reading and comparing with an expected value and subsequently writing the inverted information of the expected value to the same cell, in the background writing step, the individual cells are written to the individual cells. A method of testing a memory, characterized in that a march pattern is used, wherein the number of times of access performed to the individual cells and the number of times of access to the individual cells in the other step are the same.