JPH05289632A - Active matrix substrate - Google Patents

Abstract

PURPOSE:To provide the active matrix substrate which eliminate the superposition of a clock signal on a scanning control signal controlling scanning lines and prevents a logic circuit from malfunctioning at the time of the matrix driving of a switching element which controls applied voltages to plural pixel electrodes. CONSTITUTION:A scanning line driving circuit 10 which constitutes the active matrix substrate consists of a shift register circuit composed of analog switches 11, 14, 15, and 18 and inverters 12, 13, 16, and 17, and buffers 19 and 20, and a control line 13 through which the scanning line control signal is transmitted is connected to a 1st clock signal line 1 and a 2nd clock signal line 2 through capacitors 21 and 22 respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for a display panel of a liquid crystal television receiver, a word processor, a computer terminal display device, etc., and is driven by a matrix by driving electrodes divided into a plurality of picture element units. The present invention relates to an active matrix substrate for applying a voltage to a substance such as a liquid crystal whose optical property is changed.

[0002]

2. Description of the Related Art FIG. 4 is a plan view showing a schematic structure of an active matrix substrate 50 which is a premise of the present invention, and FIG. 5 is an active matrix substrate 50 and a counter substrate 5.
It is a schematic perspective view which shows arrangement | positioning of 8.

In the active matrix substrate 50, a plurality of picture element electrodes 52 and switching elements 53 for controlling the voltage applied to the picture element electrodes 52 are formed in a matrix on the surface of an insulating substrate 51.

A switching element 53 for selectively driving the pixel electrode 52 is a TFT (thin film transistor) element or a MOS.
A three-terminal element such as an FET (metal oxide semiconductor field effect transistor) element or a two-terminal element such as an MIM (metal-insulating layer-metal) element, a diode or a varistor is used.

When the switching element 53 is a three-terminal element, a plurality of data lines 54 and scanning lines 55 are formed in a grid pattern orthogonal to each other on the substrate on which the pixel electrodes 52 are formed. The source is connected to the data line 54, the gate is connected to the scanning line 55, the drain is connected to the pixel electrode 52, and as shown in FIG. 5, the counter substrate 58 is opposed to the pixel electrode 52 via a liquid crystal or the like. A counter electrode 56 that is uniform over the entire surface is formed. When performing color display, the color filters 57B, 57G, 57R are formed in a zigzag pattern.

When the switching element 53 is a two-terminal element, a plurality of scanning lines 55 are formed in parallel on the substrate on which the pixel electrodes 52 are formed, and one terminal of the two-terminal element is the scanning line 55, The other terminal is connected to each pixel electrode 52, and the counter substrate facing the pixel electrode 52 through a liquid crystal or the like is provided with a plurality of counter pixel electrodes corresponding to each pixel and a plurality of parallel connecting them. Data lines are formed orthogonal to the scan lines.

In the active matrix system, when the number of scanning lines is m and the number of data lines is n, m × n picture element electrodes can be matrix-driven by time-divisionally scanning these. Generally, a dot-sequential driving method of sequentially transferring display data for each picture element or a line-sequential driving method of sequentially transferring display data for each scanning line is used.

Hereinafter, as shown in FIG. 4, an example in which the switching element 53 is a three-terminal element will be described.

A portion of the active matrix substrate 50 has a first clock signal line 61 and a second clock signal line 6 through which first and second clock signals having opposite phases are transmitted.
2 and a logic circuit 60 for generating a scanning line control signal for transmitting the driving timing of each scanning line 55 using each clock signal.
Are formed. The logic circuit 60 includes a scanning line driving circuit 70 that controls an applied voltage for each scanning line, and the like, a power supply line 65 and a ground line 64 that supply a constant voltage to each scanning line driving circuit 70, and each scanning. A control line 63 for transmitting a scanning line control signal is formed between the line drive circuits 70, and the first clock signal line 61 and the second clock signal line 6 are formed.
2, the control line 63, the power supply line 65, and the ground line 64 are electrodes 61a, which are formed at the ends of the active matrix substrate.
62a, 63a, 65a, 64a are respectively connected.

FIG. 6 shows an example of a conventional scanning line drive circuit 70. To the first clock signal line 61 and the second clock signal line 62, two-phase clock signals φ1 and φ2 having opposite phases as shown in FIGS. 3 (1) and 3 (2) are transmitted, respectively. The scanning line control signal STP for transmitting the driving timing of the scanning line is transmitted to the control line 63 from the preceding scanning line driving circuit.

The operation of the scanning line drive circuit 70 will be described. The analog switch 71, 74, 75, 78 and the inverters 72, 73, 76, 77 constitute a shift register circuit, and the scanning line control signal STP is controlled from the preceding stage. When one pulse is input through the line 63, the clock signal φ1
Becomes H (high level), the analog switch 71 becomes conductive, is input to the inverter 72, and outputs L (low level). At this time, the inverter 73 outputs H, but since the clock signal φ2 is L, the analog switches 74 and 75 are in the cutoff state.

Next, when the clock signal φ1 is inverted to L and the clock signal φ2 is inverted to H, the analog switch 71 is turned on.
Is turned off and the analog switches 74 and 75 are turned on, whereby the input of the inverter 72 is held at H and L is input to the inverter 76, the output becomes H, and the inverter 77 outputs L. Therefore, the scanning line control signal STP transmitted by the control line 63 connected to the scanning line driving circuit of the next stage becomes H, and outputs H to the scanning line 55 via the buffers 79 and 80, and the scanning line 55 is output. The switching element 53 connected to 55 is made conductive.

Next, when the clock signal φ1 is inverted to H and the clock signal φ2 is inverted to L, the analog switch 7
1, 78 are turned on and the analog switches 74, 75 are turned off, the input of the inverter 76 is held at L, the scanning line control signal STP to the next stage is held at H, and the scanning from the previous stage is performed. When the line control signal STP becomes L, L is input to the inverter 72 and its output becomes H.

Next, when the clock signal φ1 is inverted to L and the clock signal φ2 is inverted to H, the analog switch 7
When the analog switches 74 and 75 are turned on and the analog switches 74 and 75 are turned on, H is input to the inverter 76, the scanning line drive signal STP to the next stage becomes L, and the switching element connected to the scanning line 55. 53 is shut off.

In this way, the scanning line control signal ST from the preceding stage
When a pulse that is H at the rising edge of the clock signal φ1 and becomes L at the next rising edge is input as P, a pulse having a time width of one clock cycle is output to the scanning line 55 and the scanning of the next stage is performed. In the line driver circuit, a similar pulse is delayed by one clock cycle and a similar pulse is output to the scan line, so that the logic circuit 60 can sequentially scan each scan line every one clock cycle. The conduction time of each switching element is set in the range of 15 μsec to 100 μsec.

FIG. 7 shows a scanning line driving circuit 70 shown in FIG.
FIG. 6 is a front view showing a part of a conductor near an input portion of the shift register circuit of FIG. A portion 90 surrounded by a two-dot chain line in FIG.
Corresponds to a portion 90 surrounded by a two-dot chain line in FIG. 6, the conductors of the first clock signal line 61 and the second clock signal line 62 are formed in parallel, and the first clock signal line 61
Of the second clock signal line 62 intersects with the conductor of the second clock signal line 62 via the insulating film, and the scanning line control signal ST
The conductor of the control line 63 through which P is transmitted intersects with the insulating film. The conductor wiring structure is a metal film-insulating film-metal composed of a lower metal film made of Ta, Al, etc., an insulating film made of SiN _x , SiO ₂ , etc., and an upper metal film made of Ti, Mo, etc. It is formed by a three-layer structure of the film, as shown in FIG.
, The first clock signal line 61 and the second clock signal line 61
The clock signal line 62 is wired by the lower metal film, and when the branch of the first clock signal line 61 intersects with the second clock signal line 62, the clock signal line 62 is wired by the upper metal film through the contact hole 82 and further contacted. A hole 63 connects to the lower metal film. Similarly, the control line 63 is wired by an upper metal film and capacitively coupled with the first clock signal 61 via the insulating film to generate a coupling capacitance 81 in the crossing region of the perspective portion, which is connected to the analog switch 71. .

[0017]

However, in the conventional scanning line driving circuit, the occurrence of the intersection region between the clock signal line and the scanning line cannot be avoided in the active matrix system in which the scanning lines are sequentially driven.

The analog switches, inverters, and the like that form the scanning line drive circuit 70 are generally formed in the same circuit form as the switching elements that control the pixel electrodes.
Especially when a TFT or a MOSFET is used as a switching element, the control line 63 has a high impedance because the ON resistance of the analog switch 71 is relatively high. Therefore, the control line 63 is in a state where signals from other conductors are easily mixed in. When capacitively coupled to the first clock signal line 61, the clock signal φ1 is added to the scanning line control signal STP as shown in FIG. 3C. However, there is a problem that the logic circuit 60 malfunctions due to the abnormal pulse generated by superimposing the pulse waveform of the above.

In order to solve the above-mentioned problems, an object of the present invention is to clock a scanning line control signal for controlling a scanning line when matrix-driving a switching element for controlling a voltage applied to a plurality of pixel electrodes. An object of the present invention is to provide an active matrix substrate capable of eliminating signal superposition and preventing malfunction of a logic circuit.

[0020]

According to the present invention, a plurality of picture element electrodes and switching elements for controlling a voltage applied to the picture element electrodes are formed in a matrix on an insulating substrate. A plurality of scanning lines for driving the first clock signal line, the first clock signal line and the second clock signal line through which the first and second clock signals having opposite phases are transmitted, and the first and second clock signals. In an active matrix substrate on which a logic circuit for generating a scanning line control signal for transmitting the scanning line driving timing is formed, the conductors for transmitting the scanning line control signal are the conductors of the first clock signal line and the second clock signal line. The active matrix substrate is characterized in that each is capacitively coupled with a conductor.

[0021]

According to the invention, the conductors for transmitting the scanning line control signal are capacitively coupled to the conductors of the first clock signal line and the conductors of the second clock signal line, respectively, so that one clock signal is coupled to the other. Even if it is superimposed on the scanning line control signal via the capacitor, another clock signal having an opposite phase is superimposed on the scanning line control signal via the other coupling capacitor, so that the superimposed clock signal can be canceled. Therefore, it is possible to prevent the occurrence of abnormal pulses.

[0022]

1 is a circuit diagram of a scanning line driving circuit 10 constituting an active matrix substrate according to an embodiment of the present invention. The configuration of the scanning line drive circuit 10 is similar to that shown in FIG. 6, and analog switches 11, 14, 15, 18 are provided.
And a shift register circuit including inverters 12, 13, 16 and 17, and buffers 19 and 20, and includes a first clock signal line 1 and a second clock signal line 2.
To the control line 3, the scanning line control signal STP for transmitting the driving timing of the scanning line is transmitted from the scanning line driving circuit in the preceding stage. It is different from the conventional one in that a coupling capacitance 22 is formed between the control line 3 and the second clock signal line.

Each analog switch 11, 14, 15, 1
8. The active elements constituting the inverters 12, 13, 16, 17 and the buffers 19, 20 have the same element configuration as the switching elements for controlling the pixel electrodes in order to simplify the manufacturing process of the active matrix substrate. preferable.

The operation of the scanning line drive circuit 10 is the same as that described above, and a pulse which is H at the rising edge of the clock signal φ1 and is L at the next rising edge is input as the scanning line control signal STP from the previous stage. When done, clock 1
A pulse having a time width corresponding to one cycle is output to the scanning line 5, and the scanning line driving circuit in the next stage outputs a similar pulse to the scanning line with a delay of one clock cycle.
The logic circuit 60 can sequentially scan each scanning line in each clock cycle.

By transmitting the video signal corresponding to each picture element through the plurality of data lines 54 in synchronization with the scanning of each scanning line, a two-dimensional display of an image can be performed.

FIG. 2A is a front view showing a part of the conductor in the vicinity of the input part of the shift register circuit of the scanning line driving circuit shown in FIG. 1, and FIG. 2B is shown in FIG. ) A-A '
FIG. A part 3 surrounded by a two-dot chain line in FIG.
0 corresponds to a portion 30 surrounded by a chain double-dashed line in FIG. 1, and the wiring structure of the conductor is the same as that shown in FIG. 7 on the insulating substrate 31 such as glass or quartz. The lower metal film 32 made of Ta, Al or the like is formed by sputtering, the insulating film 33 made of SiN _x , SiO ₂ or the like is formed by plasma CVD, and the upper metal film 34 made of Ti, Mo or the like is formed by sputtering or the like. It has a three-layer structure of metal film-insulating film-metal film as a whole, and the pattern of each layer is formed by plasma etching or the like. The analog switch 11 has the same structure as a switching element that controls the voltage applied to the pixel electrode, and is a gate electrode 11a made of Ta, Al, or the like.
And an insulating film 11b made of SiN _x , SiO ₂ or the like,
Functional film 11 made of amorphous Si, polycrystalline Si, or the like
c, and a source electrode 11d and a drain electrode 11e made of Ti, Mo or the like.

The first clock signal line 1 and the second clock signal line 2 are wired by a lower metal film, and the first clock signal line 1
When the branch of the crossing crosses the second clock signal line 2, it is wired to the upper metal film through the contact hole 23 and further connected to the lower metal film through the contact hole 24.
Similarly, the control line 3 is wired by an upper metal film and capacitively coupled with the first clock signal line via the insulating film, and a coupling capacitance 21 is generated in the crossing region of the perspective portion to be connected to the analog switch 11. At the same time, it branches off along the way and capacitively couples with the second clock signal line 2 via the insulating film, so that the coupling capacitance 22 is formed in the intersecting region of the perspective portion.

FIG. 3 is a timing chart showing the waveform of each signal of the scanning line drive circuit. Since the control line 3 and the first clock signal line 1 are capacitively coupled by the coupling capacitor 21, the pulse waveform of the clock signal φ1 is superimposed on the scanning line control signal STP transmitted to the control line 3, while the control line 3 Since the third clock signal line 3 and the second clock signal line 2 are capacitively coupled by the coupling capacitor 22, the clock signal φ2 having the opposite phase is superimposed on the scanning line control signal STP transmitted to the control line 3, and in the end, the clock signal φ1. And the superimposed pulse of the clock signal φ2 cancel each other out, and the scanning line control signal STP can maintain a normal pulse waveform (see FIG. 3 (4)). Therefore, it becomes possible to prevent malfunction of the logic circuit 60 due to abnormal pulse generation.

In the above embodiment, the control line 3 through which the scanning line control signal STP is transmitted is the first clock signal line 1
An example has been described in which capacitive coupling with the second clock signal line 2 and the second clock signal line 2 is performed at one location. However, capacitive coupling at each of two or more locations is possible. Pulse generation can be prevented as well.

Further, the present invention can be similarly applied to a display panel in which the switching element for controlling the voltage applied to the pixel electrode is a two-terminal element and the data line is formed on the counter substrate.

[0031]

As described in detail above, according to the present invention,
The conductor through which the scanning line control signal is transmitted is capacitively coupled to the conductor of the first clock signal line and the conductor of the second clock signal line, respectively, so that the superposition of the two clock signals is canceled out to prevent abnormal pulse generation. Therefore, the malfunction of the logic circuit can be reliably prevented with a simple configuration. Further, since the present invention can be realized only by modifying the shape of the conductor of the control line, it is possible to suppress an increase in manufacturing cost of the active matrix substrate.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a scanning line drive circuit that constitutes an active matrix substrate that is an embodiment of the present invention.

FIG. 2 is a front view showing a part of a conductor near an input portion of a shift register circuit of the scanning line driving circuit shown in FIG.

FIG. 3 is a timing chart showing the waveform of each signal of the scanning line drive circuit.

FIG. 4 is a front view showing a schematic configuration of an active matrix substrate which is a premise of the present invention.

FIG. 5 is a schematic perspective view showing an arrangement of an active matrix substrate and a counter substrate.

FIG. 6 is an example of a conventional scanning line drive circuit.

7 is a front view showing a part of a conductor near an input portion of a shift register circuit of the scanning line driving circuit shown in FIG.

[Explanation of symbols]

 1 1st clock signal line 2 2nd clock signal line 3 Control line 5 Scan line 10 Scan line drive circuit 11, 14, 15, 18 Analog switch 12, 13, 16, 17 Inverter 19, 20 Buffer 21, 22 Coupling capacitance 23 , 24 contact holes

Front page continuation (72) Inventor Hiroshi Fujiki 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (72) Yoshiharu Kataoka 22-22, Nagaike-cho, Abeno-ku, Osaka, Osaka Inside Sharp Corporation (72) Inventor Makoto Miyago, 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Prefecture

Claims (1)

[Claims] 1. A plurality of picture element electrodes and switching elements for controlling a voltage applied to the picture element electrodes are formed in a matrix on an insulating substrate, and a plurality of scans for driving the switching elements. Line, a first clock signal line and a second clock signal line through which first and second clock signals having opposite phases are transmitted, and scanning for transmitting drive timing of the scanning line using the first and second clock signals In an active matrix substrate on which a logic circuit for generating a line control signal is formed, a conductor through which the scanning line control signal is transmitted is capacitively coupled to a conductor of a first clock signal line and a conductor of a second clock signal line. An active matrix substrate characterized by the above.