JPH05284528A - Video signal reproducing device - Google Patents

Abstract

PURPOSE:To obtain a noiseless output picture in the case of changing the mechanical position of a reproducing head to perform tracking even at the time of special reproducing with respect to the video signal reproducing device of a VTR where the color line sequence is changed in fields to record plural segments. CONSTITUTION:The synchronizing signal of a reproduced video signal is detected by a synchronizing signal detecting circuit 4 to discriminate a field, and the reproduced video signal subjected to A/D conversion is written in a field memory 6 independently of fields, and it has the time base converted and is read out, and the field discrimination signal of the output of the synchronizing signal detecting circuit 4 has the time base operated in the same manner as the video signal of the field memory 6 to obtain a color line sequence discrimination signal, and the reproduced video signal is decoded based on the color line sequence discrimination signal by a decoder 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a special reproduction of a magnetic recording / reproducing apparatus which divides a video signal into a plurality of tracks and records the video signal. The video signal is effective when the mechanical position of the reproduction head is changed to follow the track. Reproduction device

[0002]

2. Description of the Related Art In a magnetic recording / reproducing apparatus (hereinafter abbreviated as VTR), when reproducing a video signal recorded on a recording track of a magnetic tape, a reproducing head is on-track on the recording track for reproduction scanning. Therefore, tracking control is required.

As a method that has been put into practical use, a reproducing head is mounted on an electro-mechanical conversion element composed of a piezoelectric element or the like, and the mechanical position of the head is adjusted so that the reproducing envelope signal amount reproduced by the reproducing head is maximized. Is changed to make the track follow. In this method, the mechanical position of the reproducing head is predicted from the control signal recorded in the longitudinal direction of the magnetic tape, and the mechanical position of the reproducing head is changed according to the reproduction envelope amount. In special reproduction, the track is made to follow by controlling the shake amount of the reproducing head according to the speed.

However, recently, segment recording in which one drum is divided into a plurality of tracks for recording by increasing the number of rotations of the drum cylinder due to widening of a recording signal is becoming mainstream. When it comes to segment recording like this,
The track width tends to be narrowed in consideration of the recording capacity.
In such a narrow track, crosstalk from an adjacent track increases, so that the H arrangement of recording tracks is becoming complicated.

For example, when a video signal of one frame is divided into 2 channels and 6 segments and recorded, the color signal is Pr.
Signals and Pb signals are line-correlated through a vertical filter and line-sequentially switched to Pr / Pb for each line for recording, and at least in the same segment, color line sequence with other channels is made the same to prevent crosstalk between channels. It is decreasing. At this time, if the number of effective lines included in one segment is odd, the color line sequence is inverted for each segment, and if the number of segments per field is odd, the color line sequence is inverted for each field. Further, in segment recording, in many cases shuffling is performed in consideration of the S / N ratio, dropout and the like.

Below, in a video signal of one frame,
A conventional video signal reproducing apparatus which inverts the color line sequence of the color signal for each field, divides into 2 channels 6 segments, and performs line shuffling to reproduce the recorded video signal will be described.

FIG. 7 is a block diagram of a conventional video signal reproducing apparatus, in which 1 is an input terminal for a reproduced video signal, 2 is an input terminal for a field reference signal, and 3 is an analog-digital converter (hereinafter referred to as A / D conversion). The horizontal sync signal and the segment sync signal of the reproduced video signal inputted to the input terminal 1 are detected and outputted, and the segment and field of the reproduced video signal are discriminated and outputted as a field discrimination signal. Sync signal detection circuit, 6 is a field memory for writing and deshuffling the output of the A / D converter 3, 7
Is a memory for creating a control signal for controlling the field memory 6 from the horizontal synchronizing signal output from the synchronizing signal detecting circuit 4, the segment synchronizing signal, the field discriminating signal, and the field reference signal input to the input terminal 2 of the field reference signal. A control circuit 9 is a decoder for returning the output of the field memory 6 to the original color line sequence in accordance with the field reference signal.
Reference numeral 0 is a digital-analog converter (hereinafter abbreviated as D / A converter) for converting the output of the decoder 9 into digital-analog, and reference numeral 11 is an output terminal of the D / A-converted signal.

The operation of the video signal reproducing apparatus configured as described above will be described below. A reproduction video signal as shown in FIG. 11 is input to the reproduction video signal input terminal 1. This signal is an example of a signal called a time axis compression multiplexed signal (TCI signal), and as shown in FIG. 10, a color signal and a luminance signal are time axis compression multiplexed on one horizontal line. In the case of this conventional example, since the color signal portion is color line sequential recording, P
b / Pr and one line are alternately inserted. 12
The H sequence of this conventional example is shown in FIG. In this conventional example, one frame is divided into two channels and divided into six segments and recorded, and the color signals are line-correlated through Pr and Pb signals through vertical filters, respectively, and they are switched line by line with Pr / Pb for each line. After recording, at least in the same segment, the color line sequence with other channels is the same. Further, since the number of effective lines included in one segment is odd, the color line sequence is inverted for each segment, and since the number of segments per field is 3, the color line sequence is inverted for each field.

The reproduced video signal input to the input terminal 1 is A
A / D converted by the / D converter 3 into digital data,
It is input to the field memory 6. On the other hand, the reproduced video signal is input to the sync signal detection circuit 4 and
The horizontal synchronizing signal and the segment synchronizing signal of the reproduced video signal are separated by, and the segment discriminating signal and the field discriminating signal in the field are created from the separated segment synchronizing signal. The field reference signal input to the input terminal 2 and the horizontal sync signal, the segment sync signal, the segment discrimination signal, and the field discrimination signal output from the sync signal detection circuit 4 are input to the memory control circuit 7 and are necessary for controlling the field memory 6. Create a signal. The digital data input to the field memory 6 is deshuffled by the field memory 6 and then input to the decoder 9. Decoder 9
Then, the color line sequence is restored according to the field discrimination signal. At this time, for example, since the Pr signal appears only for each line, the line without the Pr signal is interpolated and output from the upper and lower two lines. The Pb signal is processed similarly to the Pr signal. Next, the signal data output from the decoder 7 is D /
Input to the A converter 10, D / A converted, and output terminal 11
Will be output.

Next, the operation of the memory control circuit 7 will be described in more detail with reference to FIG. FIG. 8 is an internal configuration diagram of the memory control circuit 7, which includes 41, 42, 43, 44.
Are input signal terminals for receiving the output signals of the sync signal detection circuit 4, and 41 are segment sync signal input terminals, 4
2 is a segment discrimination signal input terminal, 43 is a horizontal synchronization signal input terminal, and 44 is a field discrimination signal input terminal. Reference numeral 45 is a field reference signal input terminal, 46 is a write clock generation circuit for generating a memory write clock, 47 is a memory write control signal generation circuit for generating a memory write control signal, and 48 is a read for generating a memory read clock. A clock generation circuit, 49 is a memory read control signal generation circuit that creates a memory read control signal, 50 is a write / read switching signal generation circuit that generates a control signal for switching between memory write and read control signals, and 51. Is a switch, and 52 is a memory control signal output terminal.

A write clock output from the write clock generation circuit 46, a segment sync signal which is a reference signal for a write segment, a horizontal sync signal which is a reference signal for one horizontal line for writing, and a segment in one field for writing. The segment discrimination signal indicating the number is input to the memory write control signal generation circuit 47, and the memory write control signal generation circuit 47 creates a control signal necessary for writing to the memory. It should be noted that the segment sync signal is used as a reference signal, and after writing valid lines by the number of valid lines of the segment, writing is held until the next segment sync signal arrives. On the other hand, the read clock output from the read clock generation circuit 48 and the field reference signal input to the field reference signal input terminal 45 are input to the memory read control signal generation circuit 49 to create a control signal necessary for reading the memory. .. The above-mentioned memory write control signal and memory read control signal are sent to the switch 51.
To the write / read switching signal generation circuit 50.
It is switched by the control signal of the output of, and is output from the memory control signal output terminal 52 as a memory control signal.

The write / read switching operation will be described in more detail with reference to the timing chart of FIG.

The memory of this conventional example has a memory capacity of 2 frames, and handles 1 field as 1 unit for a total of 4 units. The unit of each memory is memory 1,
When memory 2, memory 3 and memory 4 are displayed, the timing chart of writing and reading of each memory during normal reproduction is as shown in FIG. The write timing of each memory is created from the frame signal obtained by dividing the field reference signal by 1/2 and the field discrimination signal output from the sync signal detection circuit 4, and the read timing is created from the frame signal and the field reference signal. There is. In this conventional example, since the shuffling is performed in the field and recorded on the tape, the deshuffling operation is performed in the memory. Therefore, in terms of the field unit, the write side and the read side of the memory are delayed by two fields.

[0014]

However, in the above-mentioned conventional structure, the mechanical position of the reproducing head is changed in accordance with the tape speed, and control is performed so as to continuously track in the field direction in the forward direction along the longitudinal direction of the tape. In normal reproduction, there is no problem because the cycle of the field discrimination signal is the same as the cycle of the field reference signal. In addition, as described above, the memory write switching signal is created from the frame signal and the field discrimination signal, and the memory 1 and the memory 3 are switched.
The first field is controlled to be written in the memory 2 and the second field is written in the memory 4, and a switching signal for reading the memory is created from the field reference signal and the frame signal and is read regardless of the field discrimination signal. Therefore, the color line sequence of the video signal can be read out without change even in the special reproduction.

However, in the special reproduction, when the period of the field discrimination signal is tripled as shown in FIG. 10, for example, even though the video signal is written in the order of the memory 4-memory 3, the memory 3-memory. As the video signal is read out in the order of 4, the delay amount between the input signal of each memory and the output signal of the memory is not constant, the time axes of the input signal and the output signal are switched, and the desired output image is displayed. There was a problem that they could not get it.

The present invention is intended to solve the above-mentioned conventional problems, and it is possible to obtain a noise-free output video signal in the special reproduction of a VTR in which the color line sequence is recorded by reversing each segment in the multi-segment recording. It is an object of the present invention to provide a video signal reproducing device that can be used.

It is another object of the present invention to provide a video signal reproducing apparatus capable of correctly restoring the original video signal without color inversion even if dropout occurs in the segment sync signal and the video signal portion during special reproduction.

[0018]

In order to achieve the above-mentioned object, a video signal reproducing apparatus of the present invention divides a video signal of one field or one frame into a plurality of tracks for segment recording, and a color line is used for each field. In magnetic recording in which the sequence changes, A that performs A / D conversion of the reproduced video signal
/ D converter, a field memory for writing the output of the A / D converter, a horizontal synchronizing signal of the reproduced video signal, 1
Separate the segment sync signal that indicates the beginning of the track,
A synchronizing signal discriminating circuit for discriminating a segment and a field from the segment synchronizing signal and outputting a first field discriminating signal, and a second field reference for phase-synchronizing the input first field reference signal with the segment synchronizing signal. A control signal for the field memory is created from a phase synchronization circuit that outputs as a signal, the first field reference signal, the second field reference signal, and a horizontal synchronization signal and a segment synchronization signal output from the synchronization signal determination circuit. Of the field memory, a memory control circuit for controlling the field memory, a delay circuit for delaying the first field discrimination signal according to a delay amount of an input / output signal by the field memory and outputting it as a color line sequential discrimination signal, Return the read output signal to the original color line sequence according to the color line sequence determination signal. A decoder, the output of the decoder; and a D / A converter for converting D / A.

A segment detection determination circuit for determining whether or not the segment synchronization signal can be detected by inputting the segment synchronization signal output from the synchronization signal detection circuit and the first field reference signal, and the segment detection signal. A storage circuit that stores the first field determination signal for one cycle of writing in the field memory only for the segment having the segment synchronization signal that can be detected by the determination circuit; and the segment synchronization signal by the segment detection determination circuit. Of the segment which is not detected, the field discriminating signal stored in the storage circuit is switched, and the segment which can be detected by the segment detection discriminating circuit is switched to the first field discriminating signal. A switch for outputting as a field discrimination signal, and the second flap The field discrimination signal and the field reference signal are input, and the second field discrimination signal is time-axis converted according to the time axis conversion operation of the memory, and delayed by the delay amount of the input signal and the output signal of the memory. And a color line sequential discrimination signal generator for outputting as a color line sequential discrimination signal.

Further, a line memory for delaying the output of the A / D converter by one line and a field discrimination signal of the output of the sync signal detection circuit are superimposed on a horizontal blank portion of the output of the line memory, and the field memory is The field discrimination signal superimposing circuit as the input signal of, and the dropout signal and the horizontal synchronizing signal of the output of the synchronizing signal detecting circuit as an input signal, the horizontal line in which the dropout signal exists is detected, and the horizontal line A dropout line conversion circuit that outputs a second dropout signal to the entire valid signal portion, a second dropout signal that is an output of the dropout line conversion circuit, and a memory write control signal that is an output of the memory control circuit are input. And write to the field memory when the second dropout signal is detected. And a memory output signal read from the field memory as an input signal, the field discrimination signal superimposed on the horizontal blank portion of the output signal of the field memory is detected, and the color line sequential discrimination is performed. And a field determination circuit for outputting as a signal.

[0021]

According to the present invention, according to the above-mentioned structure, when the special reproduction is carried out by the video signal reproducing apparatus, the first signal inputted by the phase synchronization circuit is inputted.
The field reference signal is synchronized with the segment sync signal output from the sync signal detection circuit to create a second field reference signal, and the memory control circuit changes the memory write switching signal based on the second field reference signal. A switching signal for reading the memory is generated based on the first field reference signal to control the field memory, and the video signal read from the field memory is input to the decoder, and the decoder outputs the video signal. The first line discriminating signal of the output is delayed by the delay device by the delay amount of the input / output signal of the field memory, and the color line sequence is discriminated and controlled by the color line sequence discriminating signal, and the color line sequence is restored and output. There is.

When the segment sync signal cannot be detected due to dropout or the like, writing of the video signal of the segment having the segment sync signal is prohibited, and the segment sync signal is detected by the segment detection judgment circuit. Only when it is judged whether it is possible or not and the detection is possible, the first field discrimination signal of the output of the synchronization signal detection circuit is stored in the storage unit, and the segment synchronization determination circuit cannot detect the segment synchronization signal. A segment is switched to a field discriminating signal stored in the storage circuit, and a segment for which a segment sync signal can be detected by the segment detecting and discriminating circuit is switched to the first field discriminating signal by a switch.
The second field discrimination signal output from the switch is input to the color line sequential discrimination signal generating circuit, and the second field discrimination signal is time-axis converted according to the time axis conversion operation of the field memory to be a color line sequential discrimination signal. The video signal input to the decoder and output from the field memory is decoded by the decoder based on the color line sequential determination signal.

Further, when a dropout occurs in the video signal, the output of the A / D converter is delayed by one line in the video signal in the line memory, and the horizontal blank portion of the output of the line memory in the field discrimination signal superposition circuit. The field discriminating signal output from the sync signal detecting circuit is superposed on, the horizontal line in which the dropout signal exists is detected by the dropout line converting circuit, and the second dropout signal is applied to the entire effective signal portion of the horizontal line. The field discriminating signal which is output and inhibits writing to the field memory when the second dropout signal is detected by the inhibiting circuit, and which is superimposed on the horizontal blank part of the output signal of the field memory by the field determining circuit. Detected,
It is output as a color line sequential discrimination signal, and the decoder decodes it based on the color line sequential discrimination signal output from the field determination circuit.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION In the following, in a 1-frame video signal, the color line sequence of color signals is inverted field by field, divided into 2 channels and 6 segments, and line shuffling is performed to reproduce a recorded video signal. The video signal reproducing device will be described.

FIG. 1 is a block diagram of a video signal reproducing apparatus according to the first embodiment of the present invention. 1 is an input terminal for a reproduced video signal, 2 is an input terminal for a first field reference signal,
Reference numeral 3 is an A / D converter, and 4 is a sync signal detection for detecting and outputting a horizontal sync signal and a segment sync signal of the reproduced video signal inputted to the input terminal 1 and for producing a segment discrimination signal and a first field discrimination signal. Circuit 5 is input terminal 2
The phase synchronization circuit which synchronizes the first field reference signal input to the terminal with the segment synchronization signal and outputs it as the second field reference signal, 6 is a field memory, 7 is a horizontal synchronization signal, a segment synchronization signal, and a segment discrimination signal , A memory control circuit for creating a control signal for the field memory 6 from the first field reference signal and the second field reference signal, 8 delays the first field discrimination signal output from the sync signal detection circuit 4 by the field memory 6 Delay circuit that delays by the amount and outputs as color line sequential discrimination signal,
Reference numeral 9 is a decoder for decoding the video signal data read from the field memory 6 according to the color line sequential discrimination signal, 10 is a D / A converter for D / A converting the output of the decoder 9, and 11 is an output terminal.

The operation of the video signal reproducing apparatus configured as described above will be described below.

The reproduced video signal input to the input terminal 1 is A
The data is input to the / D converter 3, A / D converted into digital data, and input to the field memory 6. Further, the reproduced video signal is input to the sync signal detection circuit 4, and the sync signal detection signal 4 separates the horizontal sync signal and the segment sync signal,
A segment discrimination signal and a first field discrimination signal are created and output. On the other hand, the first field reference signal input to the input terminal 2 is input to the phase synchronization circuit 5, is phase-synchronized with the segment synchronization signal output from the synchronization signal detection circuit 4, and is output as the second field reference signal. It First
The field reference signal, the second field reference signal, the horizontal sync signal, the segment sync signal, and the segment discrimination signal output from the sync signal detection circuit are input to the memory control circuit 7, and the memory control circuit 7 creates the memory control signal. ..
The internal structure of the memory control circuit 7 is the same as that of FIG. 8 and the operation thereof is the same as that of the conventional example, but the first field discrimination signal is not input to the field discrimination signal input terminal of FIG. Inputting a signal is different from the conventional example. The memory control signal output from the memory control circuit 7 is input to the field memory 6 and controls the writing and reading of the field memory 6. In the case of the present embodiment, the reproduced video signal is line shuffled in field units, and the line memory is line deshuffled in field units in order to restore it. Further, the first field discrimination signal output from the synchronization signal detection circuit 4 is input to the delay circuit 8 and delayed by the amount of the video signal data delayed by the field memory 6 and output as a color line sequential discrimination signal. The video signal data output from the field memory 6 and the color line sequential discrimination signal are input to the decoder 9. The video signal data is returned to the original color line sequence by the color line sequential discrimination signal, and the D / A converter 10 performs D / A conversion. Converted and output.

FIG. 4 is a timing chart at the time of normal reproduction in this embodiment. In this embodiment as well, as in the conventional example, the memory has a memory capacity of 2 frames and handles one field as one unit for a total of four units. The units of each memory are shown as memory 1, memory 2, memory 3, and memory 4. The control of the read memory in this embodiment is the same as that of the conventional example, but the write memory switching operation is performed in the conventional example in a frame obtained by dividing the first field discrimination signal and the first field reference signal by 1/2. The switching signal for writing the memory is generated from the signal, whereas the present embodiment is different from the conventional example in that it is generated from the second field reference signal and the frame signal. The timing of normal reproduction in this embodiment is the same as that of the conventional example because the color line sequential discrimination signal coincides with the first field reference signal as shown in FIG.

FIG. 5 is a timing chart of slow reproduction in this embodiment. In the present embodiment, the reproducing head is controlled so that the mechanical position is changed according to the tape speed and the tracking is continuously performed in the forward direction of the longitudinal direction of the tape in field units. Therefore, the cycle of the first field discrimination signal is the tape speed. However, the phase of the change point of the field is in phase with the rising or falling edge of the second field reference signal. In the present embodiment, as described above, the memory switching of the write control signal is performed by creating the write switching signal from the second field reference signal and the frame signal, and the memory read switching is switched between the frame signal and the first signal. Since it is created from the field reference signal,
The operation of the memory in the slow reproduction is the same as that in the normal reproduction. Therefore, the time required from the writing to the memory to the reading is the same in each memory unit as in the normal reproduction, so that the time axis of the video signal data output from the memory is not switched.

However, when the memory is controlled as described above, the period of the first field discrimination signal does not match the second field reference signal in slow reproduction and changes depending on the tape speed, so that it is written in each memory. The field of the video signal changes with time, and the color line sequence in the read output of the memory does not always match the field reference signal as in normal reproduction. Therefore, the first to determine the field of the reproduced video signal when writing to the memory
The field discrimination signal of 1 is transmitted to the read side of the memory using the delay circuit 8, and the color line sequential is restored by controlling the decoder 9 using it as the color line sequential discrimination signal.

Therefore, according to this embodiment, the memory performs deshuffling processing regardless of the field of the reproduced video signal, and the phase difference between the input signal of the memory and the output signal of the memory is constant regardless of the field, and the reproduced video signal is reproduced. The field information of the signal is delayed as a color line sequential determination signal and transmitted to a decoder that restores the video signal read out from the memory by delaying it by a certain amount, so that the color line sequence is not mistaken and the time axis does not change. It is possible to obtain

In this embodiment, in order to create the second field reference signal, the field reference signal and the segment sync signal are synchronized to create the second field reference signal. However, instead of the segment sync signal, It goes without saying that a reproducing head switch signal may be used.

In the present description, slow reproduction has been described as an example, but it goes without saying that the same effect can be obtained even in * 1 or more special reproduction.

FIG. 2 is a block diagram of a video signal reproducing apparatus according to the second embodiment of the present invention.

Reference numeral 20 is a segment sync signal output from the sync signal detection circuit 4 and the first field reference signal input to the input terminal 2 as input signals, and determines whether or not the segment sync signal of each segment can be detected. Segment detection determination circuit for determination, 21 is a segment detection determination circuit 20
The storage unit for storing the first field discrimination signal output from the synchronization signal detection circuit 4 only for the segment having the segment synchronization signal that was detectable in step 22. The segment detection determination circuit 20 cannot detect the segment synchronization signal. The segment discriminating signal stored in the storage unit 21 is switched to the field discriminating signal stored in the memory 21, and the segment detecting circuit 20 is switched to the first field discriminating signal for the segment in which the segment sync signal can be detected as the second field discriminating signal. The switching device 23 for outputting receives the second field discrimination signal and the first field reference signal as input, and according to the time axis conversion operation of the field memory 6, the second field discrimination signal is time axis converted and the field memory 6 The input signal and output signal are delayed by the delay amount and output as the color line sequential discrimination signal. Line is a sequential determination signal generator. In addition, the same reference numerals are given to those performing the same operation as in the first embodiment.

The operation of the video signal reproducing apparatus configured as described above will be described below.

The reproduced video signal input to the input terminal 1 is A
The data is input to the / D converter 3, A / D converted into digital data, and input to the field memory 6. Further, the reproduced video signal is input to the sync signal detection circuit 4, and the sync signal detection signal 4 separates the horizontal sync signal and the segment sync signal,
A segment discrimination signal and a first field discrimination signal are created and output. Further, the segment synchronization signal output from the synchronization signal detection circuit 4 is input to the segment detection determination circuit 20, which determines whether the segment synchronization signal can be detected and outputs it. The first field discriminating signal output from the sync signal detecting circuit 4 is input to the storage unit 21 only for the segment which can be detected by the segment detecting and determining circuit 20, and is stored for one writing cycle of the field memory 6. The output of the storage unit 21 and the first field discrimination signal are input to the switching unit 22. If the segment detection / determination circuit cannot determine, the output of the storage unit 21 is selected, and if the determination is possible, the field determination signal is switched. , As the second field discrimination signal. On the other hand, the first field reference signal input to the input terminal 2 is input to the phase synchronization circuit 5, is phase-synchronized with the segment synchronization signal output from the synchronization signal detection circuit 4, and is output as the second field reference signal. It The first field reference signal, the second field reference signal, the horizontal sync signal output from the sync signal detection circuit, the segment sync signal, and the segment discrimination signal are input to the memory control circuit 7, and the memory control circuit 7 outputs the memory control signal. create. The memory control signal output from the memory control circuit 7 is input to the field memory 6 and
Controls writing and reading of. In the case of this embodiment, the reproduced video signal is shuffled in field units, and is deshuffled in the memory 6 in field units. At this time, if the sync signal detection circuit 4 cannot detect the segment sync signal, writing is prohibited for all the segments. The above-described write-inhibited segment is read again from the segment read one cycle before in the field memory 6 according to the read control signal output from the memory control circuit 7. Also, the switching device 2
The second field discrimination signal of the output of No. 2 is input to the color line sequential discrimination signal generation circuit 23, the second field discrimination signal is time-axis converted according to the time axis conversion operation of the field memory 6, and the input of the field memory 6 is performed. The signal and the output signal are delayed by the delay amount and output as a color line sequential determination signal. The video signal data output from the field memory 6 and the color line sequential discrimination signal are input to the decoder 9, and the video signal data is restored to the original color line sequence by the color line sequential discrimination signal, and D / A
It is D / A converted by the converter 10 and output.

Next, in this embodiment, the operation in the case where the segment sync signal cannot be detected will be described in more detail with reference to the timing chart of FIG.

As described above, the video signal of the segment for which the segment detection signal cannot be detected by the segment detection / judgment circuit 20 is prohibited from being written, and is written to the field memory 6 which was to be written one cycle before. The video signal is read again. In this embodiment, since the field memory 6 operates with two frames as one cycle, the video signal written two frames before becomes the video signal of the segment for which the segment detection / judgment circuit 20 cannot detect the segment synchronization signal. .. When special playback is performed,
Since the field two frames before does not always match the current field, only the segment for which the segment sync signal could not be detected is output from the memory 21 that stores the first field discrimination signal two frames before. By switching, the second field discrimination signal is created. Further, in the present embodiment, since the line deshuffling is performed in the field memory 6, the second field discrimination signal is converted in the time axis by the color line sequential discrimination signal generation circuit 23 in the same manner as the line deshuffling in the field memory 6. And output as a color line sequential determination signal. The shaded portion of the color line sequential discrimination signal in FIG. 6 indicates that the second field discrimination signal is not only delayed but also line deshuffled.

Therefore, according to the second embodiment, even if the segment sync signal cannot be detected due to dropout or the like, writing of the video signal of the segment for which the segment sync signal could not be detected is prohibited, and the field memory 6 is used. , The video signal read one cycle before is read again, and the color line sequential information of the video signal read from the field memory 6 stores the field discrimination signal in the memory 21 for one cycle of writing in the field memory 6. Then, the field discriminating signal of the output of the synchronizing signal detecting circuit 4 and the output of the memory 21 are switched depending on whether the segment synchronizing signal is detected or not, and input to the color line sequential discriminating signal generating circuit 23, and the time axis conversion operation of the field memory 6 is performed. According to the time axis conversion,
Since it is delayed by the delay amount of the input signal and the output signal of the field memory 6 and output as the color line sequential determination signal and is input to the decoder 9 to restore the color line sequential, the effect of the first embodiment is obtained. In addition, it is possible to prevent color inversion of the output signal when the segment sync signal is damaged.

Needless to say, it is better to interpolate the segment sync signal when the segment sync signal is damaged due to dropout or the like during normal reproduction.

FIG. 3 is a block diagram of a video signal reproducing apparatus according to the third embodiment of the present invention.

Reference numeral 30 denotes an input terminal for a dropout signal, 3
Reference numeral 1 is a line memory for delaying the digital signal A / D converted by the A / D converter 3 by one horizontal line. Reference numeral 32 is a horizontal line in which a dropout signal input to the input terminal 30 is present and the horizontal line is detected. A dropout line conversion circuit that outputs the entire valid signal period of the line as a second dropout signal, and 33 is a field discrimination signal that superimposes the field discrimination signal of the output of the synchronization signal detection circuit 4 on the horizontal blank portion of the output of the line memory 31. Superposition circuit, 34
Is a prohibition circuit that controls the memory write signal output from the memory control signal generation circuit 7 according to the second dropout signal to prohibit writing to the field memory 6, and 35 is a horizontal blank portion of the video signal read from the field memory 6. Is a field determination circuit that detects the field determination signal that is superimposed on and outputs it as a color line sequential determination signal. In addition, the same reference numerals are given to those performing the same operations as those of the first and second embodiments.

The operation of the video signal reproducing apparatus configured as described above will be described below.

The reproduced video signal input to the input terminal 1 is A
The data is input to the / D converter 3, A / D converted into digital data, input to the line memory 31, and delayed by one horizontal line. Further, the reproduced video signal is a sync signal detection circuit 4
The horizontal sync signal and the segment sync signal are separated by the sync signal detection signal 4 to generate and output the segment discrimination signal and the field discrimination signal. The video signal output from the line memory 31 is input to the field discrimination signal superimposing circuit 33. In the field discrimination signal superimposing circuit 33, the field discrimination signal output from the sync signal detecting circuit 4 is horizontally blanked in the video signal output from the line memory 31. The image data is superimposed and outputted on the other side, and is inputted to the field memory 6 as writing video signal data. The dropout signal input to the input terminal 30 is also input to the dropout line conversion circuit 32 together with the horizontal sync signal output from the sync signal detection circuit 4, and the dropout line conversion circuit 32 detects a horizontal line in which a dropout exists. Then, all the valid signals of the horizontal line are output as the second dropout signal. On the other hand, the field reference signal input to the input terminal 2 is input to the phase synchronization circuit 5 and the synchronization signal detection circuit 4
The phase is synchronized with the segment synchronization signal output from the output of the above, and is output as the second field reference signal. The field reference signal, the second field reference signal, the horizontal sync signal output from the sync signal detection circuit, the segment sync signal, and the segment discrimination signal are input to the memory control circuit 7, and the memory control circuit 7 creates a memory control signal. Memory control circuit 7
The output memory write control signal and the second dropout signal are input to the prohibition circuit 34, and when a dropout occurs, the prohibition circuit 34 writes to the field memory 6 based on the second dropout signal. Is prohibited, and the reading of the field memory 6 is controlled by the memory control circuit 7 as in the first and second embodiments. In the case of the present embodiment, the reproduced video signal is shuffled field by field, and the memory 6 is deshuffled field by field. Since the video signal is not newly written to the horizontal line in which the writing is prohibited, the video signal data of the line read one cycle before in the field memory 6 according to the read control signal output from the memory control circuit 7. Will be read again.
Next, the video signal read from the field memory 6 is input to the field determination circuit 35, and the field determination circuit 35 detects the field determination signal superimposed on the horizontal blank portion of the video signal, and color-sequentially detects it. Output as a discrimination signal. The video signal data output from the field memory 6 and the color line sequential discrimination signal are input to the decoder 9. The video signal data is restored to the original color line sequence by the color line sequential discrimination signal, and the D / A converter 10 performs D / A conversion. Converted and output.

Therefore, according to the third embodiment, when a dropout occurs in the video signal portion, the dropout line conversion circuit 32 for converting the line in which the dropout has occurred into the dropout for each line, and the A / D conversion. A line memory 31 for delaying the generated video signal by one line, a prohibition circuit 34 for prohibiting writing of the dropout line into the memory during the line, and a line memory 3
A field discrimination signal superimposing circuit 33 that superimposes field information on the horizontal blank portion of the output video signal of 1 is provided, and the field information is transmitted to the reading side of the field memory 6 for each horizontal line together with the video signal using the field memory 6. By detecting this and inputting it to the decoder 9 as a color line sequential discrimination signal and decoding it, it is possible to prevent color inversion of the output video signal even when dropout occurs. Note that in the case of normal reproduction, the field of the video signal for which dropout correction is performed can be easily predicted, so it is preferable to perform dropout correction in smaller data units instead of performing dropout correction in units of one horizontal line. Needless to say.

[0047]

As described above, according to the present invention, the deshuffling processing is performed in the field memory regardless of the field of the reproduced video signal, and the phase difference between the input signal of the field memory and the output signal of the field memory is independent of the field. It is fixed, and the field information of the reproduced video signal is delayed as a color line sequential determination signal by a certain amount and transmitted to the decoder that restores the video signal read from the field memory. It is possible to obtain slow replay images that are not replaced.

Further, even when the segment sync signal cannot be detected due to dropout or the like, writing of the video signal of the segment for which the segment sync signal cannot be detected is prohibited, and the video read one cycle before from the field memory. The signal is read again, the second field discrimination signal output from the switch is input to the color line sequential discrimination signal generation circuit, and the time axis conversion is performed according to the time axis conversion operation of the field memory. Is output as a color line sequential determination signal after being delayed by the delay amount of, and is input to the decoder to restore the color line sequence, so the color line sequence of the video signal read from the field memory is always the color line sequence. It is possible to prevent the color inversion of the output video signal when the segment synchronization signal is damaged in agreement with the discrimination signal.

Further, when a dropout occurs in the video signal, the field information is transmitted to the reading side of the field memory for each horizontal line together with the video signal using the field memory, and this is detected and used as a color line sequential discrimination signal. By inputting to the decoder and decoding, the video signal output from the field memory and the color line sequential discrimination signal match on all lines, and even if dropout occurs, color inversion of the output video signal is prevented. It is possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a video signal reproducing device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a video signal reproducing device according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a video signal reproducing device according to a third embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the normal reproduction memory according to the first embodiment of the present invention.

FIG. 5 is a timing chart for explaining the operation of the slow playback memory in the first embodiment of the present invention.

FIG. 6 is a timing chart for explaining the operation of the slow playback memory in the second embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a conventional video signal reproducing device.

FIG. 8 is a block diagram showing an internal configuration of a memory control circuit of a video signal reproducing device in a conventional example.

FIG. 9 is a timing chart for explaining the operation of the memory for normal reproduction in the conventional example.

FIG. 10 is a timing chart for explaining the operation of the slow-motion memory in the conventional example.

FIG. 11 is a waveform diagram showing an example of a conventional reproduced video signal.

FIG. 12 is a schematic diagram showing a state of H line on a conventional tape.

[Explanation of symbols]

 1 Playback Video Signal Input Terminal 2 Field Reference Signal Input Terminal 3 A / D Converter 4 Sync Signal Detection Circuit 6 Field Memory 7 Memory Control Circuit 8 Delay Circuit 9 Decoder 10 D / A Converter 20 Segment Detection Judgment Circuit 21 Storage Device 22 Switcher 23 Color line sequential discrimination signal generation circuit 30 Dropout pulse input terminal 31 Line memory 32 Dropout line conversion circuit 33 Field discrimination signal superposition circuit 34 Inhibition circuit 35 Field determination circuit

Claims (3)

[Claims] 1. A reproducing apparatus for a recorded video signal in which a video signal of one field or one frame is divided into a plurality of tracks and is segment-recorded, and the color line sequence is changed in field units. Analog-to-digital conversion analog-
A digital converter, a field memory for writing the output of the analog-digital converter, a horizontal sync signal of the reproduced video signal, a segment sync signal indicating the start of one track, and a segment and a field from the segment sync signal. A sync signal detecting circuit for outputting a first field discriminating signal for discriminating, and a phase synchronizing circuit for phase-locking the input first field reference signal with the segment synchronizing signal and outputting it as a second field reference signal. A memory control for controlling the field memory by creating a control signal for the field memory from the first field reference signal, the second field reference signal, a horizontal sync signal output from the sync signal detection circuit, and a segment sync signal. Circuit and the first field discrimination signal A delay circuit for delaying the input / output signal by the input memory and outputting it as a color line sequential determination signal; a decoder for returning the read output of the field memory to the original color line sequential according to the color line sequential determination signal; A video signal reproducing device comprising a digital-analog converter for converting an output into a digital-analog. 2. A segment synchronization signal output from a synchronization signal detection circuit and a first field reference signal are input, and it is determined from the segment synchronization signal whether or not the segment synchronization signal of each segment can be detected and output. The segment detection determination circuit and only the segment having the segment synchronization signal which can be detected by the segment detection determination circuit store the first field determination signal output from the synchronization signal detection circuit for one cycle of writing in the field memory. A storage device to be placed, and in the segment in which the segment synchronization signal cannot be detected by the segment detection determination circuit, the field determination signal stored in the storage circuit is stored in the segment detection determination circuit. The first field discrimination signal is switched to the second field discrimination signal. A switch for outputting a field discriminating signal, the second field discriminating signal and the field reference signal instead of the delay circuit, and the second field discriminating signal according to the time base conversion operation of the field memory. 2. The video signal reproducing apparatus according to claim 1, further comprising a color line sequential discrimination signal generator which performs time-axis conversion and delays by a delay amount of the input signal and the output signal of the memory and outputs as a color line sequential discrimination signal. 3. A line memory for delaying the output of the analog-to-digital converter by one line, and a field discrimination signal of the output of the sync signal detection circuit is superimposed on a horizontal blank portion of the output of the line memory, and an input signal of the field memory. The field discrimination signal superimposing circuit, the dropout signal, and the horizontal synchronizing signal output from the synchronizing signal detecting circuit are used as input signals, the horizontal line in which the dropout signal is present is detected, and the effective signal of the horizontal line is detected. A dropout line conversion circuit that outputs a second dropout signal to the entire unit, a second dropout signal output from the dropout line conversion circuit, and a memory write control signal output from the memory control circuit, and When the second dropout signal is detected, write to the field memory. A prohibition circuit for prohibiting and a memory output signal read from the field memory as an input signal, a field discrimination signal superimposed on a horizontal blank portion of the memory output signal is detected, and it is used as a color line sequential discrimination signal. The video signal reproducing device according to claim 1, further comprising a field determination circuit for outputting.