JPH05284050A - Tuner circuit - Google Patents

Tuner circuit

Info

Publication number
JPH05284050A
JPH05284050A JP8364592A JP8364592A JPH05284050A JP H05284050 A JPH05284050 A JP H05284050A JP 8364592 A JP8364592 A JP 8364592A JP 8364592 A JP8364592 A JP 8364592A JP H05284050 A JPH05284050 A JP H05284050A
Authority
JP
Japan
Prior art keywords
circuit
tuning
signal
inter
interstage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8364592A
Other languages
Japanese (ja)
Inventor
Masumi Iwamura
真澄 岩村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8364592A priority Critical patent/JPH05284050A/en
Publication of JPH05284050A publication Critical patent/JPH05284050A/en
Pending legal-status Critical Current

Links

Landscapes

  • Noise Elimination (AREA)

Abstract

PURPOSE:To provide the tuner circuit having high jamming excluding ability against jamming signals lower than a desired frequency band by forming a variable voltage trap circuit at a point coupled from an inter-step tuner circuit to the input side of a mixer circuit. CONSTITUTION:Since the joining capacity of variable capacity diodes 10 and 11 in an inter-step tuner circuit 2 is changed corresponding to a tuning voltage supplied from a terminal 12, the stepwise tuner circuit 2 is tuned to received signals. Concerning a local oscillation circuit 4, the resonance frequency is changed, the frequency of local oscillated signals is turned to a prescribed value, and those signals are inputted to a mixer circuit 3. Thus, the inputted received signals are amplified by a high frequency amplifier circuit 1, band- selected by the inter-step tuner circuit 2 and inputted to the mixer circuit 3. In the mixer circuit 3, the local oscillated signals outputted from the local oscillation circuit 4 and the received signals are mixed, and intermediate frequency signals 5 are generated. The tuning voltage supplied from the terminal 12 is supplied from the inter-step tuner circuit 2 to a coupling capacitor 9 at a gap to the mixer circuit 3, and the joining capacity is changed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は段間同調回路から相互誘
導結合で受信信号を取りだしミクサ回路に入力するチュ
ーナ回路に係り、特に、希望周波数帯以外の帯域に可変
トラップを形成し、帯域外で発生する妨害信号の排除特
性を向上させたチューナ回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tuner circuit for extracting a received signal from an interstage tuning circuit by mutual inductive coupling and inputting the received signal to a mixer circuit. The present invention relates to a tuner circuit having improved rejection characteristics of an interference signal generated in.

【0002】[0002]

【従来の技術】従来のチューナ回路では、段間同調回路
から相互誘導結合により受信信号を取りだし、結合コン
デンサを介しミクサ回路に入力していた。
2. Description of the Related Art In a conventional tuner circuit, a reception signal is taken out from an interstage tuning circuit by mutual inductive coupling and input to a mixer circuit via a coupling capacitor.

【0003】図2に従来のチューナ回路を示す。FIG. 2 shows a conventional tuner circuit.

【0004】従来のチューナ回路は、高周波増幅回路
1、段間同調回路2、ミクサ回路3、局部発振回路4、
中間周波信号出力5、段間1次共振線6、段間2次共振
線7、ミクサ回路結合線8、結合コンデンサ9、可変容
量ダイオード10〜11、同調電圧供給端子12、段間
1次同調用コンデンサ13、段間2次同調用コンデンサ
14から構成されている。
The conventional tuner circuit includes a high frequency amplifier circuit 1, an interstage tuning circuit 2, a mixer circuit 3, a local oscillator circuit 4,
Intermediate frequency signal output 5, interstage primary resonance line 6, interstage secondary resonance line 7, mixer circuit coupling line 8, coupling capacitor 9, variable capacitance diodes 10 to 11, tuning voltage supply terminal 12, interstage primary tuning Capacitor 13 and interstage secondary tuning capacitor 14.

【0005】[0005]

【発明が解決しようとする課題】上記従来技術では、図
2に示すように段間1次共振線6と段間2次共振線7に
より構成される段間同調回路2から、ミクサ回路結合線
8により受信信号の帯域が取り出され、ミクサ回路3に
入力されていた。取り出された受信信号は、上記段間同
調回路までの選択特性によって希望周波数帯以外の周波
数成分を減衰させ、種々の妨害を除去していた。しか
し、段間同調回路の選択特性は、受信チャンネル全域に
わたって良好であることは難しく、特に中心周波数の近
傍で発生する下側ローカル妨害周波数等の減衰量が十分
でない。そのため中心周波数の近傍の帯域に過大なレベ
ルの信号が入力されると、その信号が妨害信号となり問
題となる欠点が有った。
In the above-mentioned prior art, as shown in FIG. 2, the interstage tuning circuit 2 constituted by the interstage primary resonance line 6 and the interstage secondary resonance line 7 is connected to the mixer circuit coupling line. The band of the received signal was taken out by 8 and input to the mixer circuit 3. In the extracted received signal, frequency components other than the desired frequency band are attenuated by the selection characteristics up to the interstage tuning circuit to remove various interferences. However, it is difficult for the selection characteristics of the interstage tuning circuit to be good over the entire receiving channel, and in particular, the amount of attenuation such as the lower local interference frequency generated near the center frequency is not sufficient. Therefore, when a signal having an excessive level is input to a band near the center frequency, the signal becomes an interfering signal, which is a problem.

【0006】本発明の目的は、簡単な回路構成で希望周
波数帯の下側の帯域外特性に対しトラップを形成し、下
側チャンネル妨害排除特性を良好にした回路を提供する
ことにある。
An object of the present invention is to provide a circuit which has a simple circuit structure and which forms a trap for the out-of-band characteristic on the lower side of a desired frequency band and has a good lower channel interference rejection characteristic.

【0007】[0007]

【課題を解決するための手段】上記目的を達成するため
に、本発明では、段間同調回路とミクサ回路間の結合コ
ンデンサを可変容量ダイオードとし、その可変容量ダイ
オードに逆バイアス電圧を供給する。それによって接合
容量が連続的に変化することからその接合容量と、ミク
サ回路結合線のインダクタンスとで生じる共振点をトラ
ップとして形成した回路が提供される。
To achieve the above object, in the present invention, the coupling capacitor between the interstage tuning circuit and the mixer circuit is a variable capacitance diode, and a reverse bias voltage is supplied to the variable capacitance diode. As a result, the junction capacitance continuously changes, so that a circuit is provided in which the resonance point generated by the junction capacitance and the inductance of the mixer circuit coupling line is used as a trap.

【0008】[0008]

【作用】段間同調回路のミクサ回路結合線と直列に接続
された結合コンデンサ(可変容量ダイオード)からなる
トラップ回路を形成する。この結合コンデンサ(可変容
量ダイオード)に逆バイアス電圧を供給することで接合
容量を連続的に変化させ、希望周波数帯の下側帯域でト
ラップを形成し、そのトラップを同調電圧によって可変
させる。
The trap circuit is formed of a coupling capacitor (variable capacitance diode) connected in series with the mixer circuit coupling line of the interstage tuning circuit. By supplying a reverse bias voltage to this coupling capacitor (variable capacitance diode), the junction capacitance is continuously changed, a trap is formed in the lower band of the desired frequency band, and the trap is varied by the tuning voltage.

【0009】[0009]

【実施例】以下、本発明の一実施例を図1により説明す
る。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG.

【0010】図1は本発明の一実施例としてのチューナ
回路を示すブロック図であり、本実施例は、高周波増幅
回路1、段間同調回路2、ミクサ回路3、局部発振回路
4、中間周波信号出力5、段間1次共振線6、段間2次
共振線7、ミクサ回路結合線8、結合コンデンサ9、可
変容量ダイオード10〜11、同調電圧供給端子12か
ら構成される。
FIG. 1 is a block diagram showing a tuner circuit as an embodiment of the present invention. In this embodiment, a high frequency amplifier circuit 1, an interstage tuning circuit 2, a mixer circuit 3, a local oscillator circuit 4, an intermediate frequency circuit are provided. It includes a signal output 5, an interstage primary resonance line 6, an interstage secondary resonance line 7, a mixer circuit coupling line 8, a coupling capacitor 9, variable capacitance diodes 10 to 11, and a tuning voltage supply terminal 12.

【0011】端子12から供給される同調電圧に応じて
段間同調回路2の可変容量ダイオード10〜11の接合
容量Cjが変化する。これにより段間同調回路2は受信
信号に対して同調される。また、局部発振回路4は、共
振周波数が変化して局部発振信号の周波数が所定値とな
りミクサ回路3に入力される。
The junction capacitance Cj of the variable capacitance diodes 10 to 11 of the interstage tuning circuit 2 changes according to the tuning voltage supplied from the terminal 12. As a result, the interstage tuning circuit 2 is tuned to the received signal. In the local oscillation circuit 4, the resonance frequency changes and the frequency of the local oscillation signal becomes a predetermined value and is input to the mixer circuit 3.

【0012】この結果、入力された受信信号は、高周波
増幅回路1で増幅され、段間同調回路2で帯域選択さ
れ、ミクサ回路3に入力される。ミクサ回路3では、局
部発振回路4から出力される局部発振信号と受信信号が
混合されて、中間周波信号5が出力される。
As a result, the input reception signal is amplified by the high frequency amplifier circuit 1, band-selected by the interstage tuning circuit 2 and input to the mixer circuit 3. In the mixer circuit 3, the local oscillation signal output from the local oscillation circuit 4 and the received signal are mixed, and the intermediate frequency signal 5 is output.

【0013】端子12から供給される同調電圧は、段間
同調回路2からミクサ回路3との間の結合コンデンサ
(可変容量ダイオード)9にも供給され、接合容量Cj
が変化する。
The tuning voltage supplied from the terminal 12 is also supplied to the coupling capacitor (variable capacitance diode) 9 between the interstage tuning circuit 2 and the mixer circuit 3 and the junction capacitance Cj.
Changes.

【0014】さらに本実施例の動作について詳細に説明
する。
Further, the operation of this embodiment will be described in detail.

【0015】最近の動向としてチューナのUHF帯を使
用した放送が増えつつあり、特に、希望信号に対し隣接
したチャンネル放送の信号に対する妨害を除去する必要
がある。そのためには、段間同調回路の帯域特性を全受
信チャンネルにわたって良好とすることが不可欠であ
る。
As a recent trend, the number of broadcasts using the UHF band of tuners is increasing, and in particular, it is necessary to remove the interference with the signal of the channel broadcast adjacent to the desired signal. For that purpose, it is indispensable to improve the band characteristic of the interstage tuning circuit over all the receiving channels.

【0016】段間同調回路2により帯域選択された信号
は、ミクサ回路結合線8により取りだし、結合コンデン
サ9を介しミクサ回路3に入力される。この時、前記信
号にミクサ回路結合線8のインダクタンスと結合コンデ
ンサ(可変容量ダイオード)9の接合容量とによる共振
点を、トラップとして形成し、希望周波数帯以外に過大
なレベルの信号が入力された場合の帯域外トラップとし
て動作させる。
The signal whose band is selected by the interstage tuning circuit 2 is taken out by the mixer circuit coupling line 8 and input to the mixer circuit 3 via the coupling capacitor 9. At this time, a resonance point due to the inductance of the mixer circuit coupling line 8 and the junction capacitance of the coupling capacitor (variable capacitance diode) 9 is formed as a trap in the signal, and an excessive level signal other than the desired frequency band is input. In case of out-of-band trap.

【0017】ここで段間同調回路と本発明のトラップ回
路について考察する。段間1次同調コンデンサ13の容
量をC、段間1次共振線6のインダクタンスをL、可変
容量ダイオード10の接合容量をCjとすると共振周波
数foは、
Consider now the interstage tuning circuit and the trap circuit of the present invention. When the capacitance of the interstage primary tuning capacitor 13 is C, the inductance of the interstage primary resonance line 6 is L, and the junction capacitance of the variable capacitance diode 10 is Cj, the resonance frequency fo is

【0018】[0018]

【数1】 [Equation 1]

【0019】で求められる。またトラップ回路について
は、ミクサ回路結合線8のインダクタンスをL’、結合
コンデンサである可変容量ダイオード9の接合容量をC
j’とするとトラップ周波数をftは、
It is calculated by Regarding the trap circuit, the inductance of the mixer circuit coupling line 8 is L ′, and the junction capacitance of the variable capacitance diode 9 which is a coupling capacitor is C.
j'is the trap frequency ft,

【0020】[0020]

【数2】 [Equation 2]

【0021】で求められる。ここで理想的にコイルが密
結合な場合を考えると、L=L’、また同調回路の可変
容量ダイオード10と同一の変化比を持った接合容量の
可変容量ダイオードを結合コンデンサ9として選べばC
j=Cj’となる。上式により共振周波数foとトラッ
プ周波数をftの関係は次式の通りとなる。
Is calculated by Considering ideally the case where the coils are tightly coupled, if L = L ′ and a variable capacitance diode having a junction capacitance having the same change ratio as the variable capacitance diode 10 of the tuning circuit is selected as the coupling capacitor 9, C
j = Cj '. From the above equation, the relationship between the resonance frequency fo and the trap frequency ft is as follows.

【0022】[0022]

【数3】 [Equation 3]

【0023】したがって、ft≦foの関係が保たれ
る。即ち、トラップ周波数ftを図3の如く受信周波数
より下側に形成させることができる。また、可変容量ダ
イオードの接合容量Cjは同調点の低い点で大きく、同
調点の高い点で小さい。そして受信周波数は、同調電圧
の低い点で低く、同調電圧の高い点で受信周波数も高
い。このとき上式に示すトラップ周波数は、常にft≦
foであるので図4に示す全受信周波数帯において、あ
る一定の関係を持って移動する。
Therefore, the relationship of ft≤fo is maintained. That is, the trap frequency ft can be formed below the reception frequency as shown in FIG. The junction capacitance Cj of the variable capacitance diode is large at the low tuning point and small at the high tuning point. The reception frequency is low when the tuning voltage is low, and the reception frequency is high when the tuning voltage is high. At this time, the trap frequency shown in the above equation is always ft ≦
Since it is fo, it moves with a certain fixed relationship in all the reception frequency bands shown in FIG.

【0024】トラップ回路を形成する結合コンデンサ
(可変容量ダイオード)9の逆方向バイアス電圧は、チ
ューナの同調電圧を利用する。本実施例では受信周波数
がfo=474〜858MHzの範囲で、同調電圧が2
〜20V変化したとき、可変容量ダイオード9の接合容
量Cjは15〜3pF程度連続的に変化する。
The tuning bias voltage of the tuner is used as the reverse bias voltage of the coupling capacitor (variable capacitance diode) 9 forming the trap circuit. In this embodiment, the reception frequency is fo = 474 to 858 MHz and the tuning voltage is 2
When it changes by ˜20 V, the junction capacitance Cj of the variable capacitance diode 9 continuously changes by about 15 to 3 pF.

【0025】図3および図4はそれぞれ本発明の一実施
例の特性を示す特性図である。
3 and 4 are characteristic diagrams showing the characteristics of one embodiment of the present invention.

【0026】本実施例では、チューナ回路の同調電圧を
利用し、ミクサ回路3で周波数変換される前に希望周波
数の下側における減衰量を大きくとることができる。
In this embodiment, the tuning voltage of the tuner circuit can be used to increase the amount of attenuation below the desired frequency before the frequency is converted by the mixer circuit 3.

【0027】[0027]

【発明の効果】本発明によれば、受信周波数より下側に
おける減衰量を大きくとることができるので、希望周波
数帯より低い妨害信号に対する妨害排除能力の優れたチ
ューナ回路が実現できる。
According to the present invention, a large amount of attenuation can be obtained below the reception frequency, so that it is possible to realize a tuner circuit having an excellent capability of eliminating interference with respect to an interference signal lower than a desired frequency band.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示すチューナ回路図であ
る。
FIG. 1 is a tuner circuit diagram showing an embodiment of the present invention.

【図2】本発明の従来例を示すチューナ回路図である。FIG. 2 is a tuner circuit diagram showing a conventional example of the present invention.

【図3】本発明の一実施例を示す特性図である。FIG. 3 is a characteristic diagram showing an example of the present invention.

【図4】本発明の一実施例を示す特性図である。FIG. 4 is a characteristic diagram showing an example of the present invention.

【符号の説明】[Explanation of symbols]

1…高周波増幅回路、2…段間同調回路、3…ミクサ回
路、4…局部発振回路、5…中間周波出力、6…段間1
次共振線、7…段間2次共振線、8…ミクサ回路結合
線、9…結合コンデンサ、10〜11…可変容量ダイオ
ード、12…同調電圧供給端子、13…段間1次同調用
コンデンサ、14…段間2次同調用コンデンサ、15…
下側トラップ形成部。
DESCRIPTION OF SYMBOLS 1 ... High frequency amplifier circuit, 2 ... Inter-stage tuning circuit, 3 ... Mixer circuit, 4 ... Local oscillation circuit, 5 ... Intermediate frequency output, 6 ... Inter-stage 1
Next resonance line, 7 ... Interstage secondary resonance line, 8 ... Mixer circuit coupling line, 9 ... Coupling capacitor, 10-11 ... Variable capacitance diode, 12 ... Tuning voltage supply terminal, 13 ... Interstage primary tuning capacitor, 14 ... Interstage secondary tuning capacitor, 15 ...
Lower trap forming part.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】受信信号を入力し、その信号を増幅して出
力する高周波増幅回路と、該高周波増幅回路からの出力
信号を入力し、所望の帯域を選択して出力する段間同調
回路と、局部発振信号を発生して出力する局部発振回路
と、前記段間同調回路からの出力信号と前記局部発振回
路からの局部発振信号とを混合して、中間周波信号を出
力するミクサ回路とから成り、前記段間同調回路及び局
部発振回路の各々の共振回路を構成する可変容量ダイオ
ードに、同調電圧をそれぞれ供給して、該同調電圧を変
化させることにより、前記段間同調回路及び局部発振回
路の選択すべき帯域を変化させ得るチューナ回路におい
て、 前記段間同調回路から前記ミクサ回路の入力側へ結合し
て成る点に、電圧可変トラップ回路を形成したことを特
徴とするチューナ回路。
1. A high frequency amplifier circuit for inputting a received signal, amplifying the signal and outputting the same, and an interstage tuning circuit for inputting an output signal from the high frequency amplifier circuit and selecting and outputting a desired band. A local oscillation circuit that generates and outputs a local oscillation signal, and a mixer circuit that mixes the output signal from the interstage tuning circuit and the local oscillation signal from the local oscillation circuit to output an intermediate frequency signal. The interstage tuning circuit and the local oscillator circuit are supplied with a tuning voltage to each of the variable capacitance diodes forming the resonance circuits of the interstage tuning circuit and the local oscillation circuit, and the tuning voltage is changed. In the tuner circuit capable of changing the band to be selected, a voltage variable trap circuit is formed at a point formed by coupling the interstage tuning circuit to the input side of the mixer circuit. Anna circuit.
【請求項2】請求項1において、前記段間同調回路は複
同調回路で構成され、入力側に段間1次同調回路、出力
側に段間2次同調回路とから成り、前記段間同調回路と
ミクサ回路結合線との相互誘導結合によって受信信号が
取りだされ、前記ミクサ回路に入力され、前記受信信号
のうち希望周波数帯以外の適当な帯域に相互インダクタ
とコンデンサを直列に接続したトラップ回路を形成し、
前記トラップを段間同調回路と同期させスプリアス妨害
となる信号のレベルを減衰させる回路を有することを特
徴とするチューナ回路。
2. The inter-stage tuning circuit according to claim 1, wherein the inter-stage tuning circuit comprises a double-tuning circuit, and the inter-stage tuning circuit comprises an inter-stage primary tuning circuit on the input side and an inter-stage secondary tuning circuit on the output side. A trap in which a reception signal is taken out by mutual inductive coupling between a circuit and a mixer circuit coupling line, is input to the mixer circuit, and a mutual inductor and a capacitor are connected in series in an appropriate band other than a desired frequency band of the reception signal. Forming a circuit,
A tuner circuit comprising a circuit for synchronizing the trap with an interstage tuning circuit to attenuate the level of a signal that causes spurious interference.
JP8364592A 1992-04-06 1992-04-06 Tuner circuit Pending JPH05284050A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8364592A JPH05284050A (en) 1992-04-06 1992-04-06 Tuner circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8364592A JPH05284050A (en) 1992-04-06 1992-04-06 Tuner circuit

Publications (1)

Publication Number Publication Date
JPH05284050A true JPH05284050A (en) 1993-10-29

Family

ID=13808191

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8364592A Pending JPH05284050A (en) 1992-04-06 1992-04-06 Tuner circuit

Country Status (1)

Country Link
JP (1) JPH05284050A (en)

Similar Documents

Publication Publication Date Title
US5437051A (en) Broadband tuning circuit for receiving multi-channel signals over a broad frequency range
US4162452A (en) Channel selection for a television receiver having low-gain high frequency RF-IF section
US4380828A (en) UHF MOSFET Mixer
US4408347A (en) High-frequency channel selector having fixed bandpass filters in the RF section
US4160953A (en) Self-oscillation mixer circuits
US4710974A (en) Circuit arrangement for a tuner for changing over several frequency ranges
US4835608A (en) Image trap filter circuit
KR860000441B1 (en) Tunner
MXPA97002782A (en) Entry circuit for a televis tuner
JPH05284050A (en) Tuner circuit
US4164710A (en) Very high frequency tuner for eliminating image interference and stray capacitance effects
US2978578A (en) Improved transistorized mixing circuit
US6734761B2 (en) Radio-frequency input stage
US6842610B2 (en) Tuner
JP2534982B2 (en) Selective receiving circuit of SHF receiver
US3458819A (en) Uhf-if or vhf-if converter
JPH0730456A (en) Television tuner
KR20020030379A (en) Double conversion type tuner for using trap circuit
JPS622829Y2 (en)
US6701142B1 (en) Mixer oscillator stage
US20060223481A1 (en) Integrated circuit layout for a television tuner
JPH0210684Y2 (en)
JP3596760B2 (en) Receiver
KR950012950B1 (en) Stabilization circuit of input signal for ic tunor
JP2603560Y2 (en) Double tuning circuit