JPH05283961A - Amplitude constant circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption by constituting an amplitude constant circuit outputting the amplitude of an input signal while making it constant in accordance with the control signal from the outside of a CMOS circuit. CONSTITUTION:The output of a variable gain amplifier circuit 1 is inputted to a peak holding circuit 3. A voltage comparator 5 compares the output of the peak holding circuit 3 with the output of a reference voltage circuit 6. A peak detection circuit 4 detects the peak on the positive side in a sine wave to be the output of an oscillation circuit 2. A counter 7 counts peak every time the peak detection circuit 4 detects the peak. The output data of the counter 7 changes the amplification factor in the variable gain amplifier circuit 1 via a latch circuit 8. When the output of the voltage comparator 5 is inverted in the latch circuit 8, the output data of the counter 7 is latched and the variable gain amplifier circuit 1 outputs constant amplitude.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a constant amplitude circuit,
In particular, it relates to a constant amplitude circuit realized in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art As a conventional constant amplitude circuit, there is a circuit as shown in the block diagram of FIG. As shown in FIG.
The output terminal of the variable gain amplifier circuit 55 has a peak holding circuit 56.
Is connected to the input end of. The negative phase input terminal of the operational amplifier circuit 58 is connected to the output terminal of the peak holding circuit 56, and the positive phase input terminal is connected to the output terminal of the reference voltage source circuit 57. The variable gain amplifier circuit 55 includes the operational amplifier circuit 5
The output voltage of 8 determines the amplification factor.

Next, the operation of the conventional constant amplitude circuit configured as described above will be described.

The peak holding circuit 56 detects, holds and outputs the peak voltage in the output signal of the variable gain amplifier circuit 55. The operational amplifier circuit 58 amplifies and outputs the difference between the output of the peak holding circuit 56 and the output of the reference voltage source circuit 57, and the output voltage changes the amplification factor in the variable gain amplifier circuit 55.

FIG. 9 is a graph showing the voltage vs. amplification factor characteristic of the variable gain amplifier circuit 55 in the constant amplitude circuit shown in FIG. As shown in FIG. 9, when the control voltage VB, which is the output voltage of the operational amplifier circuit 58, is gradually increased, the amplification factor increases from a certain value of the control voltage VB in proportion to the increase of the control voltage VB. When the control voltage VB reaches a predetermined level, the amplification factor remains constant even if the control voltage VB is increased.

When the amplitude of the input signal of the variable gain amplifier circuit 55 is lower than the output of the reference voltage source circuit 57, the control voltage VB is increased by the operational amplifier circuit 58 and the amplification factor in the variable gain amplifier circuit 55 is increased. Can be raised. When the amplitude of the input signal of the variable gain amplifier circuit 55 is higher than the output of the reference voltage source circuit 57, the control voltage VB is reduced by the operational amplifier circuit 58 and the amplification factor in the variable gain amplifier circuit 55 is lowered. .. Then, finally, the amplitude of the output signal of the variable gain amplifier circuit 55 is
It becomes the same as the output voltage of the reference voltage source circuit 57.

Then, by changing the output voltage of the reference voltage source circuit 57, the amplitude of the output signal of the variable gain amplifier circuit 55 can be set arbitrarily.

FIG. 10 is a circuit diagram showing an example of a detailed configuration of the variable gain amplifier circuit 55 in FIG. As shown in FIG. 10, the signal input from the input terminal IN is amplified by the differential amplifier circuit including the transistor and the resistor and output to the output terminal OUT. The amplification factor in the differential amplifier circuit is configured to change according to the control voltage VB applied from the outside.

[0009]

However, in the above-described conventional constant amplitude circuit, the circuit is composed of bipolar transistors, and the structure as shown in FIG.
Since it is difficult to configure with OS transistors, there is a problem that power consumption increases.

The present invention has been made in view of the above problems, and in an amplitude constant circuit which outputs an input signal with a predetermined constant amplitude, the amplitude constant circuit can be formed of a CMOS circuit, thereby reducing power consumption. An object is to provide a constant amplitude circuit that can be reduced.

[0011]

A constant amplitude circuit according to the present invention comprises a variable gain amplifier circuit whose amplification factor is controlled by a control signal, and a peak holding circuit which holds a peak value at the output of the variable gain amplifier circuit. In the constant amplitude circuit having, a means for outputting a digital signal according to the difference between the output voltage of the peak holding circuit and the reference voltage is provided, and the digital signal in this means is used as the control signal in the variable gain amplifier circuit. It is characterized by

[0012]

In the amplitude constant circuit according to the present invention, the variable gain amplifier circuit amplifies the input signal with an amplification factor controlled by the control signal in the amplitude constant circuit which outputs the input signal with a predetermined constant amplitude. And output. The peak holding circuit inputs the output of the variable gain amplifier circuit, holds the peak value of this input, and outputs it. And, in the amplitude constant circuit according to the present invention, the difference between the peak value of the variable gain amplifier circuit which is the output of the peak holding circuit and the reference voltage is calculated,
This difference is converted into a digital signal and used as a control signal for the variable gain amplifier circuit. Since all the circuits described above can be designed and manufactured with CMOS circuits, the constant amplitude circuit according to the present invention can reduce power consumption.

[0013]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an amplitude constant circuit according to the first embodiment of the present invention. As shown in Figure 1,
The output end of the oscillation circuit 2 is connected to one input end of the variable gain amplification circuit 1 and the input end of the peak detection circuit 4, and the output end of the variable gain amplification circuit 1 is connected to the input end of the peak holding circuit 3. .. The output terminal of the peak holding circuit 3 is connected to the positive phase input terminal of the voltage comparator 5, and the output terminal of the reference voltage circuit 6 is connected to the negative phase input terminal. The output end of the peak detection circuit 4 is connected to the input end of the counter 7, and one input end of the latch circuit 8 is connected to the output end. Latch circuit 8
The output terminal of the voltage comparator 5 is connected to the other input terminal, and the other input terminal of the variable gain amplifier circuit 1 is connected to the output terminal. The input of the latch circuit 8 is latched by the output of the voltage comparator 5.

Next, the operation of the constant amplitude circuit according to the first embodiment constructed as described above will be described.

The oscillator circuit 2 outputs a signal having a predetermined amplitude. The variable gain amplifier circuit 1 is set to an amplification factor of 1 as an initial value. The peak voltage in the output signal of the variable gain amplifier circuit 1 is held by the peak holding circuit 3, and the peak voltage is output from the peak holding circuit 3. The voltage comparator 5 compares the peak voltage with the output signal of the reference voltage circuit 6 and outputs the comparison result. When the output voltage of the voltage comparator 5 is low level, 1 is added to the count in the counter 7. Voltage comparator 5
When the output voltage of 1 becomes high level, the output of the counter 7 is latched, and the signal of the magnification corresponding to the count is output from the counter 7.

FIG. 2 is a circuit diagram showing a detailed embodiment of the peak holding circuit section in FIG. The SIN wave output of the oscillation circuit 12 appears at the first output terminal 9 shown in FIG.
The first output terminal 9 is connected to the SI of the peak detection circuit 11.
It is connected to the N wave input terminal. The COS wave output of the oscillation circuit 12 appears at the second output terminal 10. Also, the second
The output terminal 10 of is connected to the COS wave input terminal of the peak detection circuit 11. One end of the analog switch 13 is connected to the first input terminal 14, and the other end is connected to the positive phase input end of the operational amplifier circuit 15. The peak detection circuit 11 outputs a pulse at the peak of the input SIN wave signal, and this pulse turns on / off the analog switch 13.
Turned off. The capacitor 16 has one end connected to the positive phase input end of the operational amplifier circuit 15 and the other end connected to GND.
The negative phase input terminal of the operational amplifier circuit 15 is connected to the output terminal 17 and the output terminal of the operational amplifier circuit 15.

The input end of the variable gain amplifier circuit 1 in FIG. 1 is connected to the first output terminal 9 in FIG. 2, and the output end is connected to the first input terminal 14. A peak voltage in the output signal of the variable gain amplifier circuit 1 appears at the output terminal 17.

FIG. 3 shows a variable gain amplifier circuit 1 shown in FIG.
3 is a circuit diagram showing a detailed embodiment of FIG. The variable gain amplifier circuit shown in FIG. 3 constitutes a switched capacitor circuit, and the voltage amplification factor is the total capacitance of the capacitance group 18 and the second capacitance 19.
It depends on the ratio of. A series circuit of the first variable capacitor 20 and the first analog switch 21 is connected in parallel with the first capacitor 22. Similarly, the series circuit of the n-th (n is a natural number) variable capacitor 23 and the n-th analog switch 24 is
It is connected in parallel with the first capacitor 22. Where the first
Let C be the capacitance value of the capacitance 22 and the capacitance of the second capacitance 19. The capacitance value of the first variable capacitance 20 is C / 2, and the capacitance value of the m-th variable capacitance is C / {2 to the m-th power} (m is a natural number of m ≦ n).

The counter 25 is an n-bit counter. The first latch circuit 26 latches the LSB of the counter 25, and the m-th latch circuit
Latch the m bits of. First analog switch 21
Is turned on / off by the output of the first latch circuit 26, and similarly, the nth analog switch 24 is turned on / off by the output of the nth latch circuit 27. The positive phase input end of the voltage comparison circuit 28 is connected to the output end of the reference voltage circuit 29, and the negative phase input end is connected to the input terminal 30. The output of the voltage comparison circuit 28 is the latch circuits 26,
Latched at 27. The input terminal 30 is connected to the output terminal 17 of the peak holding circuit section shown in FIG.

The variable gain amplifier circuit shown in FIG. 3 is configured to latch when the input voltage input from the input terminal 30 becomes larger than the output of the reference voltage circuit 29.

FIG. 4 is a circuit diagram showing a detailed embodiment of the peak detection circuit 4 in FIG. One end of the first dividing resistor 31 shown in FIG. 4 is connected to the high potential power source, and the other end is the third
Is connected to the positive phase input terminal of the voltage comparator 34. Second
One end of the dividing resistor 32 is connected to the positive phase input terminal of the third voltage comparator 34, and the other end is connected to the negative phase input terminal of the fourth voltage comparator 35. One end of the third dividing resistor 33 is connected to the low potential power source, and the other end is connected to the negative phase input end of the fourth voltage comparator 35. The resistance value of the first dividing resistor 31 is R, the resistance value of the second dividing resistor 32 is r, and the resistance value of the third dividing resistor 33 is (R + r).

The negative phase input end of the third voltage comparator 34 and the positive phase input end of the fourth voltage comparator 35 are connected to the COS wave input terminal 37. The positive phase input terminal of the fifth voltage comparator 36 is connected to the negative phase input terminal of the fourth voltage comparator 35, and the negative phase input terminal of the fifth voltage comparator 36 is connected to the SIN wave input terminal 38. .. In the first two-input AND 39, the first input terminal is connected to the output terminal of the third voltage comparator 34, and the second input terminal is connected to the output terminal of the fourth voltage comparator 35.
In the second 2-input AND 40, the first input terminal is connected to the output terminal of the first 2-input AND 39, and the second input terminal is connected to the output terminal of the fifth voltage comparator 36. The output terminal of the second 2-input AND 40 is connected to the peak detection signal terminal 41.

FIG. 5 is a waveform diagram showing the operation of each part in the peak detection circuit shown in FIG. As shown in FIG.
When the amplitude of the SIN wave increases to the positive side and passes the GND level, a pulse signal is output.

FIG. 6 is a block diagram showing an amplitude constant circuit according to the second embodiment of the present invention. As shown in FIG.
The input terminal of the peak holding circuit 43 is connected to the variable gain amplifier circuit 42.
Is connected to the output end of. The subtraction circuit 45 outputs the difference between the output of the peak hold circuit 43 and the output of the reference voltage source circuit 44. The A / D conversion circuit 46 converts the output voltage of the subtraction circuit 45 into a digital signal. Variable gain amplifier circuit 4
2 determines the amplification factor according to the output data of the A / D conversion circuit 46. The A / D conversion circuit 46 has a function of latching the output data after outputting the data.

FIG. 7 is a circuit diagram showing a detailed embodiment of the subtraction circuit 45 in FIG. The difference between the voltage input from the first input terminal 47 and the voltage input from the second input terminal 48 appears at the output terminal 49. The subtraction circuit in the second embodiment also operates as an amplifier whose amplification factor is determined by the ratio of the first capacitor 50 and the second capacitor 51.

The amplitude constant circuit according to the second embodiment described above is characterized in that the time until the desired amplitude is obtained can be shortened.

[0028]

As described above, according to the amplitude constant circuit of the present invention, in the amplitude constant circuit which outputs the input signal with a predetermined constant amplitude, the output voltage of the peak holding circuit and the reference voltage are Since the digital signal corresponding to the difference is output and the amplification factor in the variable gain amplifier circuit is changed based on the digital signal, the entire circuit configuration can be designed and manufactured by the CMOS circuit,
The power consumption can be reduced, and the time required to obtain a desired amplitude can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing an amplitude constant circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a detailed example of a peak holding circuit section in the constant amplitude circuit shown in FIG.

3 is a circuit diagram showing a detailed embodiment of a variable gain amplifier circuit in the constant amplitude circuit shown in FIG.

FIG. 4 is a circuit diagram showing a detailed example of a peak detection circuit in the constant amplitude circuit shown in FIG.

5 is a waveform diagram showing the operation of each part in the peak detection circuit shown in FIG.

FIG. 6 is a block diagram showing an amplitude constant circuit according to a second embodiment of the present invention.

7 is a circuit diagram showing a detailed embodiment of a subtraction circuit in the constant amplitude circuit shown in FIG.

FIG. 8 is a block diagram showing an example of a conventional constant amplitude circuit.

9 is a graph showing voltage-amplification factor characteristics of a variable gain amplifier circuit in the constant amplitude circuit shown in FIG.

10 is a circuit diagram showing an example of a detailed configuration of a variable gain amplifier circuit in the constant amplitude circuit shown in FIG.

[Explanation of symbols]

 1; Variable gain amplification circuit 2; Oscillation circuit 3; Peak holding circuit 4; Peak detection circuit 5; Voltage comparator 6; Reference voltage circuit 7; Counter 8; Latch circuit

Claims (1)

[Claims] 1. An amplitude constant circuit having a variable gain amplifier circuit, the amplification factor of which is controlled by a control signal, and a peak holding circuit which holds a peak value in the output of the variable gain amplifier circuit. A constant amplitude circuit comprising means for outputting a digital signal according to the difference between the voltage and the reference voltage, and the digital signal in this means being the control signal in the variable gain amplifier circuit.