JPH05283709A - Semiconductor nonvolatile memory - Google Patents

Abstract

PURPOSE:To provide a semiconductor nonvolatile memory with which electric erasing is conducted and also the low threshold value of a memory cell can be read out. CONSTITUTION:The low threshold value of a memory cell can be read out by applying verification voltage to the potential of a control gate, i.e., a word line W1, and by applying low positive voltage Vms by a source potential control circuit SVC to the common source CS of the memory cell. Accordingly, as the transistor M1 of a cell works on a linear region by the application of a positive voltage Vms to the source, a low threshold value can be read out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor non-volatile memory device for electrically erasing information, and a semiconductor non-volatile memory device suitable for judging the threshold voltage of a transistor of a memory cell of a memory array. Regarding

[0002]

BACKGROUND ART erasable information by ultraviolet rays as a semiconductor nonvolatile memory device EPROM (E rasable and P
rogrammable R ead O nly M emory) , electrically erasable EEPROM (E lectrically E rasable and P rogramm
able R ead O nly M emory) and flash memory are used for the storage of programs and data. In particular,
The flash memory has the same memory cell area as that of the EPROM and can be electrically erased like the EEPROM.

Unlike the threshold value of the thermal equilibrium state when erasing with ultraviolet rays like EPROM, the threshold value of the transistor of the memory cell after erasing of the flash memory is generally negative in some cases. If the threshold value of the memory cell transistor drops to a negative value, reading or the like is adversely affected. That is, in a cell in which the threshold voltage of the transistor of the memory cell is decreased to a negative value, a current (non-selection leak current) flows through the data line even if the voltage of the word line, that is, the control gate voltage is 0V. As a result, the reading time is delayed, which causes erroneous reading.

The threshold value of the transistor of each memory cell of the memory array after erasing the flash memory has a distribution within the array. The magnitude of this threshold variation is approximately 1V to 3V. Therefore, it is necessary to precisely control the threshold values of the transistors of all the memory cells in the memory array so that the threshold voltage does not become a negative voltage after erasing. To this end, it is necessary to divide the erasing into several times, read each time the erasing is performed, check whether the erasing is sufficient, and repeat the operation of erasing if not enough.

On the other hand, IEEE issued in October 1988
JOURNAL SOLID-STATE CICUITS, VOL.23, NO.5 pp.1157
-1163, page 1161 in Fig. 6 discloses the erase algorithm of the flash memory. In order to secure the lower limit of the operable power supply voltage Vccmin during normal read, the memory chip is read during read (erase-bay-fy). It states that a verify voltage is generated therein.
The upper limit value of the threshold voltage distribution is determined by this lower limit of operable power supply voltage Vccmin, that is, the verify voltage.

The IEEE Internation, issued in 1988
al Solid-State Circuits Conference DIGEST OF TECHN
ICAL PAPERS pp.122-123 discloses a read circuit of a semiconductor nonvolatile memory device as shown in FIG. The circuit shown in FIG. 3 is for an EPROM, but it can also be used for a flash memory. The circuit of FIG. 3 has an inverter configuration in which the transistors M1 and M3 of the memory cell are driver transistors and the p-channel MOSFET Q6 is a load transistor. Further, for flash memory, the diode-connected type in which the gate of the p-channel MOSFET Q6 as the load transistor of FIG.
Published in IEEE International Solid-State Circuits Co
nferenceDIGEST OF TECHNICAL PAPERS pp.60-61.

In FIG. 3, if the threshold voltage of the transistors M1 and M3 of the memory cell is high, no current flows when the voltage of the word line, that is, the control gate voltage is 0V, and the voltage drop in the p-channel MOSFET Q6 is almost zero. When the threshold value is low, the current flows and p
A voltage drop occurs in the channel MOSFET Q6. This is judged by the inverter circuit composed of MOSFETs Q8 and Q9. The circuit A including the MOSFETs Q4 to Q7 sets the drain voltage of the memory cell transistor to about 1V.
Is a circuit for setting the voltage to, and at the same time, the signal amplitude of the data line is made small so that the data can be read at high speed. Biasing the drain of the transistor to such a low voltage is to prevent weak writes during read operations. When a voltage is applied to the drain for a long time, weak writing occurs even under normal writing conditions. In order to keep this within the allowable range, it is necessary to set the data line voltage to about 1V. In addition, MOSFETQ
The circuit B composed of 1 to Q3 is a circuit for precharging the data line at high speed.

FIG. 4 shows static characteristics when a memory cell in which a logic "0" is written and a logic "1" is erased is read in the sense amplifier circuit of FIG. The vertical axis represents the potential V of the output node C of the sense amplifier in FIG.
C, the horizontal axis is the power supply voltage Vcc. In FIG. 4, the MOS of FIG.
The logical threshold value of the inverter circuit of the output of the sense amplifier composed of the FETs Q8 and Q9 is shown at the same time. The point where the characteristic line of the logical threshold value of the inverter and the characteristic of the logical "1" intersect is the operable lower limit power supply voltage Vccmin. That is, in such a reading method, the threshold voltage of the memory cell has a one-to-one correspondence with Vccmin. By utilizing this relationship, the threshold voltage of the memory cell can be determined by measuring the operable lower limit power supply voltage Vccmin.

FIG. 5 shows the lower limit operable voltage Vccmin and the threshold voltage Vth of the transistor of the memory cell of "1".
Shows the relationship. In this way, the threshold value in a limited range can be determined by the operable power supply voltage. The upper limit voltage E of the operable power supply is determined by the device breakdown voltage of the MOSFETs that constitute the read-system sense amplifier circuit, while the lower limit voltage D
Is determined by the logical threshold value of the MOSFET forming the read circuit system. However, in this method, reading below the threshold value F of logic "1" that should be judged at the power supply voltage D or lower cannot be performed. For example, the operable lower limit power supply voltage Vccmi
nD is 2V to 2.5V, and the threshold voltage F at this time is
Is 1.5V to 2V.

[0010]

In the above-mentioned conventional semiconductor non-volatile memory device for electrical erasing, attention should be paid to reading when the threshold voltage of the transistor of the memory cell after electrical erasing is low. Therefore, there is a problem that the distribution of the low threshold voltage of the transistor of each memory cell cannot be measured. In other words, it is impossible to judge the threshold value equal to or lower than F in FIG.

This is because even if the threshold voltage of the transistor of each memory cell is stopped by the operation lower limit power supply voltage Vccmin method described above for the erase stop level, the negative threshold value which causes the erroneous reading described above. It is inconvenient to know the margin up to the value voltage and the process stability.

Further, in the case where it becomes possible to reduce the threshold voltage variation at the erase stop level in order to increase the operation margin in the reading by suppressing the variation of the threshold voltage due to the improvement of the process, etc. The operation lower limit power supply voltage Vccmin method has a problem that the erase stop level cannot be lowered.

Therefore, an object of the present invention is to provide a semiconductor nonvolatile memory device capable of reading a low threshold voltage of a transistor of a memory cell and determining a threshold voltage having a low erase stop level. It is in.

[0014]

The above object is achieved by providing means for applying a drain voltage, that is, a positive voltage lower than the potential of the data line, to the source electrode of the transistor of the memory cell of the memory of the semiconductor nonvolatile memory element. It

[0015]

According to the above-mentioned means, by applying a positive voltage lower than the drain voltage to the source electrode of the memory cell of the semiconductor non-volatile memory device to read it, the lower limit of the threshold voltage of the transistor of the memory cell which can be judged is widened. be able to. That is, the lower limit voltage of the operable power supply is not determined by the logic threshold value of the MOSFETs forming the read circuit system.

By applying a drain voltage, that is, a positive voltage lower than the potential of the data line to the source electrode of the transistor of the memory cell of the memory of the semiconductor nonvolatile memory element, the MOS transistor of the memory cell is not in the saturation region but in the linear region. Operate.

On the other hand, the voltage-current characteristic in the linear region of the MOS transistor is given by the following equation 1 as is well known.

[0018]

[Equation 1]

By applying a drain voltage, that is, a positive voltage lower than the potential of the data line to the source electrode of the transistor of the memory cell, the drain-source voltage Vds becomes sufficiently small. Since items can be ignored, equation 1 can be approximated as equation 2 as follows.

[0020]

[Equation 2]

It is now assumed that a certain power supply voltage Vcc is supplied to the control gates of the memory cell transistors and the sense amplifier circuit. At this time, the drain voltage of the memory transistor supplied from the sense amplifier circuit, that is, the voltage of the data line is substantially constant regardless of the power supply voltage Vcc and the source voltage of the memory. Further, since the sense amplifier converts the current flowing through the memory cell transistor into a voltage, the current sensitivity determined by the sense amplifier circuit also becomes a substantially constant value without depending on the source voltage of the memory cell transistor. .. Here, if the potential of the source electrode is raised with the threshold value of the memory transistor kept at a certain value, the gate-source voltage Vgs and the drain-source voltage Vds decrease, and the current Ids flowing through the memory decreases. .. That is, when a positive voltage is applied to the source electrode, a current equal to that when the source voltage is 0V cannot flow in the sense amplifier circuit unless the threshold value is lowered as compared with the case where no potential is applied to the source electrode. become. In other words, the sensitivity of the sense amplifier with respect to the sense current, that is, the drain current Ids is constant regardless of the potential of the source, so that the memory cell that can be detected as the gate-source voltage Vgs and the drain-source voltage Vds decrease. Threshold value Vth becomes low. That is, if the threshold value of the memory is constant, the operable lower limit power supply voltage Vccmin at which the read information is inverted between logic "0" and logic "1" by raising the potential of the source electrode.
Can be lowered.

With this read method, it is possible to know the threshold voltage distribution of the transistors of each memory cell of the memory array having a low threshold value after erase, and further continue or stop the erase operation based on the read information. Can be controlled. The gate electrode of the memory cell, that is, the potential of the word line can be set to the power supply voltage Vcc supplied from the outside or the word line potential applied during normal reading.
Also, during normal reading, if the threshold value of the erase stop level is controlled by the method described above, the threshold value after erasing can be lowered, the read current increases and the operation margin such as the read speed increases. You can

FIG. 6 shows the relationship between the threshold voltage Vth of the transistor of the memory cell and the operable lower limit power supply voltage Vccmin according to the read method of the present invention. By applying a potential to the source electrode of the memory cell, logic
Reading below the threshold value F of 1 ″ can be determined in the range of power supply voltages D to E.

A lower limit Vcc of the power supply voltage which is operable by applying a positive voltage Vms lower than the drain voltage to the source electrode of the memory cell and changing the power supply voltage Vcc of the control gate, that is, the word line potential.
It can be determined by measuring min. By this read method, the threshold voltage V of the transistor of the memory cell is
Since th has a one-to-one correspondence with the operable lower limit power supply voltage Vccmin, it is possible to know the distribution of the low threshold voltage Vth of the transistors in each memory cell after erasing in the realistic range of the power supply voltage Vcc. For example, if the source electrode potential Vms is 0.8V, the threshold value from 0V can be determined.

[0025]

FIG. 1 is a circuit block showing a semiconductor integrated circuit having a semiconductor nonvolatile memory device which is a flash memory according to an embodiment of the present invention. In the embodiment of FIG. 1, in order to determine a low threshold value, a positive voltage Vms lower than the voltage of the drain electrode 3, that is, the voltage of the data line CD is applied to the source electrode 4 of the transistor M1 of the memory cell by the source voltage control circuit SVC. Is applied to read out.

The transistor M1 of the non-volatile memory cell shown in FIG. 1 can have the cell structure shown in FIG. 2, for example. Such a structure is known as Inte, published in 1987.
It has the same structure as the transistor of the memory cell of the flash memory announced at rnational Electron Device Meeting pp.560-563. The memory cell includes a control gate electrode 1, a floating gate 2, a drain electrode 3, a source electrode 4,
One transistor 1 element is composed of a tunnel oxide film 5, a P substrate 6, a high impurity concentration N + source / drain region 7, a low impurity concentration N− region 8 on the source side, and a high impurity concentration P + region 9 on the drain side. A flash erase type EEPROM cell as a non-volatile memory cell is configured.

In FIG. 1, the control gate electrode 1 of the memory transistor M1 is connected to the word line W1 and further connected to the row decoder XDCR. Row decoder XDC
The R supplies the power supply voltage Vcc to the control gate 1 at the time of reading. The drain electrode 3 of the memory transistor M1 is connected to the common data line CD, and further connected to the sense amplifier circuit SA which has a drain voltage setting function and a sensing function. The drain voltage for reading is a low voltage of about 1 V so that weak writing is unlikely to occur. The source electrode 4 of the memory transistor M1 is connected to the common source line CS and further connected to the source potential control circuit SVC. In this source potential control circuit SVC, either the ground potential or a positive voltage Vms lower than the drain voltage can be selectively applied to the source electrode 4.

The voltage Vms applied to the source electrode is a constant voltage or a voltage dependent on the power supply voltage Vcc, which is a power supply supplied from the outside or a built-in power supply inside the semiconductor integrated circuit. Any lower positive voltage will do.

FIG. 7 shows a circuit diagram of a semiconductor nonvolatile memory device according to a more specific embodiment of the present invention.
Although each circuit element of is not particularly limited, a known CMOS
It is formed on a semiconductor substrate such as a piece of single crystal silicon by the manufacturing technology of a (complementary MOS) integrated circuit. Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single crystal p-type silicon. n channel MO
The SFET is a gate formed of polysilicon, which is formed on the surface of the semiconductor substrate between the source region, the drain region, and the source region and the drain region on the surface of the semiconductor substrate through a thin gate insulating film. Composed of electrodes. The p-channel MOSFET is formed in the n-type well region formed on the surface of the semiconductor substrate. As a result, the semiconductor substrate constitutes a common substrate gate of the plurality of n-channel MOSFETs formed on it, and the ground potential of the circuit is supplied. The common substrate gate of the p-channel MOSFET, that is, the n-type well region is connected to the power supply voltage Vcc. Alternatively, if it is a high voltage circuit, it is connected to a high voltage Vpp given from the outside, an internally generated high voltage, or the like.
Alternatively, the integrated circuit may be formed on a semiconductor substrate made of single crystal n-type silicon. In this case, n channel MOS
The FET is formed in the p-type well region.

Although not particularly limited, the semiconductor nonvolatile memory device of this embodiment shown in FIG. 7 has a row address buffer XADB and a column address buffer YADB which receive a row address signal and column address signals AX and AY supplied from external terminals.
Complementary address signals formed through are supplied to the row address decoder and column address decoders XDCR and YDCR. Although not particularly limited, the row address buffers and the column address buffers XADB and YADB are activated by the selection signal ce inside the device, take in the address signals AX and AY from the external terminals, and have the same phase as the address signals supplied from the external terminals. To form a complementary address signal composed of the internal address signal and the opposite phase address signal.

The row address decoder XDCR forms selection signals for the word lines W1, W2 ... Wn of the memory array according to the complementary address signals of the address buffer XADB,
The column address decoder YDCR is an address buffer YA.
A select signal for the data lines D1, D2 ... Dm of the memory array is formed according to the complementary address signal of DB.

Although not particularly limited, since memory cells are selected by writing or reading in 8-bit or 16-bit units, the row address decoder XDCR and the column address decoder YDCR select 8 or 16 memory cells. To be selected. The number of memory cells in one data block is n in the word line direction (row direction) and m in the data line direction (column direction). In other words, the memory array of the semiconductor chip is divided into 8 or 16 data blocks of n × m memory cell groups.

As shown in FIG. 2, the memory array includes memory cell MOSFETs M1 to M9 having a stacked gate structure having a control gate and a floating gate, and a word line W1.
Wn ... Wn and data lines D1, D2 ... Dm and common source line CS. Common source line C
S is connected to the source potential control circuit SVC. The source potential control circuit SVC writes the potential of the common source line CS and the ground potential Vss of the circuit during normal reading.
It is a circuit that switches to a low positive voltage Vms during erase verify and to the power supply voltage Vcc or high voltage Vpp during erase. The potential Vcc is an erasing method in which a negative voltage is applied to the gate, and the high potential Vpp is an erasing method in which the gate potential is 0V. In the memory array of FIG. 7, memory cells arranged in the same row, for example, M1 and M
The control gates of M4 and M7 are connected to the word line W1, and the drains of the memory cells M1 to M3 arranged in the same column are connected to the data line D1.

The data lines D1 to Dm are connected to the common data line CD through column selection switch MOSFETs Q12 to Q14 which receive a selection signal formed by the address decoder YDCR. The output terminal of the write data input buffer DIB, to which the write signal input from the external terminal I / O is supplied, is connected to the common data line CD via the MOSFET Q16 which is turned on upon receiving the write control signal we during writing. Connected. Further, the common data line CD is connected to the sense amplifier SA via the switch MOSFET Q15 which is turned on when receiving the read control signal se, and further connected to the external terminal I / O through the read data output buffer DOB. ..

The timing control circuit CONT is not particularly limited, but external terminals / CE, / OE, / WE, / EE.
Timing signals such as internal control signals ce, se, we, er, ev according to the chip enable signal, output enable signal, write enable signal, erase enable signal and high voltage Vpp for writing and erasing supplied to , A read power supply voltage Vcc, a write high voltage Vpp, etc., which are selectively supplied to the address decoder and the like.

The memory cells M1, M2 ... M8, M9 are not particularly limited, but have the cell structure shown in FIG. 2, for example. This is the 1987 International Electron Device
It is a memory cell sectional view of a flash memory announced in Meeting pp.560-563. Each memory cell is composed of one memory transistor element including a control gate electrode 1, a floating gate 2, a drain electrode 3, and a source electrode 4. Writing is performed by injecting hot carriers generated in the vicinity of the drain junction into the floating gate 2 as in the EPROM. By writing, the threshold value seen from the control gate electrode 1 of the memory cell becomes high. On the other hand, for erasing, a high electric field is generated between the floating gate 2 and the source electrode 4 by applying a high voltage to the source electrode 4 by grounding the control gate 1 and utilizing the tunnel phenomenon through the thin oxide film 6. This is done by extracting the electrons accumulated in the floating gate 1 to the source. For reading, a low voltage of about 1 V is applied to the drain so that weak writing is unlikely to occur, and about 5 V is applied to the control gate 1. The magnitude of the channel current flowing at this time is made to correspond to the logic "0" and the logic "1" of the information. In the figure, 6 is a p-type silicon substrate, 7 is a high-concentration n-type source / drain diffusion layer, 8 is a low-concentration n-type diffusion layer on the source side, and 9 is a high-concentration p-type diffusion layer on the drain side. is there. Also, 1991 Symposium on VLSI Technology p
In the erase method announced on p.77-78, a negative voltage is applied to the word line W connected to the control gate electrode 1 and a relatively low positive voltage is applied to the source electrode 4 in the sectional view of the flash memory cell of FIG. , For example, a power supply voltage Vcc is applied. According to this method, the control gate electrode 1 of the memory cell is
By selectively applying a negative voltage to the word line connected to, sector erasing for partially erasing cells in the memory array is realized. Further, since a low voltage is applied to the source electrode 4, the low concentration n-type diffusion layer 8 is unnecessary,
It is easy to miniaturize the memory cell.

At the time of writing, the internal signals ce and we are set to the high level. The source potential is set to the output potential Vss of the source potential control circuit SVC. A high voltage Vpp is supplied as an operating voltage to the row and column address decoder circuits XDCR and YDCR and the data input circuit DIB. The voltage of the word line W to be written becomes the above-mentioned high voltage Vpp. The data line D connected to the memory cell for injecting electrons into the floating gate is connected to the same high voltage Vpp as described above. As a result, writing is performed in the memory cell. In the written memory cell in the logic "0" state, electrons are accumulated in the floating gate.

At the time of erasing, the internal signals ce and er described above are used.
Is brought to a high level. When the erase signal er generated from the timing control circuit CONT is at high level, the source potential control circuit SVC is supplied with the high voltage Vpp or the voltage Vcc for erase. As a result, erasing is performed.
However, when the voltage is Vcc, a negative voltage is applied to the control gate potential, that is, the word potential. At this time, a high electric field from the control gate to the source acts, the electrons accumulated in the floating gate of the memory cell are extracted to the source line side by the tunnel phenomenon, and the state of logic "1" is restored to perform the erase operation. Be done.

Each operation may be designated by a command system in which a control signal for instructing an operation such as writing or erasing is supplied from the external terminal I / O. The high voltage Vpp may be a potential obtained by boosting the power supply voltage Vcc inside the integrated circuit chip instead of being supplied from the outside.

At the time of normal reading of binary information corresponding to the magnitude of the current flowing through the semiconductor nonvolatile memory cell and the transistor of the memory cell, the internal signal se is read.
And ce are set to the high level, and the source potential is set to the ground potential Vss by the source potential control circuit SVC. Row address decoder circuit, column address decoder circuit XDC
The power supply voltage Vcc is supplied to the R, YDCR, the sense amplifier SA and the data input circuit DIB as its operating voltage. The voltage of the word line W connected to the memory cell to be read out becomes the power supply voltage Vcc. Data line D
Is supplied with a low voltage of about 1 V from the sense amplifier SA so that weak writing is unlikely to occur. In the written memory cell in the logic "0" state, electrons are accumulated in the floating gate, the threshold voltage becomes high, and the drain current does not flow even if the word line W is selected at the time of reading. The threshold voltage of the memory cell in the state of logic "1" in which electrons are not injected is low, and when the word line W is selected, a current flows. This current is received by the sense amplifier SA and is output to the external terminal I / O through the data output circuit DOB. As a result, normal reading of the memory array is performed.

In contrast to normal reading which reads binary information corresponding to the magnitude of the current flowing in the transistor of the memory cell, when reading the memory cells after erasing and reading the memory cells distributed in the low threshold, The internal signals se, ce and ev are set to high level. The common source CS of the memory array is a source potential control circuit SVC.
Then, the ev signal is received and the low positive voltage Vms is obtained.

In the flash memory, it is necessary to precisely control the threshold voltage of the transistor of the memory cell, which causes erroneous reading, so as not to become a negative voltage. It is necessary to repeat the operation of reading (that is, erase bafi) to confirm whether the erase is sufficient, and if not, erase. That is, the reading for controlling the continuation and the stop of the erasing (at the erase-baifing) is performed by applying a low positive voltage to the source electrode of the memory cell and setting the power supply voltage Vcc as the verify voltage. By setting the control gate, that is, the word line voltage and the power supply voltage of the sense amplifier SA at the time of reading (at the time of erase verify) to the verify voltage Vev, the upper limit value of the threshold voltage distribution can be controlled. The verify voltage Vev and the source electrode voltage Vms are such that the transistors of all the memory cells of the memory array do not have negative threshold voltages, that is, they do not have negative threshold values under highly variable voltage conditions.
To set.

The power supply voltage Vcc is supplied as a verify voltage Vev to the row address decoder circuit, the column address decoder circuits XDCR and YDCR, the sense amplifier SA and the data input circuit DIB as its operating voltage. The potential of the word line W connected to the memory cell to be read out becomes the verify voltage Vev. The potential of the data line D is
The power supply voltage of the sense amplifier SA becomes a low voltage of about 1V even if it is the verify voltage Vev. When the word line W is selected and the threshold value of the memory cell is below a certain value, a current flows. The sense amplifier SA receives this current, and the data output circuit DOB
Is output to the external terminal I / O. As a result, verification after erasing and reading of the low threshold memory cell are performed.

It is assumed that a certain power supply voltage Vcc is supplied to the control gate of the memory and the sense amplifier circuit. At this time, the drain voltage of the memory, that is, the data line voltage supplied from the sense amplifier circuit becomes substantially constant regardless of the source voltage of the memory. Further, the current sensitivity for determining the logic "0" and the logic "1" of the information in the sense amplifier circuit also has a substantially constant value without depending on the source voltage. Here, if the potential of the source is raised to a low positive voltage Vms while keeping the threshold value of the memory at a certain value, the gate-source voltage and the drain-source voltage decrease, and the current flowing through the memory decreases. .. That is, unless the potential Vms is applied to the source, the threshold voltage of the memory must be lowered so that a current equal to the current when the source voltage is 0 V cannot flow in the sense amplifier circuit. In other words, if the threshold value of the memory is constant, by raising the potential of the source, the power supply voltage Vccmin at which read information is inverted between "0" and "1" can be lowered, and the low threshold value Vth. It is possible to detect up to. In order to know the threshold voltage distribution of the transistors of each memory cell of the memory array having a low threshold value after erasing, a positive voltage Vms lower than the drain voltage is applied to the source electrode of the memory cell, and the control gate or word line This can be done by changing the power source voltage Vcc of the voltage and measuring the lower limit Vccmin of the operable power source voltage. By this reading method, the threshold voltage Vth of the memory cell transistor is 1: 1 with the operable lower limit power supply voltage Vccmin.
In the realistic range of the power supply voltage Vcc,
The distribution of the low threshold voltage Vth of the transistor of each memory cell after erasing can be known. For example, if the source electrode potential Vms is 0.8V, the threshold value from 0V can be determined.

Further, according to this read method, it is possible to further control the continuation and stop of erasing based on the read information. At this time, the control gate, that is, the power supply voltage of the word line voltage is not set to the verify voltage Vev of another power supply voltage,
A constant power supply voltage supplied from the outside or a control gate or word line voltage for reading binary information of the memory cell can be used.

The voltage Vms applied to the source of the memory is supplied from the outside or the source potential control circuit S of the built-in power source.
It is sufficient if the voltage supplied from VC is a constant voltage or a voltage that depends on the power supply voltage Vcc and is lower than the drain voltage during reading, that is, the data line voltage. The sense amplifier circuit SA of FIG. 7 is not limited to the current sense amplifier circuit of FIGS. 1 and 3, and may be a differential type sense amplifier circuit. The array of memory cells is not limited to that shown in FIG. 7, and may be an array of memory cells as a block in which some memory cells are arranged in parallel and in series. Further, the drain voltage at the time of reading the memory cell is set to a low voltage of about 1 V so that weak writing is less likely to occur. Can apply a voltage of about 1 V or more and can increase the memory cell current, resulting in faster read speed. For reading that controls distribution of low threshold voltage and stop of erasing, a voltage lower than the drain voltage may be applied to the source electrode of the memory.

The source potential control circuit SV is shown in FIGS.
An example of C is shown. The source potential control circuit SVC is not limited to these embodiments. 9 to 11 are circuits that output the source voltage Vms that depends on the power supply voltage Vcc, and FIGS. 8, 12, and 13 are circuits that output a constant voltage that does not depend on the power supply voltage Vcc. Switch sw1 ... s
A MOSFET may be used for w7.

Input signal e of the source potential control circuit SVC
The r, ev and the output signals Vms, Vss, Vcc are defined as follows, for example. The output signal is Vms when the er signal and the ev signal are at the high level, the output signal is Vss when the er signal and the ev signal are at the low level, and the output signal is Vcc when only the er signal is at the high level.

In the embodiment of FIG. 8, the era signal is the er signal, and when the ev signal is at high level, the external power supply Vpp is set to Vms. In the embodiment of FIG. 9, the erb signal is the negative signal of the er signal and the erc signal is the ev signal. In the embodiment of FIG. 10, the erd signal is a negative signal of the er signal. When the ev signal is high level, the switch sw2 is on, the switch sw1 is off, and when the ev signal is low level, the switch sw1 is on and the switch sw2 is The off state becomes. In the embodiment of FIG. 11, when the er signal is at the high level, the switch sw4 is in the ON state, and the switch sw is
3 is an off state, and when the er signal is low level, the switch sw
3 is in the on state, switch sw4 is in the off state, and
The re signal is an ev signal. 12 and 13 show an embodiment using the operational amplifier OA and the reference voltage circuit Vref. When the er signal and the ev signal are at the high level, the switch sw7 is in the on state, when the er signal and the ev signal are at the low level, the switch sw6 is in the on state, and when only the er signal is at the high level, the switch sw5 is in the on state.
According to the method described above, the source potential becomes the ground potential Vss during writing and normal reading, the power supply voltage Vcc or Vpp during erasing, and the low voltage Vms during erasing verify and low threshold reading. The Vnn potential in FIG. 13 is a negative voltage power supply. It is effective in erasing with a negative voltage applied to the word line connected to the control gate.

[0050]

As described above, according to the present invention, in an electrically erasable semiconductor nonvolatile memory device, variations in low threshold voltage of transistors of each memory cell after electrically erasing are performed. Since it is possible to measure the distribution of, the effect of ensuring the margin up to the negative threshold voltage that causes erroneous reading and the process stability can be obtained. Further, the threshold voltage can be lowered by further controlling the continuation and stop of erasing based on the read information, which has the effect of increasing the operation margin such as the reading speed.

[Brief description of drawings]

FIG. 1 is a block diagram of a semiconductor nonvolatile memory device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a transistor of the semiconductor nonvolatile memory cell of the embodiment of FIG.

FIG. 3 is a circuit diagram of a sense amplifier circuit of a conventional semiconductor nonvolatile memory device.

FIG. 4 is a diagram showing read static characteristics of the conventional sense amplifier circuit of FIG.

5 is a diagram showing a relationship between a threshold Vth of a memory cell of the conventional sense amplifier circuit of FIG. 3 and an operable lower limit power supply voltage Vccmin.

FIG. 6 is a diagram showing a relationship between a threshold Vth of a memory cell and an operable lower limit voltage Vccmin according to the present invention.

FIG. 7 is a circuit diagram of a semiconductor nonvolatile memory device according to a more specific embodiment of the present invention.

8 is a diagram showing a circuit example of a source potential control circuit SVC used in the embodiment of FIG.

9 is a diagram showing a circuit example of a source potential control circuit SVC used in the embodiment of FIG.

10 is a diagram showing a circuit example of a source potential control circuit SVC used in the embodiment of FIG.

11 is a diagram showing a circuit example of a source potential control circuit SVC used in the embodiment of FIG.

12 is a diagram showing a circuit example of a source potential control circuit SVC used in the embodiment of FIG.

13 is a diagram showing a circuit example of a source potential control circuit SVC used in the embodiment of FIG.

[Explanation of symbols]

SVC: Source potential control circuit, SA: Sense amplifier, X
DCR, YDCR: row and column address decoder, XAD
B, YADB: row, column address buffer, DOB, DI
B: output, input buffer, CONT: timing control circuit, OA: operation amplifier circuit, Vref: reference voltage circuit, M1 to M9: memory cells, Q1 to Q33: M
OSFET, C: capacitance, W1 to Wn: word line, D1 to
Dm: data line CS: common source line, CD: common data line, so: sense amplifier output signal, Vss: ground voltage,
Vcc: power supply voltage, Vpp: high voltage, Vms: low voltage,
Vev: verify voltage, Vnn: negative voltage, 1: control gate, 2: floating gate, 3: drain, 4: source,
5: oxide film, 6: p-type substrate, 7: n-type diffusion layer, 8: low concentration n-type diffusion layer, 9: p-type diffusion layer, AX, AY: row, column address signal, / CE, / OE, / WE, / EE, I /
O: external terminal, se, we, ce, er, ev: timing signal, era to ere: control signal, sw1 to sw
7: Switch

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Koichi Seki Koichi Seki 1-280, Higashi Koigokubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (8)

[Claims] 1. A semiconductor non-volatile memory cell, a read circuit for reading binary information corresponding to the magnitude of a current flowing through a transistor of the memory cell, and a drain voltage, that is, a data line of a source electrode of the transistor of the memory cell. A semiconductor non-volatile memory device comprising: an applying unit that applies a positive voltage lower than the voltage. 2. The transistor of the memory cell is a MOSF having a two-layer gate structure of a floating gate and a control gate.
The semiconductor nonvolatile memory device according to claim 1, wherein the semiconductor nonvolatile memory device is ET. 3. A semiconductor non-volatile memory cell, and a read circuit for reading binary information corresponding to the magnitude of the current flowing through the transistor of the memory cell, the potential of the source electrode of the transistor of the memory cell being set. While applying a ground potential during normal reading, an application means is further provided for applying the potential of the source electrode of the transistor of the memory cell to a drain voltage, that is, a positive voltage lower than the voltage of the data line when reading a memory cell having a low threshold value. A semiconductor non-volatile memory device comprising: 4. A semiconductor non-volatile memory cell and a read circuit for reading binary information corresponding to the magnitude of the current flowing through the transistor of the memory cell, the potential of the source electrode of the transistor of the memory cell being set. While the ground potential is used during normal reading, the potential of the source electrode of the transistor of the memory cell is set to the drain voltage, that is, a positive voltage lower than the voltage of the data line when reading the low threshold voltage distribution of the transistor of each memory cell. A semiconductor non-volatile memory device, further comprising: an applying unit that applies a voltage to change a gate potential of a transistor of the memory cell. 5. A semiconductor non-volatile memory cell, and a read circuit for reading binary information corresponding to the magnitude of a current flowing through a transistor of the memory cell are provided, and an electrical erasing operation of the memory cell is performed. After that, a drain voltage, that is, a positive voltage lower than the voltage of the data line is applied to the source electrode of the transistor of the memory cell to determine the threshold value of the transistor of the memory cell. apparatus. 6. A semiconductor non-volatile memory cell, and a read circuit for reading binary information corresponding to the magnitude of a current flowing through a transistor of the memory cell, and electrically erasing the memory cell. The subsequent read is performed by applying a drain voltage, that is, a positive voltage lower than the voltage of the data line to the source electrode of the transistor, and further controlling the continuation and stop of erasing based on the read information. Semiconductor nonvolatile memory device. 7. A semiconductor non-volatile memory cell, and a read circuit for reading binary information corresponding to the magnitude of a current flowing through a transistor of the memory cell are provided, and the electrical erasing operation of the memory cell is performed. In the subsequent reading, the gate electrode of the transistor, that is, the voltage of the word line is set as a constant power supply voltage supplied from the outside, and the drain voltage, that is, a positive voltage lower than the voltage of the data line is applied to the source electrode for reading, A semiconductor non-volatile memory device characterized by further controlling the continuation and termination of erasing based on the read information. 8. A semiconductor non-volatile memory cell, and a read circuit for reading binary information corresponding to the magnitude of a current flowing through a transistor of the memory cell, and electrically erasing the memory cell. Later read, the gate electrode of the transistor, that is, the voltage of the word line is set to 2
The value information is set to a voltage equal to the potential to be read, a drain voltage, that is, a positive voltage lower than the voltage of the data line is applied to the source electrode for reading, and the continuation and stop of erasing are further controlled based on the read information. And a semiconductor nonvolatile memory device.