JPH05283382A - Rear processing method of semiconductor wafer and surface side structure of semiconductor wafer at the time of rear processing - Google Patents

Rear processing method of semiconductor wafer and surface side structure of semiconductor wafer at the time of rear processing

Info

Publication number
JPH05283382A
JPH05283382A JP7688592A JP7688592A JPH05283382A JP H05283382 A JPH05283382 A JP H05283382A JP 7688592 A JP7688592 A JP 7688592A JP 7688592 A JP7688592 A JP 7688592A JP H05283382 A JPH05283382 A JP H05283382A
Authority
JP
Japan
Prior art keywords
semiconductor wafer
surface side
wafer
film body
rear processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7688592A
Other languages
Japanese (ja)
Inventor
Shinji Tanaka
伸治 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP7688592A priority Critical patent/JPH05283382A/en
Publication of JPH05283382A publication Critical patent/JPH05283382A/en
Pending legal-status Critical Current

Links

Landscapes

  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PURPOSE:To provide a rear processing method of a semiconductor allowing execution while securing a parallel state to a wafer support of a semiconductor wafer and the surface side structure of the semiconductor wafer time of rear processing. CONSTITUTION:A rear processing method of a semiconductor wafer 1 includes a process of overall covering the surface side of the semiconductor wafer to be subjected to rear processing by a film body 10, a process of forming a plurality of groove parts 11 opening while being taken out up to an outer end edge of the semiconductor wafer 1 on the prescribed spots of the film body 10 respectively and a process of putting on the surface side of the semiconductor wafer 1 covered by the film body 10 on the wafer support 2 through wax 3 for junction followed by press. Further, as to the surface side structure of the semiconductor wafer 1, its surface side is overall covered by the film body 10, a plurality of groove parts 11 opening while being taken out up to an outer end edge of the semiconductor wafer 1 are formed on the prescribed sports of this film body 10.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体ウェハの裏面加
工方法及び裏面加工時における半導体ウェハの表面側構
造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for processing a back surface of a semiconductor wafer and a front surface side structure of the semiconductor wafer at the time of processing the back surface.

【0002】[0002]

【従来の技術】従来から、半導体素子を製造する際に
は、その実装時における熱放散機能を高めるべく、半導
体ウェハの段階において基板厚みを100μm程度以下
にまで薄くしておくことが行われており、基板厚みを薄
くするには半導体ウェハをその裏面側から少しずつ削り
取っていく方法を採用するのが一般的となっている。そ
して、このような裏面加工の実施にあたっては、図3で
例示するような支持構造、すなわち、裏面加工すべき半
導体ウェハ1と、半導体ウェハ1の表面側を支持するウ
ェハ支持体2とを、接合用ワックス3を介して貼り合わ
せてなる支持構造が利用されており、この半導体ウェハ
1は次のような手順に従って裏面加工されるようになっ
ている。
2. Description of the Related Art Conventionally, when manufacturing a semiconductor element, in order to enhance a heat dissipation function at the time of mounting the semiconductor element, the substrate thickness is thinned to about 100 μm or less at a semiconductor wafer stage. Therefore, in order to reduce the thickness of the substrate, it is general to employ a method of gradually scraping the semiconductor wafer from the back surface side. Then, in carrying out such back surface processing, a support structure as illustrated in FIG. 3, that is, a semiconductor wafer 1 to be back processed and a wafer support 2 supporting the front surface side of the semiconductor wafer 1 are bonded together. A supporting structure formed by laminating via a wax 3 is used, and the semiconductor wafer 1 is processed on the back surface according to the following procedure.

【0003】まず、裏面加工すべき半導体ウェハ1と対
面してこれを全面的に支持するガラス製の円板をウェハ
支持体2として用意したうえ、その一面上に接合用ワッ
クス3を塗布して溶融させる。つぎに、この熔融状態に
ある接合用ワックス3に対して半導体ウェハ1の加工済
みとなった表面を押し付けることにより、この接合用ワ
ックス3を介して半導体ウェハ1とウェハ支持体2とを
互いに貼り合わせる。そして、接合用ワックス3を固化
させて半導体ウェハ1及びウェハ支持体2を一体化した
後、ウェハ支持体2の他面、すなわち、半導体ウェハ1
が貼り合わされていない面(図では、下側面)を加工基
準としながら半導体ウェハ1の裏面(図では、上側面)
に対する研磨もしくは研削を行って基板厚みが所定厚み
となるまで薄く加工する。
First, a glass disk, which faces the semiconductor wafer 1 to be processed on the back surface and supports the entire surface, is prepared as a wafer support 2, and a bonding wax 3 is applied to one surface thereof. Melt. Next, by pressing the processed surface of the semiconductor wafer 1 against the bonding wax 3 in the molten state, the semiconductor wafer 1 and the wafer support 2 are attached to each other via the bonding wax 3. To match. Then, after solidifying the bonding wax 3 to integrate the semiconductor wafer 1 and the wafer support 2, the other surface of the wafer support 2, that is, the semiconductor wafer 1
The back surface of the semiconductor wafer 1 (upper side surface in the figure) while using the surface not bonded (lower side surface in the figure) as a processing reference.
By polishing or grinding, the substrate is thinly processed until it has a predetermined thickness.

【0004】[0004]

【発明が解決しようとする課題】ところで、前述したよ
うな半導体ウェハ1の裏面加工は、この半導体ウェハ1
を支持するウェハ支持体2を加工基準として行われるの
であるから、半導体ウェハ1とウェハ支持体2との平行
状態が確保されているか否かが裏面加工時における重要
な要素となる。そして、これら両者の平行状態が確保さ
れているか否かは、半導体ウェハ1とウェハ支持体2と
の間に介在する接合用ワックス3の厚みが両者間のいず
れの箇所においても均一となっているか否かに基づいて
定まることになる。
By the way, the back surface processing of the semiconductor wafer 1 as described above is performed by this semiconductor wafer 1.
Since the wafer support 2 for supporting the wafer is used as a processing reference, whether or not the parallel state between the semiconductor wafer 1 and the wafer support 2 is ensured is an important factor during the back surface processing. Whether or not the parallel state between these two is ensured is whether or not the thickness of the bonding wax 3 interposed between the semiconductor wafer 1 and the wafer support 2 is uniform at any position between them. It will be decided based on whether or not.

【0005】しかしながら、接合用ワックス3を利用し
て半導体ウェハ1とウェハ支持体2とを全面的に貼り合
わせた場合、接合用ワックス3が均一な厚みで両者間に
介在することになるとは限らず、図3で示したように、
半導体ウェハ1とウェハ支持体2との間に接合用ワック
ス3のうちの過剰分までもが残ってしまい、接合用ワッ
クス3の厚みが不均一となる結果、この接合用ワックス
3を介して貼り付けられた半導体ウェハ1が傾いた姿勢
のままでウェハ支持体2と一体化されてしまうことが起
こる。そして、このようになっていると、傾いた状態の
ままで半導体ウェハ1の裏面加工が行われることにな
り、基板厚みが不均一となる結果、得られた半導体素子
それぞれにおける厚みが互いにばらつくという不都合が
生じてしまう。
However, when the semiconductor wafer 1 and the wafer support 2 are bonded together using the bonding wax 3, the bonding wax 3 does not always have a uniform thickness therebetween. Instead, as shown in FIG.
Excessive amount of the bonding wax 3 remains between the semiconductor wafer 1 and the wafer support 2, and the thickness of the bonding wax 3 becomes non-uniform. It may happen that the attached semiconductor wafer 1 is integrated with the wafer support 2 in an inclined posture. Then, in such a case, the back surface processing of the semiconductor wafer 1 is performed in an inclined state, and as a result of the substrate thickness becoming nonuniform, the obtained semiconductor elements have different thicknesses. It causes inconvenience.

【0006】本発明は、このような不都合に鑑みて創案
されたものであって、半導体ウェハのウェハ支持体に対
する平行状態を確保しつつ実施することのできる半導体
ウェハの裏面加工方法及び裏面加工時における半導体ウ
ェハの表面側構造の提供を目的としている。
The present invention was devised in view of such inconveniences, and can be carried out while ensuring the parallel state of the semiconductor wafer with respect to the wafer support. In order to provide a front surface side structure of a semiconductor wafer in.

【0007】[0007]

【課題を解決するための手段】本発明にかかる半導体ウ
ェハの裏面加工方法は、裏面加工すべき半導体ウェハの
表面側を膜体によって全面的に覆う工程と、前記半導体
ウェハの外側端縁にまで引き出されて開口する複数本の
溝部を前記膜体の所定箇所それぞれに形成する工程と、
前記膜体によって覆われた前記半導体ウェハの表面側を
接合用ワックスを介してウェハ支持体上に載せ付けたう
えで押圧する工程とを含むことを特徴としている。ま
た、裏面加工時における半導体ウェハの表面側構造は、
ウェハ支持体によって支持される半導体ウェハの表面側
が膜体によって全面的に覆われており、この膜体の所定
箇所それぞれには前記半導体ウェハの外側端縁にまで引
き出されて開口する複数本の溝部が形成されていること
を特徴とするものである。
A method of processing a back surface of a semiconductor wafer according to the present invention comprises a step of entirely covering a front surface side of a semiconductor wafer to be processed by a film body with a film body and an outer edge of the semiconductor wafer. A step of forming a plurality of groove portions that are pulled out and opened at predetermined positions of the film body,
And a step of placing the front surface side of the semiconductor wafer covered with the film body on a wafer support through a bonding wax and pressing the wafer support. Also, the structure of the front surface side of the semiconductor wafer during back surface processing is
The surface side of the semiconductor wafer supported by the wafer support is entirely covered with a film body, and a plurality of groove portions that are drawn out to the outer edge of the semiconductor wafer and open at predetermined positions of the film body. Are formed.

【0008】[0008]

【作用】上記方法によれば、膜体によって覆われた半導
体ウェハの表面側をウェハ支持体上に載せ付けたうえで
押圧すると、接合用ワックスの過剰分は膜体に形成され
た溝部を伝わりながら半導体ウェハの外側端縁にまで速
やかに押し出されることになる。そこで、半導体ウェハ
の表面側を覆う膜体とウェハ支持体との間には余分な接
合用ワックスが介在しなくなり、これらの両者間におけ
る接合用ワックスの厚みが均一化される結果、両者の平
行状態が確保されることになる。
According to the above method, when the front surface side of the semiconductor wafer covered with the film is placed on the wafer support and then pressed, the excess amount of the bonding wax is transmitted through the groove formed in the film. However, it is quickly extruded to the outer edge of the semiconductor wafer. Therefore, the extra bonding wax does not exist between the film body covering the front surface side of the semiconductor wafer and the wafer support, and the thickness of the bonding wax between both of them is made uniform. The state will be secured.

【0009】[0009]

【実施例】以下、本発明の実施例を図面に基づいて説明
する。
Embodiments of the present invention will be described below with reference to the drawings.

【0010】図1は裏面加工時における半導体ウェハの
表面側構造及びその支持構造を示す分解斜視図であり、
図2は貼り合わせ状態を示す側断面図である。なお、こ
れらの図において従来例を示す図3と互いに同一もしく
は相当することになる部品、部分については同一符号を
付し、ここでの詳しい説明は省略する。
FIG. 1 is an exploded perspective view showing the front surface side structure of a semiconductor wafer and its supporting structure at the time of processing the back surface.
FIG. 2 is a side sectional view showing a bonded state. In these figures, parts and portions which are the same as or correspond to those in FIG. 3 showing the conventional example are denoted by the same reference numerals, and detailed description thereof is omitted here.

【0011】本実施例にかかる支持構造は、裏面加工す
べき半導体ウェハ1と、半導体ウェハ1の表面側を全面
的に支持するウェハ支持体2とを、接合用ワックス3を
介して貼り合わせてなる構造を有する一方、半導体ウェ
ハ1の表面側構造としては、半導体ウェハ1の表面側を
所定厚みの膜体10によって全面的に覆ったうえ、この
膜体10の所定箇所それぞれには半導体ウェハ1の外側
端縁にまで引き出されて開口する複数本の溝部11を形
成した構造が採用されている。すなわち、この半導体ウ
ェハ1の既に加工済みとなった表面上には保護膜(図示
していない)を介して数μmの厚みとされた膜体10で
あるレジスト膜が形成されており、かつ、このレジスト
膜には複数本の溝部11が縦横の向きに沿って形成され
ている。なお、この膜体10がレジスト膜に限定される
ものではなく、絶縁性樹脂シートなどであってもよいこ
とは勿論である。また、ここで、半導体ウェハ1と対面
してこれを支持するウェハ支持体2としては、従来例同
様、ガラス製の円板が用いられている。
In the support structure according to the present embodiment, a semiconductor wafer 1 to be processed on the back surface and a wafer support 2 which entirely supports the front surface side of the semiconductor wafer 1 are bonded together via a bonding wax 3. On the other hand, as a front surface side structure of the semiconductor wafer 1, the front surface side of the semiconductor wafer 1 is entirely covered with a film body 10 having a predetermined thickness, and the semiconductor wafer 1 is provided at each predetermined position of the film body 10. A structure in which a plurality of groove portions 11 that are drawn out and open to the outer edge of is formed is adopted. That is, a resist film, which is the film body 10 having a thickness of several μm, is formed on the already processed surface of the semiconductor wafer 1 through a protective film (not shown), and A plurality of groove portions 11 are formed in this resist film along the vertical and horizontal directions. The film body 10 is not limited to the resist film, and it goes without saying that it may be an insulating resin sheet or the like. As the wafer support 2 that faces the semiconductor wafer 1 and supports it, a glass disk is used as in the conventional example.

【0012】つぎに、このような支持構造及び表面側構
造を有する半導体ウェハ1の裏面加工方法を手順に従っ
て説明する。
Next, a method of processing the back surface of the semiconductor wafer 1 having such a support structure and a front surface side structure will be described according to the procedure.

【0013】まず、半導体ウェハ1の表面側におけるレ
ジスト膜形成及びパターニングを行うことにより、この
半導体ウェハ1の表面側を全面的に覆う膜体10として
のレジスト膜及び複数本の溝部11を形成する。そし
て、この際、溝部11のそれぞれは半導体ウェハ1のス
クライブライン(図示していない)に沿って形成すれ
ば、スクライブラインの幅が40μm程度であるのに対
して溝部11の幅は合わせマージンを十分に確保しうる
20μm程度でよいことになる。次いで、ガラス製の円
板をウェハ支持体2として用意し、その一面上にスカイ
ワックス(商品名)のような接合用ワックス3を塗布し
たうえで溶融させる。
First, by forming and patterning a resist film on the front surface side of the semiconductor wafer 1, a resist film as a film body 10 covering the front surface side of the semiconductor wafer 1 and a plurality of groove portions 11 are formed. .. At this time, if each of the groove portions 11 is formed along a scribe line (not shown) of the semiconductor wafer 1, the width of the scribe line is about 40 μm, whereas the width of the groove portion 11 has an alignment margin. About 20 μm, which can be sufficiently secured, is sufficient. Next, a glass disk is prepared as the wafer support 2, and one surface thereof is coated with a bonding wax 3 such as sky wax (trade name) and then melted.

【0014】その後、この熔融状態にある接合用ワック
ス3に対して半導体ウェハ1を押し付け、すなわち、そ
の表面上を覆う膜体10から接合用ワックス3に向かう
ようにして押し付けることにより、この接合用ワックス
3を介して半導体ウェハ1とウェハ支持体2とを全面的
に貼り合わせる。さらに、このような貼り合わせを行っ
た後、互いに貼り合わされた半導体ウェハ1及びウェハ
支持体2を貼り合わせ方向に沿って押圧すると、接合用
ワックス3の過剰分は半導体ウェハ1の表面上を覆う膜
体10に形成された溝部11を伝わりながら半導体ウェ
ハ1の外側端縁にまで押し出されてくる。そこで、これ
らの互いに貼り合わされた半導体ウェハ1とウェハ支持
体2との間には余分な接合用ワックス3が介在しないこ
とになり、これらの両者間における接合用ワックス3の
厚みは均一化される。
Thereafter, the semiconductor wafer 1 is pressed against the bonding wax 3 in the molten state, that is, the semiconductor wafer 1 is pressed toward the bonding wax 3 from the film body 10 covering the surface thereof. The semiconductor wafer 1 and the wafer support 2 are bonded to each other with the wax 3 in between. Furthermore, after such bonding is performed, when the semiconductor wafer 1 and the wafer support 2 bonded together are pressed along the bonding direction, the excess amount of the bonding wax 3 covers the surface of the semiconductor wafer 1. While being transmitted through the groove portion 11 formed in the film body 10, it is pushed out to the outer edge of the semiconductor wafer 1. Therefore, the extra bonding wax 3 does not exist between the semiconductor wafer 1 and the wafer support 2 bonded to each other, and the thickness of the bonding wax 3 between them is made uniform. ..

【0015】引き続き、接合用ワックス3の固化によっ
て半導体ウェハ1及びウェハ支持体2を一体化したう
え、ウェハ支持体2の他面、すなわち、半導体ウェハ1
が貼り合わされていない面(図では、下側面)を加工基
準としながら半導体ウェハ1の裏面(図では、上側面)
に対する研磨もしくは研削を行って基板厚みが所定厚み
となるまで薄く加工する。そして、半導体ウェハ1の裏
面加工が終了すると、接合用ワックス3を溶解しうる剥
離用溶剤を用いることによってウェハ支持体2から半導
体ウェハ1を剥離する。なお、この際には、半導体ウェ
ハ1の表面上を覆う膜体10に形成された溝部11を通
じて剥離用溶剤が浸透するため、剥離作業に要する時間
が短くて済むことになると同時に、膜体10であるレジ
スト膜によって素子表面の保護が行われるという利点が
ある。
Subsequently, the semiconductor wafer 1 and the wafer support 2 are integrated by solidifying the bonding wax 3, and the other surface of the wafer support 2, that is, the semiconductor wafer 1 is integrated.
The back surface of the semiconductor wafer 1 (upper side surface in the figure) while using the surface not bonded (lower side surface in the figure) as a processing reference.
By polishing or grinding, the substrate is thinly processed until it has a predetermined thickness. Then, when the back surface processing of the semiconductor wafer 1 is completed, the semiconductor wafer 1 is peeled from the wafer support 2 by using a peeling solvent capable of dissolving the bonding wax 3. At this time, since the stripping solvent penetrates through the groove 11 formed in the film body 10 covering the surface of the semiconductor wafer 1, the time required for the stripping work can be shortened, and at the same time, the film body 10 There is an advantage that the element surface is protected by the resist film.

【0016】さらに、ウェハ支持体2から剥離された半
導体ウェハ1をアセトンなどの溶剤中に浸漬し、その表
面上からレジスト膜を取り去った後、次工程において半
導体ウェハ1のスクライブを行うと、個々に分割された
半導体素子が得られる。
Further, the semiconductor wafer 1 separated from the wafer support 2 is dipped in a solvent such as acetone, the resist film is removed from the surface, and then the semiconductor wafer 1 is scribed in the next step. A semiconductor element divided into two is obtained.

【0017】[0017]

【発明の効果】以上説明したように、本発明にかかる半
導体ウェハの裏面加工方法及び裏面加工時における半導
体ウェハの表面側構造によれば、膜体によって覆われた
半導体ウェハの表面側とウェハ支持体との間に余分な接
合用ワックスが介在することはなくなり、これらの両者
間における接合用ワックスの厚みが均一化される結果、
半導体ウェハのウェハ支持体に対する平行状態が確保さ
れることになる。そのため、このウェハ支持体を加工基
準として裏面加工された半導体ウェハ及びこれから得ら
れる半導体素子それぞれにおける基板厚みもばらつくこ
となく均一になるという効果が得られる。
As described above, according to the method of processing the back surface of the semiconductor wafer and the structure of the front surface side of the semiconductor wafer during the back surface processing according to the present invention, the front surface side of the semiconductor wafer covered by the film body and the wafer support. No extra bonding wax is present between the body and the thickness of the bonding wax between these two is made uniform,
The parallel state of the semiconductor wafer with respect to the wafer support is ensured. Therefore, it is possible to obtain an effect that the substrate thickness of the semiconductor wafer whose back surface is processed with the wafer support as a processing reference and the semiconductor element obtained from each of the wafers are uniform without variation.

【図面の簡単な説明】[Brief description of drawings]

【図1】裏面加工時における半導体ウェハの表面側構造
及びその支持構造を示す分解斜視図である。
FIG. 1 is an exploded perspective view showing a structure on a front surface side of a semiconductor wafer and a supporting structure thereof when a back surface is processed.

【図2】その貼り合わせ状態を示す側断面図である。FIG. 2 is a side sectional view showing the pasted state.

【図3】従来例にかかる裏面加工時における半導体ウェ
ハの支持構造の貼り合わせ状態を示す側断面図である。
FIG. 3 is a side sectional view showing a bonded state of a support structure for a semiconductor wafer during backside processing according to a conventional example.

【符号の説明】[Explanation of symbols]

1 半導体ウェハ 2 ウェハ支持体 3 接合用ワックス 10 膜体 11 溝部 1 Semiconductor Wafer 2 Wafer Support 3 Wax for Bonding 10 Membrane 11 Groove

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 裏面加工すべき半導体ウェハ(1)の表
面側を膜体(10)によって全面的に覆う工程と、 前記半導体ウェハ(1)の外側端縁にまで引き出されて
開口する複数本の溝部(11)を前記膜体(10)の所
定箇所それぞれに形成する工程と、 前記膜体(10)によって覆われた前記半導体ウェハ
(1)の表面側を接合用ワックス(3)を介してウェハ
支持体(2)上に載せ付けたうえで押圧する工程とを含
むことを特徴とする半導体ウェハの裏面加工方法。
1. A step of entirely covering a front surface side of a semiconductor wafer (1) to be processed on the back surface with a film body (10), and a plurality of pieces which are pulled out and opened to an outer edge of the semiconductor wafer (1). Forming a groove part (11) at a predetermined position of the film body (10), and a front surface side of the semiconductor wafer (1) covered with the film body (10) with a bonding wax (3) interposed. And then pressing the wafer support (2) on the wafer support (2).
【請求項2】 ウェハ支持体(2)によって支持される
半導体ウェハ(1)の表面側が膜体(10)によって全
面的に覆われており、この膜体(10)の所定箇所それ
ぞれには前記半導体ウェハ(1)の外側端縁にまで引き
出されて開口する複数本の溝部(11)が形成されてい
ることを特徴とする裏面加工時における半導体ウェハの
表面側構造。
2. The surface side of a semiconductor wafer (1) supported by a wafer support (2) is entirely covered with a film body (10), and each of the predetermined portions of the film body (10) has the above-mentioned structure. A front surface side structure of a semiconductor wafer at the time of backside processing, characterized in that a plurality of groove portions (11) that are drawn out and opened to the outer edge of the semiconductor wafer (1) are formed.
JP7688592A 1992-03-31 1992-03-31 Rear processing method of semiconductor wafer and surface side structure of semiconductor wafer at the time of rear processing Pending JPH05283382A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7688592A JPH05283382A (en) 1992-03-31 1992-03-31 Rear processing method of semiconductor wafer and surface side structure of semiconductor wafer at the time of rear processing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7688592A JPH05283382A (en) 1992-03-31 1992-03-31 Rear processing method of semiconductor wafer and surface side structure of semiconductor wafer at the time of rear processing

Publications (1)

Publication Number Publication Date
JPH05283382A true JPH05283382A (en) 1993-10-29

Family

ID=13618094

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7688592A Pending JPH05283382A (en) 1992-03-31 1992-03-31 Rear processing method of semiconductor wafer and surface side structure of semiconductor wafer at the time of rear processing

Country Status (1)

Country Link
JP (1) JPH05283382A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004058726A3 (en) * 2002-12-23 2004-10-28 Artesian Therapeutics Inc CARDIOTONIC COMPOUNDS WITH INHIBITORY ACTIVITY AGAINST β-ADRENERGIC RECEPTORS AND PHOSPHODIESTERASE

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004058726A3 (en) * 2002-12-23 2004-10-28 Artesian Therapeutics Inc CARDIOTONIC COMPOUNDS WITH INHIBITORY ACTIVITY AGAINST β-ADRENERGIC RECEPTORS AND PHOSPHODIESTERASE

Similar Documents

Publication Publication Date Title
US7521384B2 (en) Method and apparatus for peeling surface protective film
JP3455762B2 (en) Semiconductor device and manufacturing method thereof
JP2001185519A5 (en)
US5169804A (en) Method for fastening a semiconductor, body provided with at least one semiconductor component to a substrate
JP2003197567A (en) Method of manufacturing semiconductor device
JP2658135B2 (en) Semiconductor substrate
JP2994356B1 (en) Wafer surface protection tape peeling device
JPH03278554A (en) Chip tray structure
JPH05283382A (en) Rear processing method of semiconductor wafer and surface side structure of semiconductor wafer at the time of rear processing
JP2616247B2 (en) Method for manufacturing semiconductor device
JPH0917756A (en) Protective type for semiconductor and its usage method
JP2001085453A (en) Method of manufacturing semiconductor device
JP4462940B2 (en) Manufacturing method of semiconductor device
JPS61152358A (en) Grinding method for semiconductor wafer
US6515347B1 (en) Wafer level semiconductor device and method of manufacturing the same
JPH05198671A (en) Dicing method of semiconductor wafer
JP4342340B2 (en) Manufacturing method of semiconductor device
JPH06204267A (en) Manufacture of semiconductor device
JP2846073B2 (en) Method for producing thin film and method for producing X-ray mask
JP2000349138A (en) Stretching device of wafer sheet and method thereof
JPH05109679A (en) Manufacture of semiconductor device
JP2660024B2 (en) Method for manufacturing semiconductor device
JPH0793329B2 (en) How to fix semiconductor pellets
JP2001267342A (en) Method of manufacturing semiconductor device
JP2919415B2 (en) Lead frame