JPH05282864A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To select refresh depending on the charge storing capacity of a memory cell and to contribute to improvement of yield by making different the number of memory mats for selecting a word line depending on a designated refresh cycle. CONSTITUTION:An operation mode specifying means RFC specifies one refresh cycle out of a plurality of refresh cycles. In accordance with an operation mode specified by this operation mode specifying means RFC, a control logic RFC makes different the number of memory mats MARY1 and MARY2 for selecting a word line in a unit memory cycle. According to this constitution, the refresh cycle corresponding to the charge storing capacity of a dynamic type memory cell can be realized internally on a circuit basis. Even when the charge storing capacity is lower than a prescribed value, moreover, it can be relieved without being regarded as defective, and thus a yield can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a dynamic memory cell, and more particularly to a refresh cycle switching or selecting technique in the semiconductor memory device.

[0002]

2. Description of the Related Art A dynamic memory cell holds data as accumulated charge information, but the accumulated charge decreases with time due to undesired leakage. Therefore, the dynamic memory cell needs a refresh operation for rewriting the stored information at every predetermined time. The conventional dynamic type memory has a circuit configuration having one refresh cycle. That is, the interval time for refresh is determined in consideration of the characteristic error due to the circuit characteristics of the semiconductor integrated circuit and the manufacturing process, and the refresh cycle is determined from the time and the memory cycle time. For example, when refreshing is performed every 1024 cycles, the number of word lines selected in a single refresh operation or selection so that refresh operations of all the memory cells are cycled within a predetermined period by performing refresh at that interval. Internal circuitry is configured to determine the number of memory mats to be populated.

Incidentally, as an example of a document describing refreshing of a dynamic type memory, November 3, 1984
"LSI Handbook" No. 492, published by Ohmsha on the 0th
Pages 494.

[0004]

However, in the circuit configuration in which the refresh cycle is one kind, the LSI in which the stored charge retention capability of the memory cell is lower than the specified value in the wafer stage test cannot be avoided. ..

An object of the present invention is to provide a semiconductor memory device in which a refresh cycle can be selected according to the accumulated charge holding ability of a dynamic memory cell. Another object of the present invention is to provide a semiconductor memory device that can be utilized without causing a defect even when the accumulated charge holding capacity of a dynamic memory cell is lower than a specified value, and can contribute to an improvement in yield. It is in.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, in a semiconductor memory device having a plurality of memory mats in which dynamic memory cells are arranged in a matrix, operation mode designating means for designating one refresh cycle from a plurality of refresh cycles, and its operation mode designating means. Control logic for changing the number of memory mats from which word lines should be selected in a unit memory cycle according to the operation mode designated by the means. At this time, as the operation mode designating means, a control register rewritably holding operation mode designating information supplied from the outside, a dedicated external terminal for designating the operation mode, and an operation mode fixed at a predetermined stage of the manufacturing process. It is possible to employ one of the non-volatile storage means set in step 1 or a wiring means that fixedly determines the operation mode at a predetermined stage of the manufacturing process.

[0009]

According to the above means, it is possible to change the number of memory mats whose word lines are to be selected in a unit memory cycle in accordance with a designated refresh cycle because it is possible to retain the accumulated charge of a dynamic memory cell. Of the semiconductor memory device having a dynamic memory cell, which improves the yield of the semiconductor memory device that does not become defective even when the accumulated charge holding capacity is lower than a specified value. ..

[0010]

FIG. 1 shows a dynamic RAM (random access memory) according to an embodiment of the present invention.
Although not particularly limited, the dynamic RAM shown in the same figure is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

The dynamic RAM according to the present embodiment is not particularly limited, but it has two memory mats MARY1 and MAR.
With Y2. Memory mats MARY1 and MAR
Although not particularly limited, Y2 is a folded bit line system, and complementary bit lines BL arranged in the vertical direction in FIG.
It includes word lines WL arranged in the horizontal direction, and memory cells MC arranged in a lattice at intersections of these complementary bit lines and word lines. In the figure, each complementary bit line is shown as one signal line, but in reality it is a pair of complementary signal lines. Although not particularly limited, the memory cell MC is a so-called one-element type dynamic memory cell, and is configured by a series circuit of an information storage capacitor (hereinafter also simply referred to as storage capacitor) and an address selection MOS transistor. .. Memory mat Mary1,
The data input / output terminals of the address selection MOS transistors of the memory cells MC arranged in the same column of MARY2 are alternately coupled to the corresponding non-inverted signal lines or inverted signal lines of the complementary bit lines with a predetermined regularity. . The gates of the address selecting MOS transistors of the memory cells MC arranged in the same row of the memory mats MARY1 and MARY2 are commonly coupled to the corresponding word lines. The information storage capacitor of the memory cell MC is connected to a cell plate to which a predetermined cell plate potential is applied.

Each memory mat MARY1, MARY
2 is provided with X decoders XDEC1 and XDEC2,
A predetermined word line is driven to a selection level by a selection signal output from each of them, thereby selecting a memory cell in word line units. The X decoders XDEC1 and XDEC2 have X address signals X0 to X8 and a NAND gate NAND.
The outputs of 1 and NAND2 are received and decoded to generate a word line selection signal.

A precharge circuit (not shown) is provided for each of the complementary bit lines BL, and precharges the complementary bit lines to a level of about half the power supply voltage during the chip non-selection period. In addition, each memory mat MARY1, M
In ARY2, the complementary bit line BL is the sense amplifier SA.
1 and SA2 and are activated all at once when the minute read signal from the memory cell MC connected to the word line WL selected in the chip selected state is established on the corresponding complementary bit line BL. As a result, the sense amplifiers SA1 and SA2, which are made operable, operate on the word line W
The minute read signals output from the memory cells MC selected via L to the complementary bit lines BL are each amplified to be a high-level or low-level binary read signal. When the dynamic RAM is set to the read mode or the refresh mode, these binary read signals are rewritten in the corresponding memory cells to refresh the stored data. In other words, the predetermined word line WL is selectively set to the high-level selected state, and the sense amplifier SA
The refresh operation of the dynamic memory cell MC is realized by putting 1 and SA2 into the operating state all at once.

Each memory mat MARY1, MARY
The complementary bit line BL included in 2 is the column selection circuit CSE.
Complementary common data lines CD1. C
Connected to D2. Complementary common data line CD in the figure
Although each of 1 and CD2 is shown as one signal line, it is actually a pair of complementary signal lines. Column selection circuit C
SEL1 and CSEL2 include switch MOS transistors (not shown) for selectively turning on the complementary bit line BL to the complementary common data lines CD1 and CD2, which are Y decoder YDE for decoding the Y address signals Y0 to Y7.
The switch is controlled by the output selection signal of C.

Complementary common data lines CD1 and CD2 are connected to a main amplifier MA via transfer gates G1 and G2, and this main amplifier MA is coupled to a data input / output buffer BUF. In the data read mode, the main amplifier MA further amplifies a binary read signal output from the memory cell selected by the word line via the complementary bit line and the complementary common data line, and transmits it to the data input / output buffer BUF. In the data write mode, the complementary common data line CD is driven according to the write data supplied from the data input / output buffer BUF.

In FIG. 1, RFC is a dynamic RA.
In M, it is an operation mode designating means for designating one refresh cycle from a plurality of refresh cycles, and a word line should be selected during a unit memory cycle according to the operation mode designated by the operation mode designating means. Control logic R that makes the number of memory mats different
Have FL.

As the operation mode designating means RFC,
A control register that holds rewritable operation mode specification information supplied from the outside, a dedicated external terminal for operation mode specification, a laser blow fuse or an electric fuse whose operation mode is fixedly set at a predetermined stage of the manufacturing process. Such a non-volatile storage means, or a bonding option for fixedly determining the operation mode at a predetermined stage of the manufacturing process, or one means selected from wiring means such as an aluminum master slice may be adopted. it can. In either case, the refresh mode control signal HRB is set to the high level or the low level according to the designation.

The control logic RFL includes a NAND gate NAND1 having two inputs of the refresh mode control signal HRB and an inverted signal of the address bit X9, and the refresh mode control signal HRB and the address bit X9.
And a normal rotation signal of 2 are input to the NAND gate NAND2. Address bit X9 is regarded as a memory mat selection bit, and its high level indicates selection of memory mat MARY1 and its low level indicates selection of memory mat MARY2. In response to this, the X decoders XDEC1 and XDEC2 are activated when the inputs of the terminals receiving the outputs of the NAND gates NAND1 and NAND2 are at the high level, and the addresses X0 to X0.
The word line designated by the value of X8 is driven to the selection level. When the refresh mode control signal HRB is at the low level, the outputs of the NAND gates NAND1 and NAND2 are set to the high level regardless of the logical value of X9, so that both memory mats MAR in the chip selected state.
A word line is selected by Y1 and MARY2. When the refresh mode control signal HRB is at the high level, one of the outputs of the NAND gates NAND1 and NAND2 is set to the high level according to the logical value of X9, so that the memory mats MARY1 and MAY are selected in the chip selected state.
A word line is selected by only one of RY2.

The transfer gates G1 and G2 are
Are NAND gates NAND2 and NAND4 which output complementary logical values according to the logical value of the address bit Y8 when the refresh mode control signal HRB is at low level.
When the refresh mode control signal HRB is at a high level, the NAND gates NAND2 and NAND2 are controlled regardless of the logical value of the address bit Y8.
It is controlled to be in the ON state by the high level signals output from both sides. This control logic is designed so that the data of the memory cells selected in parallel by both memory mats MARY1 and MARY2 do not collide when the refresh mode control signal HRB is at the low level. Such consideration can also be made in other circuit parts. For example, when the Y decoder is individualized for each memory mat, data collision can be avoided by using the address bit Y8 as an activation control signal for the Y decoder.

In this embodiment, the low level of the refresh mode control signal HRB designates the operation mode of 512 refresh cycles, and the high level of the refresh mode control signal HRB designates the operation mode of 1024 refresh cycles. The 512 refresh cycle means that the stored information of all the memory cells can be prevented from being destroyed by executing the refresh cycle every 512 memory cycles.
The 024 refresh cycle means that the stored information in all the memory cells can be prevented from being destroyed by executing the refresh cycle every 1024 memory cycles. Which refresh cycle should be adopted in the dynamic RAM of this embodiment is
It is determined at least by the relationship with the stored charge retention capacity of the memory cell and is revealed by a test such as a wafer probe test. For example, as shown in FIG.
In the wafer probe test, if the accumulated charge effective holding time Tref of the memory cell is K (acceleration coefficient) × 16 ms or more, it is determined that refreshing in 1024 refresh cycles is sufficient, and the accumulated charge effective holding time T
5 if ref is less than that and K × 8 ms or more
It is determined that it is sufficient to perform refresh in 12 refresh cycles, and if it is less than that, it is determined to be defective. This determination result is reflected in the designation by the operation mode designating means RFC, and the refresh mode control signal HRB
The level of is determined.

In the dynamic RAM of the present embodiment, when the operation mode of 512 refresh cycles is designated by the low level of the refresh mode control signal HRB, the address bit X9 is used but X8 is not used. Or even if it is used, it has no practical meaning. On the other hand, when the operation mode of 1024 refresh cycles is designated by the high level of the refresh mode control signal HRB, the address bit X8
Instead of being used, X9 is not used. Or even if you use it, it has no practical meaning.

Operation mode designating means RFC 102
The dynamic RAM in which the 4 refresh cycle mode is specified uses the input terminals of addresses X0 to X9 and Y0 to Y7, and the refresh operation mode is specified from the outside every 1024 memory cycles, and is specified by the addresses X0 to X9 at that time. The selected one word line is selected and refresh is performed. The dynamic RAM in which the 512 refresh cycle mode is designated by the operation mode designation means RFC has addresses X0 to X8 and Y0 to Y8.
The refresh operation mode is specified from the outside every 1024 memory cycles, and a total of two word lines specified by the addresses X0 to X8 at that time in the memory mats MARY1 and MARY2 are arranged in parallel. It is selected and refreshed. This 512
Externally, the refresh operation mode is specified every 1024 memory cycles in the dynamic RAM in which the refresh cycle mode is specified, but the memory cells coupled to two word lines are simultaneously refreshed in the single refresh operation mode. Therefore, it is possible to obtain substantially the same result as refreshing the memory cell coupled to one word line internally every 512 memory cycles, and the charge storage capability of the memory cell is lower than the specified value. Even if it is one, it is guaranteed that the stored charge information of the memory cell is prevented from being destroyed. That is, when the dynamic RAM in which the 1024 refresh cycle mode is specified performs the refresh operation every 1024 memory cycles for a predetermined period to complete the refresh operation of all memory cells, the dynamic RAM in which the 512 refresh cycle mode is specified.
This is because F can perform the refresh operation for a predetermined period every 1024 memory cycles to perform the refresh operation for all the memory cells twice.

The refresh operation mode is not particularly limited, but by asserting a refresh signal to a dedicated mode terminal or a CBR refresh mode such as an address multiplex type dynamic RAM, that is, a row address strobe signal is applied. It can be specified by asserting the column address strobe signal before asserting.

According to the above embodiment, there are the following effects.

(1) In the dynamic RAM whose operation mode designating means RFC specifies the 1024 refresh cycle mode, the refresh operation mode is externally specified every 1024 memory cycles, and 1 specified by the addresses X0 to X9 at that time is specified. A word line of the book is selected and refresh is performed. Operation mode designating means RFC
In the dynamic RAM in which the 512 refresh cycle mode is designated by the refresh operation mode from the outside every 1024 memory cycles, a total of two memory mats MARY1 and MARY2 are designated by the addresses X0 to X8 at that time. Word lines are selected in parallel and refresh is performed. This 51
Externally, the refresh operation mode is specified every 1024 memory cycles in the dynamic RAM in which the two refresh cycle mode is specified, but the memory cells coupled to two word lines are simultaneously refreshed in the single refresh operation mode. Therefore, it is possible to obtain substantially the same result as refreshing the memory cell coupled to one word line every 512 memory cycles internally, and the charge storage capacity of the memory cell MC is higher than the specified value. Even for the inferior ones, it is possible to prevent the accumulated charge information of the memory cells from being destroyed even if the refresh operation is externally instructed every 1024 memory cycles.

(2) Rescue as a dynamic RAM having the same outer surface specifications as the dynamic RAM in the 1024 refresh cycle mode by designating the 512 refresh cycle mode even for the chip in which the charge storage capacity of the memory cell is less than the specified value. Therefore, the yield of the dynamic RAM can be improved.

(3) Operation mode designating means When the RFC is a means such as a register that can be set on the system, a fresh operation is performed every 1024 memory cycles on the system for a chip whose charge storage capacity is lower than a specified value. Can be freely selected from among a refresh control mode for instructing a fresh operation every 512 memory cycles, and a degree of freedom for system configuration such as system expansion can be increased. Become.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Yes.

For example, the above embodiment has been described with respect to the one having two memory mats, but the number can be two or more. Further, the number of memory mats or the number of word lines that are simultaneously selected at the time of refreshing is not limited to 1 and 2, and an appropriate combination can be used. Further, although the above embodiment has been described with respect to the case where the present invention is applied to the dynamic RAM, the present invention can be applied to a semiconductor memory device having a dynamic memory cell such as a nonvolatile static RAM.

In the above description, the case where the invention made by the present inventor is mainly applied to a dynamic RAM as a single memory LSI which is a field of application which is the background of the invention has been described. The present invention is not limited to this. It can also be widely applied to on-chip memories for microcomputers and the like. The present invention can be secretly applied to at least a condition having a dynamic memory cell that requires a refresh operation.

[0031]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, by changing the number of memory mats from which word lines should be selected in a unit memory cycle in accordance with a designated refresh cycle, the refresh cycle according to the accumulated charge holding capability of the dynamic memory cell, etc. Can be realized internally as a circuit, and as a result, there is an effect that a refresh cycle can be selected according to the accumulated charge holding ability of the dynamic memory cell without changing the external specifications.

Further, even if the accumulated charge holding capacity is lower than the specified value, no defect occurs and the yield of the semiconductor memory device having dynamic memory cells can be improved.

[Brief description of drawings]

FIG. 1 is a dynamic R according to an embodiment of the present invention.
It is a block diagram of AM.

FIG. 2 is a flowchart of an example of a chip-specific method used to internally set a refresh cycle.

[Explanation of symbols]

 MARY1, MARY2 memory mat MC dynamic type memory cell WL word line BL bit line SA1, SA2 sense amplifier XDEC1, XDEC2 X decoder CSEL1, CSEL2 column selection circuit YDEC Y decoder X0 to X9, Y0 to Y8 address signal RFC operation mode designating means RFL Control logic NAND1, NAND2 NAND gate HRB Refresh mode control signal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuhiko Saie 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hiratsuru ELS Engineering Co., Ltd. (72) Inventor Takashi Kikuchi Kodaira, Tokyo 5-20-1 Jitsumizu Honcho, Ichi, Japan, within Hitate Super L.S.I. Engineering Co., Ltd. (72) Inventor, Kotoko Sasaki 5-20-1, Kamimizuhoncho, Kodaira, Tokyo I Engineering Co., Ltd. (72) Inventor Susumu Hatano 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Inside the Musashi Factory, Hitachi Ltd.

Claims (2)

[Claims] 1. A semiconductor memory device having a plurality of memory mats each having a dynamic memory cell arranged in a matrix, and an operation mode designating means for designating one refresh cycle from a plurality of refresh cycles, and the operation mode designating means. Control logic for varying the number of memory mats from which a word line should be selected in a unit memory cycle according to an operation mode designated by the means;
A semiconductor memory device comprising: 2. The operation mode designating means holds a rewritable operation mode designating information supplied from the outside, a dedicated external terminal for designating the operation mode, and the operation mode is fixed at a predetermined stage of the manufacturing process. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is one of a nonvolatile memory means that is permanently set or a wiring means that fixedly determines an operation mode at a predetermined stage of a manufacturing process.