JPH0528107A - Data bus transfer circuit - Google Patents

Abstract

PURPOSE:To simplify the constitution of a data bus transfer circuit and also to eliminate a through current by using a bus driver circuit containing a tristate output circuit to transfer the data after precharging a data bus having a transistor. CONSTITUTION:A transfer circuit consists of a data bus 1, a precharge signal generating circuit 7, a precharge transistor 2 which precharges the bus 1 with a precharge signal SP of the output of the circuit 7, end a bus drive circuit 3 containing a tristate output circuit a which inputs a data signal SD and an enable signal SE and outputs the data to the bus 1. The circuit 7 inputs a clock SCL having the length equivalent to 2-dividing value of an instruction clock SC to a 2n-stage inverter 11 and also inputs the delay signal SDR outputted from the inverter 11 to an EXO gate 12 to obtain the signal SP. The number of stages of the inverter 11 is larger then the largest number of stages of a decoding circuit and used for precharge.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data bus transfer circuit, and more particularly to a bus transfer circuit for data transfer required by a microprocessor or a signal processor.

[0002]

2. Description of the Related Art A conventional data bus transfer circuit is shown in FIG.
The method is usually used. In the first method, as shown in FIG. 4, a static bus drive circuit 3 having a tri-state output circuit 8 and a gate output from the data bus 1 are composed of a NAND gate 5 or a NOR gate.

In the second method, as shown in FIG. 5, a precharge p-channel transistor 2 for precharging the data bus 1 and a dynamic charge for drawing the precharged charges of the data bus 1 to the ground G are provided. The N-channel bus drive circuit 6 and the gate for outputting from the data bus 1 to other circuits are composed of the inverter 4.

A signal processor will be described as an example of a system in which such a data bus transfer circuit is used. In the signal processor, data operation and data transfer using the data bus are performed by designating instructions. However, in the signal processor which does not have pipeline processing between the operation and the bus transfer, data operation and bus transfer are performed in one instruction. Need to do.

FIG. 6 shows the timing of the signal processor. One instruction is executed for one clock cycle. At this time, the data operation for the instruction is performed in the period a, and the bus data is transferred for the operation result data in the period b. The time for which the calculation result is determined is not constant because it depends on the pattern of the calculation.

As shown in FIG. 7, the operation of the conventional first bus transfer method in this system is as shown in FIG. 7, in which the control signal of the bus drive circuit 3 output to the data bus by the instruction and the control signal input to the transfer destination gate Decode
The decoded enable signal SE is input to the bus drive circuit 3. However, the data signal SD has not been completely determined as the data to be transferred when the enable is started because the calculation is not completed completely. The bus drive circuit 3 outputs an indeterminate value to the data bus 1 until the operation of the data is confirmed, and then outputs the confirmed data and transfers the data to the transfer destination.

On the other hand, the second conventional method operates as shown in FIG. This method requires a clock signal SCS shorter than the cycle of the clock signal SC described above. While decoding the data output source and the data transfer destination for the instruction data bus 1, the bus 1 is precharged to the VD side by the transistor to which the precharge signal SP is input. Since the data bus 1 operates dynamically, it is not possible to put the unfinished data SD on the data bus 1. Therefore, after the operation data is fixed, the enable signal SE is generated by the short clock signal SCS and the data bus 1 is discharged by the data SD.

[0008]

The conventional data bus transfer circuit has the following problems. That is, in the first conventional method, when it is attempted to transfer 8 bits of data to the bus having a width of 24 bits by LSB packing, the upper 16 bits excluding the data of 8 bits in the bus width of 24 bits are "0". It is desirable that the data be output.

However, in the conventional first method having a bus driver for 8 bits, the upper data is in a high impedance state, and the data value is uncertain. Therefore, it is necessary to add a bus driver for outputting "0" to the upper level. This is the same for all transfer resources having a bit length shorter than the internal bus width, and the addition of this bus driver increases hardware.

Further, since there is no bus driver which becomes active when there is no data to be transferred and no data is transferred, all the data buses are in a high impedance state. As a result, if the gate on the receiving side is an inverter, an intermediate potential will be applied to the gate input, and a through current will flow.

On the other hand, in the second conventional method, a clock for generating the precharge signal and the enable signal of the data bus is required, but this clock is a clock having a cycle shorter than the instruction cycle and a signal operating at high speed. It is difficult to supply with a processor.

Further, since it is not possible to enable the data until the operation is completed and put it on the bus, it is necessary to wait for the operation confirmation time before enabling it, and it is necessary to secure it in the clock cycle. It is possible that the transfer time cannot be secured sufficiently.

[0013]

A data bus transfer circuit of the present invention includes a data bus having a plurality of signal lines, and a precharge P-channel transistor for precharging the data bus by inputting a precharge signal to its gate. And a bus drive circuit for inputting data and an enable signal and transmitting the data to the data bus, a precharge signal generating circuit for generating the precharge signal is provided at one input terminal with the precharge signal generating circuit. A bus transfer or a clock signal having a half cycle thereof is input, and the periodic signal is input to the other input terminal through a delay circuit having a delay time longer than the maximum delay time of a control signal decoding circuit that determines a transfer source and a transfer destination. The bus drive circuit has a logic gate for input, and the bus drive circuit includes the data signal and the enable signal. A plurality of gates is configured to have a tristate output circuit driven by a logic operation output.

[0014]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. The data bus transfer circuit inputs the data bus 1, the precharge signal generation circuit 7, the precharge transistor 2 for precharging the data bus 1 by the output precharge signal SP, the data signal SD and the enable signal SE. A bus drive circuit 3 having a tri-state output circuit 8 for outputting data to the data bus 1.

The bus drive circuit 3 transfers indeterminate data because the operation data has not been determined immediately after it is enabled, but when the operation result data is subsequently determined, the correct data is transferred from that point.

Further, the precharge signal generation circuit 7 has a long clock S for dividing the instruction clock SC by two.
CL is input to the 2n-stage inverter 11 and the long clock S
Delay signal SDR output from CL and 2n stage inverter
Are input to the exclusive OR gate 12 to obtain the precharge signal SP. The number of stages of the inverter 11 is set to be larger than the maximum number of stages of a decoding circuit that decodes an instruction, and the precharge is applied during the decoding period.

FIG. 2 is a timing chart of each signal for explaining the operation of the block of FIG. The decoding time TD is completely applied to the precharge period by the even number of 2n-stage inverters 11 whose number is larger than the maximum number of gate stages of the decoder circuit that outputs the control signal of the transfer destination and the transfer destination of the data bus 1 from the instruction. Data transfer can be enabled as soon as it is finished.

According to this embodiment, when outputting lower 8-bit data to the bus 1 having a width of 24 bits, the upper 16 bits are output.
A fixed value is output without connecting a driver circuit to the bit. Even if no data is transferred, the bus 1 is precharged in each cycle, so the bus state is fixed at "H".

Therefore, even if the gate on the receiving side is an inverter, the bus does not have an intermediate value, so there is no risk of a through current flowing. Therefore, the number of gates on the data output side and the data input side can be reduced in terms of hardware.

Furthermore, since the precharge signal SP can be generated from the clock SC of the instruction cycle,
No higher frequency clock is required. Further, since the bus drive circuit 3 can be immediately enabled after the precharge is completed, even if the data is not confirmed at that time, the bus transfer time can be fully applied after the confirmation.

FIG. 3 is a block diagram of the second embodiment of the present invention. In the transfer circuit of this embodiment, the tri-state output circuit 3a is composed of a clocked inverter. Further, the precharge signal generation circuit 7a uses the clock S of the transfer cycle.
It is composed of a CT, a (2n + 1) stage inverter 13 and a NOR gate 14, and has the first block operation and effect.
It is similar to the embodiment of.

[0022]

As described above, according to the present invention, by precharging the data bus by the P-channel transistor, a data bus transfer circuit having a simple circuit and in which a through current does not flow can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a timing diagram of signals for explaining the operation of the block of FIG.

FIG. 3 is a block diagram of a second embodiment of the present invention.

FIG. 4 is a block diagram of a first example of a conventional data bus transfer circuit.

FIG. 5 is a block diagram of a first example of a conventional data bus transfer circuit.

FIG. 6 is a timing chart of each signal for explaining the operation of the signal processor.

FIG. 7 is a timing chart of each signal for explaining the operation of the block of FIG.

FIG. 8 is a timing chart of signals for explaining the operation of the block of FIG.

[Explanation of symbols]

 1 Data Bus 2 P-Channel Transistor for Precharge 3, 3a Bus Drive Circuit 4 Inverter 7, 7a Precharge Signal Generation Circuit 8 Tri-State Output Circuit 11 2n-stage Inverter 12 EXOR Gate 13 (2n + 1) -stage Inverter 14 NOR Gate SCL Long Clock SD data signal SE enable signal SC clock SDR delay signal

Claims (1)

Claim: What is claimed is: 1. A data bus having a plurality of signal lines, a precharge P-channel transistor for inputting a precharge signal to a gate to precharge the data bus, and a data and enable signal. In a data bus transfer circuit having a bus drive circuit for inputting and transmitting the data to the data bus, a precharge signal generation circuit for generating the precharge signal has a bus transfer or one half cycle thereof at one input end. Of the control signal decoding circuit that determines the transfer source and the transfer destination at the other input terminal, and has a logic gate that inputs the periodic signal through a delay circuit having a delay time longer than the maximum delay time of the control signal decoding circuit. In addition, the bus drive circuit outputs a plurality of gates by a logical operation output of the data signal and the enable signal. There the data bus transfer circuit, characterized in that it comprises a tri-state output circuit driven.