JPH05275690A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make a gate insulating film thin while restraining a tunnel current from flowing by a method wherein a gate insulating film of 2.5nm or less thickness and a gate electrode of 0.5mum or less are provided. CONSTITUTION:A leakage component ID1 to a gate electrode 4 by a tunnel effect, a channel component ID2, and a gate length L are made to bear relations to each other to satisfy formulas I and II. alpha1 and alpha2 are constant. The formula I shows that a leakage component ID1 is in proportion to a gate length L. The formula II indicates that a channel component ID2 increases with a decrease in gate length L to set a semiconductor device high in efficiency. The ratio of the leakage component ID1 to the channel component ID2 is represented by a formula III basing on the formulas I and II. alpha3 is a constant. Therefore, (ID1/ID2) decreases linearly with L, and a gate length L is so scaled as to satisfy a formula, L<=0.5mum. Even if L=10mum, ID increases till a gate insulating film reaches to 2.5nm in thickness TOX. When L=0.5mum, ID shows a tendency to increase even if TOX reaches to 1.5nm, so that TOX and L are set less than 2.5nm and 0.5mum respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which constitutes a MISFET.

[0002]

2. Description of the Related Art With the progress of integrated circuit technology for MISFETs, especially MOSFETs, the gate length of MOSFETs has fallen into the deep submicron region, and practical studies are being carried out in various places.

Heretofore, miniaturization scaling of this MOSFET has generally been carried out based on the concept of "proportional reduction" proposed by Denard in 1974. The proportional reduction scaling means that, when the size of a specific constituent element of the element is reduced, the other constituent elements of the element are also reduced at the same ratio to ensure the operating characteristics as a transistor.

However, since there are some parameters that are difficult to scale, such as built-in voltage and power supply voltage, which are determined by the state of the PN junction in the substrate, recently, the power supply voltage is K ^1/2 (K is a scaling factor).
The method of lowering with is proposed, and it is one of the guidelines for design.

Until now, it has been considered that the gate insulating film of MOSFET is a parameter that is difficult to scale,
It has been considered that the thickness of the gate insulating film is about 3 to 4 nm. This is because if the gate insulating film is made thinner than that value, the tunnel current between the drain and source and the gate electrode increases, and the transistor no longer operates.

By the way, the gate length is 0.1 to 0.2 μm.
In the following extremely fine transistor circuit, the power supply voltage also drops to about 1 to 1.5V. On the other hand, a high driving force is required to operate the device at high speed. for that purpose,
It is necessary to set the threshold voltage low.

[0007]

[Problems to be Solved by the Invention] However, as such,
Since the gate insulating film is not thinned to 4 nm or less and a transistor having a low threshold value is designed, the concentration of the channel cannot be sufficiently increased, and it is difficult to suppress the short channel effect. The situation is.

Further, the fact that the thinning of the gate insulating film has reached its limit has resulted in relying only on the reduction of the gate length for the improvement of the driving force, which is one of the obstacles to the improvement of the device speed. ..

The present invention has been made in view of the above circumstances, and an object of the present invention is to improve the driving force without relying only on the suppression of the channel concentration and the reduction of the gate length.
Therefore, it is to provide a MISFET that greatly contributes to the improvement of the resistance against the short channel effect and the improvement of the device speed.

[0010]

The semiconductor device of the present invention comprises:
A second conductivity type opposite to the first conductivity type formed on one side of the channel formation region in the surface portion of the semiconductor substrate of the first conductivity type.
A drain region of conductivity type, a source region of the second conductivity type formed on the other side of the channel formation region in the surface portion of the semiconductor substrate, and a gate insulating film having a thickness of 2 formed on the channel formation region. MISF having a gate electrode portion having a gate length of 0.5 μm or less and 0.5 nm or less
It is characterized in that it constitutes an ET.

[0011]

According to the present invention, since the gate insulating film thickness and the gate length are set to the above values together, the gate insulating film thickness can be reduced while suppressing the tunnel current. It is possible to improve the driving force in a state where the concentration is sufficiently secured and without relying only on the reduction of the gate length, and it is possible to miniaturize the device that satisfies the resistance to the short channel effect and the device speed.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a MISFE according to an embodiment of the present invention.
3 shows the structure of T.

The FET shown in FIG.
If it is an ISFET, 1 will be a p-type Si substrate. An element isolation insulating film 2 made of a SiO ₂ film or the like is formed on the substrate 1, and a portion on the substrate 1 surrounded by the element isolation insulating film 2 serves as an element region.
T is built in.

This MISFET has a gate insulating film 3 made of a SiO ₂ film or the like, a gate electrode 4 made of a polysilicon film, a source region 5 and a drain region 6. The gate insulating film 3 and the gate electrode 4 form a MOS type gate electrode portion, the gate insulating film 3 is formed on the central portion of the element region on the substrate 1, and the gate electrode 4 is formed by the gate insulating film 3
It is placed on top. The portion of the surface portion of the substrate 1 immediately below the gate electrode portion serves as a channel formation region, and the source region 5
Is formed on one side of the channel forming region as a n ⁺ region, the drain region 6 is formed on the other side of the channel region as n ⁺ regions.

In such a structure, a gate bias VG is applied to the electrode 4, a bias VD is applied to the drain region 6, and a bias VS is applied to the source region 7 to form an n-type inversion layer in the channel forming region. , Drain region 6
A current ID2 is caused to flow from the source to the source region 5 to obtain a predetermined transistor operation.

In the MISFET of the present invention, the thickness Tox of the gate insulating film 3 is 2.5 nm or less and the gate length L is 0.5 μm or less.

Here, ID1 indicates a leak component to the gate electrode 4 due to the tunnel effect except for the normal channel component ID2 out of the current flowing out from the drain region 6, and the leak component ID1 and the channel component ID2 and the gate length L. The following relationship is established between and.

First, ID1 = α1 · L (1) ID2 = α2 · (1 / L) (2) In this equation, α1 and α2 are proportional constants,
Equation (1) means that the leak component ID1 is proportional to the gate length L. The leakage component ID1 flows through the path shown by the solid line in the overlapping portion of the gate electrode 4 and the drain region 6, and because of the process problem, the end portion of the gate insulating film 3 is formed slightly thicker than the intermediate portion. , There are those that do not flow through the route indicated by the solid line but flow through the route indicated by the broken line. The current through this path increases as L increases. Therefore, the formula (1) is established. On the contrary, the expression (2) means that the shorter the gate length L is, the more the channel component ID2 increases, and the higher the efficiency becomes.

[0020] Then, by (1), (2), the ratio of leak component ID1 for channel component ID2 is expressed as (ID1 / ID2) = α3 · L 2 (3). α3 is a proportional constant and corresponds to (α1 / α2). The smaller (ID1 / ID2) shown in the equation (3) is more desirable, and the smaller (ID1 / ID2) is, the smaller the value is. The gate length L of L ≦ 0.5 μm is so scaled. The MISFET having the gate electrode portion as described above is formed, for example, by the manufacturing method described below.

Normally, in the MISFET, in a state where the element isolation insulating film 2 is formed on the substrate 1 to perform element isolation, a thin SiO ₂ film for cleaning the element region surface is provided in the area surrounded by the element isolation insulating film 2. Impurities adhering to the surface of the element region are removed by forming and removing this. After that, a SiO ₂ film or the like which becomes the material of the gate insulating film 3 is formed, and subsequently a polysilicon film which becomes the material of the gate electrode 4 is deposited,
The gate insulating film 3 and the gate electrode 4 are formed by patterning the SiO ₂ film and the like and the polysilicon film. Then, using the gate electrode portion as a mask, for example, A is formed on each side of the channel formation region of the substrate 1 immediately below the gate insulating film.
The n ⁺ source region 5 and the n ⁺ drain region 6 are formed by doping s ions in a high concentration and diffusing it by heat treatment.

Here, in particular, in the case of the present invention, a device is added to the step of forming the material film of the gate insulating film 3 and the patterning step for forming the gate insulating film 3 and the gate electrode 4.

That is, first, the material film of the gate insulating film 3 is formed so that Tox becomes 2.5 nm or less. The processing method adopted in the material film forming step of the gate insulating film 3 is as follows.

(A) 600 to 800 ° C., HCl 10
% Furnace oxidation in an atmosphere. As a result, a SiO ₂ film is formed as the material film.

(B) Lamp oxidation for 5 seconds in a dry atmosphere at 700 to 900 ° C. As a result, a SiO ₂ film is formed as the material film.

(C) Treatment of either (a) or (d): Nitriding treatment at 800 to 900 ° C. As a result, a oxynitride film is formed as the material film.

(D) Processing for forming a TaO ₅ film. In this case, the material film is a TaO ₅ film.

(E) Processing of (d) + (a), (b),
One of the processes in (c). As a result, the oxidized TaO
₅ film or oxynitride TaO ₅ film is formed as a material film.

Various other types are possible.

In the patterning process of the gate electrode portion, the patterning process is performed so as to satisfy the above numerical value, that is, L ≦ 0.5 μm.

As described above, the gate insulating film thickness and the gate length are combined to form the above values, so that it is possible to reduce the gate insulating film thickness while suppressing the tunnel current.
It is possible to improve the driving force in a state where a sufficient channel concentration is secured and without relying only on the reduction of the gate length. This has been confirmed by experiments, and its contents are shown below.

First, FIGS. 4 to 6 show static characteristics of MISFETs in which the thickness Tox of the gate insulating film 3 is changed while the gate length L is large (L = 10 μm). Among them, FIG. 4 shows VD-ID characteristics, FIG. 5 shows VD-IS characteristics,
FIG. 6 shows VD-IG characteristics, and in each figure, is V
A curve when G = 0V, a curve when VG = 0.5V, a curve when VG = 1.0V, a VG = 1.
The curve at 5V is the curve at VG = 2.0V. 4A, 5A, and 6A are n-MISFETs having a pure SiO ₂ film (“PO”) as a gate insulating film, FIG. 4B, and FIG. b), FIG.
(B) is an n-MISFET having a nitride film (“N”) as a gate insulating film, FIG. 4 (c), FIG. 5 (c), and FIG. 6.
(C) is an n-MISFET having a nitrided oxide film (“ON”) as a gate insulating film, and FIGS. 4D, 5D, and 6D are reoxidized and nitrided oxide films as a gate insulating film. ("O
NO ") is provided for each characteristic of the n-MISFET. The ratio (W / L) of the gate width W and the gate length L of these MISFETs is" 1 ", that is," 10 µm / 10 µm ", and is the same. In each of FIGS. 4 to 6, Tox is a minimum of 1.5 n
m, in the range of maximum 2.0 nm, (a) <(b) <(c) <
The relationship is (d).

First, the characteristics shown in FIGS. 4 to 6 (d) are ideal characteristics. That is, when VG = 0V, regardless of the value of VD, ID, IS, and IG = 0 μA, and there is no leak current in the gate electrode 4, the source region 5, and the drain region 6 (see FIGS. 4 to 6D). .. And V
In response to increasing G, IS and ID increase, and
Can be read as 0 μA regardless of VG, and the leak current ID1 shown in FIG. 1 is almost 0 μA, which shows that good transistor characteristics are obtained.

On the other hand, in contrast to this, FIGS.
Looking at the other characteristics shown in (a), it can be seen that the characteristics deteriorate as the gate insulating film thickness Tox becomes smaller. Figure 4-
6 (c) is not so great, but FIGS.
In the characteristic shown in (b), when VG = 1.0 V or more is applied, a current flows out from the gate electrode 4, and accordingly,
The characteristics of the currents I D and I S have deteriorated.
Looking at the curve of, the drain region 6 where the current should flow out
It can be seen that the smaller the VD is, the more the current flows.

Therefore, according to FIGS. 4 to 6, even if the gate length L is 10 μm, the gate insulating film thickness Tox is 2.0 μm.
However, when the gate length L remains large, the characteristics become worse as Tox becomes thinner.
It is well understood that a reduction in ox causes a plateau.

On the other hand, FIG. 2 shows the gate insulating film thickness Tox.
Is kept constant at 1.8 nm and the gate length L is changed to n-MIS.
The VD-ID static characteristics of the FET are measured. The gate insulating film of the sample is a Si nitride film (SiN;
"N").

The characteristics shown in FIG. 2A are the same as those shown in FIG. As shown in this figure, Tox = 1.8 μm
It can be seen that even if the thickness is reduced, the characteristics are improved by reducing L accordingly, and when L = 0.5 μm shown in FIG. 2C, good transistor characteristics are already obtained. ..

In FIG. 3, the gate insulating film thickness Tox is 1.
N-MISFET with constant 5 nm and different gate length L
VD-ID static characteristics of The gate insulating film of the sample is a pure oxide film (SiO ₂ film; “P
O ").

The characteristics shown in FIG. 3A are the same as those shown in FIG. As shown in this figure, Tox = 1.5 μm
Even if it becomes even thinner, if L is reduced to 1 μm,
It can be seen that the characteristics are improved.

FIG. 7 shows the relationship between the driving force and the gate insulating film thickness Tox. In FIG. 7A, L = 10 μm, and in FIG. 7B, L = 0.5 μm. ..

Even when L = 10 μm, the increase in ID (ID2) is seen up to about Tox = 2.5 nm. When L = 0.5 μm, the tendency of increase in ID (ID2) is seen even when reaching Tox = 1.5 nm.

Therefore, the gate insulating film thickness Tox is 2.5 nm.
In the case of scaling to the following, it can be seen that if the gate length L is also 0.5 μm or less, good transistor characteristics can be surely obtained.

As described above, by scaling the gate insulating film thickness Tox and the gate length L to a specific value, the tunnel current can be suppressed and the gate insulating film thickness can be reduced. As a result, it is possible to improve the driving force in a state where the channel concentration is sufficiently secured and without relying only on the reduction of the gate length, and it is possible to miniaturize the element that satisfies the resistance to the short channel effect and the element speed. It will be possible. Further, since an extremely thin film through which a tunnel current flows is used as the gate insulating film, the generated charge does not continue to be trapped, but is quickly detrapped, and the characteristic deterioration of the transistor is extremely small.

[0044]

As described above, according to the present invention, the gate insulating film thickness is 2.5 nm or less and the gate length is 0.5 μm.
By scaling the gate insulating film thickness and the gate length so as to have the following gate electrode portion, it is possible to reduce the gate insulating film thickness while suppressing the tunnel current. Secured in
In addition, the driving force can be improved without relying only on the reduction of the gate length, and the element can be miniaturized while satisfying the resistance against the short channel effect and the element speed improvement.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a MISFET according to an embodiment of the present invention.

FIG. 2 shows the MISF when the gate insulating film is kept constant at 1.8 nm and the gate length is set to 10 μm, 1 μm, and 0.5 μm.
The curve figure which shows the VD-ID static characteristic data of ET.

FIG. 3 shows VD − of a MISFET when the gate insulating film has a constant thickness of 1.5 nm and the gate length is 10 μm and 1 μm.
The curve figure which shows ID static characteristic data.

FIG. 4 is a MISFE when the gate length is fixed at 10 μm and the gate insulating film thickness is changed within the range of 1.5 to 2.0 nm.
The curve diagram which shows the VD-ID static characteristic data of T.

FIG. 5: MISFE when the gate length is fixed at 10 μm and the gate insulating film thickness is changed within the range of 1.5 to 2.0 nm.
The curve figure which shows the VD-IS static characteristic data of T.

FIG. 6 is a MISFE when the gate length is fixed at 10 μm and the gate insulating film thickness is changed within the range of 1.5 to 2.0 nm.
The curve diagram which shows the VD-IG static characteristic data of T.

FIG. 7 is a curve diagram showing the relationship between the driving force of the MISFET and the gate insulating film thickness Tox.

[Explanation of symbols]

 1 Si substrate 2 element isolation insulating film 3 gate insulating film 4 gate electrode 5 source region 6 drain region L gate length Tox gate insulating film thickness

Claims (1)

[Claims] 1. A drain region of a second conductivity type opposite to the first conductivity type, which is formed on one side of a channel formation region in a surface part of a semiconductor substrate of the first conductivity type, and a drain region of the semiconductor substrate surface part. A source region of the second conductivity type formed on the other side of the channel forming region, and a gate insulating film of 2.5 nm or less and a gate length of 0.5 μm or less, which is formed on the channel forming region. A semiconductor device forming a MISFET including a gate electrode portion.