JPH0527199B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a read-only memory circuit in which information can be electrically written, that is, a programmable read-only memory, and particularly relates to a test memory cell. It is something.

[Conventional technology]

Recent programmable read-only memories (hereinafter referred to as P-ROMs), especially bipolar P-ROMs, are highly flexible due to their flexibility in allowing the user to freely write the contents stored in each memory. It is widely used for information processing and control purposes. The memory cells of such P-ROM are:
As shown in Figure 2, the emitter of transistor Q ₁ with an open base is connected to the column line B, and the collector is connected to the row line W, and the diodes D ₁ and D ₂ are reversed as shown in the equivalent circuit shown in Figure 3. There are junction breakdown type memory cells connected in series in the direction. This junction breakdown type memory cell is written in as shown in FIG. 4 by making the non-conductive state before writing conductive by shorting diode _D2 shown in the equivalent circuit.

However, in P-ROMs for writing logic information into memory cells, the manufacturer ships them in a non-conductive state, that is, in an unwritten state, and the writing is performed only after reaching the user, so there is a problem with the writing yield. There is.

In the conventional junction destruction type memory cell, as shown in FIG. 5, each memory cell M ₁₁ , M ₁₂ , M ₂₁ , M ₂₂ has
Row selection circuits WD ₁ and WD ₂ are connected via matrices W ₁ and W ₂ . The row selection circuit WD is a circuit that selects a row line by setting the row line to a high or low level, and absorbs a write current during writing. In FIG. 5, memory cells M ₁₁ , M ₂₁ and M ₂₂ are shown in a written state. In FIG. 5, when writing to memory cell _M12 that has not been written yet, row selection circuit WD2 connected to row line _W2 is selected and turned on, and memory cell _M12 is selected and turned on. Write current _{( e.g.}
200 mA), a write current flows into the selected row select circuit WD ₂ through the memory cell M ₁₂ and destroys the diode D ₂ shown in FIG.

[Problem that the invention seeks to solve]

However, when writing this memory cell _M12 , the memory cell _M12 to be written from column line _B1
In addition to the current path of the selected row selection circuit D ₂ through the column line B ₁ to the selected row selection circuit WD ₂ through the written memory cells M ₁₁ , M ₂₁ , M ₂₂ . It is clear that there is a current path. Reverse withstand voltage of memory cell _M21 in this current path (withstand voltage when a voltage with a polarity different from the voltage applied to the memory cell to be written is applied)
is low, and the write current that should originally flow through the current path through the memory cell M ₁₂ to be written to is already written to the memory cell M ₁₁ ,
If the current flows through the current path through M ₂₁ and M ₂₂ , it will result in a writing failure, and since this writing failure occurs during writing by the user, a problem arises in that the writing yield is reduced.

[Means for solving problems]

Programmable read-only of the present invention
The memory is a matrix of N rows and M columns (N and M are positive integers) in which memory cells are composed of base-open transistors, and the emitters of these base-open transistors are connected to column lines and the collectors are connected to row lines. In a programmable read-only memory including a memory cell array arranged in the form of a memory cell array, a test device provided for at least one of the N rows of row lines and M columns of column lines and having the same configuration as the memory cells. The memory cell is in a written state and has a configuration in which the emitter of the base-open transistor of this test memory cell is connected to the row line and the collector is connected to the column line.

[Effect]

The present invention, as explained using FIG.
Memory cells M ₁₁ , M ₂₁ , written from B ₁
It is only necessary to test whether a current path occurs through _M22 , and for this purpose, when writing the memory cell _M12 , the maximum voltage of the column line _B1 at the instant of destroying the diode _D2 as shown in FIG. Let V ₁ be the voltage, and let the forward voltage of the already written memory cells M ₁₁ and M ₂₂ be
V ₂ and the on level V ₃ of the row select circuit WD ₂ that is selected and turned on, the reverse breakdown voltage of the memory cell M ₂₁ is (V ₁ −2V ₂ −V ₃ ) or more, that is, Substantially the memory cell in FIG.
Focusing on the fact that it is sufficient to test that the reverse breakdown voltage of _M21 is at least (V ₁ −2V ₂ −V ₃ ), as mentioned above, in addition to the regular memory cell matrix, all The memory cell in the state is connected in the row direction and/or as a test memory cell with the emitter connected to the row line and the collector connected to the column line, which is the opposite of the normal connection (i.e. emitter to column line and collector to the row line). They are arranged in the column direction.

P-ROM cannot be tested by directly writing data into regular cells, and generally the reverse withstand voltage (different from the voltage during normal operation) of the circuit elements incorporated in the circuit is It is extremely difficult to confirm the withstand voltage (when a polar voltage is applied).

However, when multiple cells with the same configuration are used under the same conditions,
When formed simultaneously using the same method, the properties of these cells fall within typical ranges.

Therefore, in the present invention, the reverse withstand voltage of a regular cell is indirectly tested by testing the reverse withstand voltage of a test cell that is formed simultaneously with the same configuration, the same conditions, and the same method as the regular cell. It is designed to guarantee that

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention. In FIG. 1, memory cells M ₃₃ , M ₃₄ , M ₄₃ , which are in a normal unwritten state that have not yet been written to and are written to for the first time by the user.
_M44 connects _the row selection circuit _{WD3 ,}
Test memory cells M ₃₅ and M ₄₅ connected to WD ₄ and all written according to the present invention in the row direction and M ₅₃ and M ₅₄ in the column direction are connected to regular memory cells.
The connection of the cells, that is, the emitters are connected to the column lines and the collectors are connected to the row lines.The emitters are connected to _the row lines, and the _collectors are connected to _the column lines. ₄ to the row selection circuits WD ₃ and WD ₄ , and the test memory cells M ₃₅ and M ₄₅ are connected to the row line W ₅
It shows that it is connected to the row selection circuit _WD5 through.

In this embodiment, the row selection circuit WD ₅ connected to the row line W ₅ is turned on, and the reverse breakdown voltage of the test memory cell M ₃₅ or M ₄₅ is determined by the column line B ₃ or B ₄ as described above ( V ₁ −2V ₂ −V ₃ ) or more, and then the row selection circuit connected to the row line W ₃
Turn on WD ₃ , turn on the reverse breakdown voltage of test memory cell M ₅₃ from column line B ₅ and turn on the row selection circuit WD ₄ connected to row line W ₄ , and select memory cell for test from column line B ₅ . The reverse breakdown voltage of _M54 is V ₁ −2V ₂ −
Test whether there are V ₃ or more, memory cells
The reverse withstand voltage of M ₃₃ , M ₃₄ , M ₄₃ , and M ₄₄ can be indirectly tested.

In addition, in the above embodiment, the test memory
We discussed the case where cells are provided in both rows and columns, but
Depending on the case, even if this is provided only in one of the rows or columns, a certain effect can be obtained.

〔Effect of the invention〕

As explained above, according to the present invention, base open transistors with emitters connected to columns and collectors connected to row lines are used as memory cells,
A programmable read-only memory has an array arranged in a matrix of M rows and N columns (M and N are positive integers), and is a regular memory.
The emitter of the cell is connected to the column line, and the collector is connected to the row line, and the collector is connected to the column line.The emitter of the cell is connected to the row line, and the collector is connected to the column line, and the fully written transistor is used as a test memory cell and connected in the row direction and/or column. By testing the reverse breakdown voltage of this test memory cell, when writing to a desired memory cell, it is possible to detect memory that has already been written to the same column line as the desired memory cell.・From the cell, from the opposite direction of the already written memory cell on the same row line as this memory cell being written to,
Furthermore, a write current flows through the memory cell that has already been written between the same column line as the memory cell being written and the row line of the desired memory cell, and the desired memory cell is written. This makes it possible for manufacturers to indirectly test the issue of whether or not write errors occur at the shipping stage before handing over to users, making it possible to provide P-ROMs with a high write yield, is large.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the main part of an embodiment of the present invention, FIG. 2 is a circuit diagram showing the configuration of a memory cell,
FIG. 3 is an equivalent circuit diagram thereof, FIG. 4 is an equivalent circuit diagram after memory cell writing is performed, and FIG. 5 is a circuit diagram showing the main part of a conventional example. _B3 to _B5 ...column lines, _W3 to _W5 ...row lines, _M33 ,
M ₃₄ , M ₄₃ , M ₄₄ ...Memory cell, M ₃₅ , M ₄₅ ,
_M53 , _M54 ...Test memory cells, _W3 to _W5 ...
Row selection circuit.

Claims (1)

[Claims] 1. Memory cells are configured with base-open transistors, and the emitters of these base-open transistors are connected to column lines, and the collectors are connected to row lines, forming a matrix of N rows and M columns (N and M are positive integers). In a programmable read-only memory including a memory cell array arranged in a memory cell array, a test memory provided for at least one of the N rows of row lines and the M columns of column lines and having the same configuration as the memory cells. - A programmable read-only memory characterized in that the cell is in a written state and the emitter of the base-open transistor of this test memory cell is connected to the row line and the collector is connected to the column line.