JPH05268251A - Packet switching system - Google Patents

Abstract

PURPOSE:To provide a constitution system for a highly-efficient large-capacity exchange realizing a low cell losing rate, a low call loss probability and a small delay time characteristic in a communication network, especially that using ATM. CONSTITUTION:In an ATM three-stage switch, a first stage unit switch 101 is provided with a common buffer 105 and a control circuit 106 controlling the distribution of cells to a second stage unit switch, and a third stage switch 103 is provided with an order control circuit 108 correcting cell order inversion. Consequently, a load can equally be distributed to the second stage unit switch so that a cell loss rate at the second stage unit switch can be lowered. Besides, even in the case of the order inversion of the cells generated by the difference of routes inside the switch at respective cells, the quantity of inversion is reduced so that a buffer quantity needed for order control can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet switching system, and more particularly to an asynchronous transfer mode (A
TM: Asynchronous Transfer
The present invention relates to a packet switching system applied to a (Mode) communication network.

[0002]

2. Description of the Related Art In an ATM network, which is being studied by various research institutes as a next-generation powerful communication system, information is transmitted in a fixed-length packet (hereinafter referred to as "cell") format, and a transmission speed is set. Various types of media (voice, image, data, etc.) are used for information communication.

In the ATM network, since the cells are asynchronously transmitted and exchanged without time division, a large number of cells may be concentrated on the same output line of the ATM switch at the same time. A so that cells are not lost when concentrated
In the TM switch, a buffer memory is installed for each output line so that a part of the cell can be kept waiting there.
Since there is a limit to the buffer memory capacity that can be installed, it is difficult to completely avoid the loss of cells.

A large-capacity exchange system is generally constructed by connecting a plurality of unit switches in multiple stages. As a form of multi-stage connection, for example, n unit switches each having m × k inputs / outputs (m inputs and k outputs) are arranged in parallel to form a first-stage switch group, n
Xy unit switches are arranged in parallel to form a second-stage switch group, and y unit kxg unit switches are arranged in parallel to form a third-stage switch group. By alternately connecting the unit switch groups and the second and third unit switch groups, a mn × gy large-capacity switch is configured.

When the above multi-stage connection form is applied to an ATM switch, not only in the output line of the unit switch in the third stage, which is the output line of the switch, but also in the output line of each unit switch in the first and second stages. Cell loss will occur. Therefore, in order to realize the same cell loss rate as that of the exchange configured by one unit switch, the utilization rate of the input / output line must be set low. As a result, the throughput per line decreases and the call loss rate increases. On the contrary, in order to obtain the same call loss rate as that of the exchange configured by one unit switch, it is necessary to prepare a large number of switches, which increases the amount of hardware. The above-mentioned cell loss rate differs depending on the medium. For example, a higher-speed call and a call in which cell arrivals are bursty (collective) (for example, a video call, a high-speed data transfer call, etc.) have a higher loss rate. growing.

In order to solve the above-mentioned problem, in the Institute of Electronics, Information and Communication Engineers Technical Report SSE89-173 "Examination of control method in large-scale ATM switch", the input / output line of the first stage switch is irrelevant regardless of the cell destination. A method has been proposed in which the connection pattern is changed over time. In this method, for example, the output line connected to the input line 1 of the first-stage switch is changed in the order of line numbers 1, 2, 3, ..., M, 1, 2, ... In one clock cycle. .. "1 clock" here means the time required to transfer one cell, and for example, the line speed is 156 Mbp.
In the case of s, one clock is about 2.7 μsec.

According to the above method, even when cells collectively arrive at a certain input line of the first stage switch, these cells are distributed and output to the plurality of second stage switches. The probability that the cells collectively arrive at the specific unit switch in the second stage is reduced, and the loss rate of cells in the second stage switch can be reduced. Also, in each switch in the first stage, by avoiding simultaneous connection of multiple input lines to the same output line, the input / output connection pattern is determined to avoid cell collision in the switch in the first stage. However, it is possible to prevent the loss of cells associated therewith.

The second stage switch performs switching according to the destination of the input cell. In addition, the third-stage switch performs order control for correcting inversion of the cell order caused by a different path for each cell. In this sequence control, cells that have passed the preceding cell in the switch are temporarily stored in a buffer, and the cells are read out so that the cells are output in the order of arrival at the ATM switch.

[0009]

However, in the above conventional method, each switch in the first stage is provided with a function of distributing cells that have collectively arrived at the input line to a plurality of switches in the second stage. The problem of cell concentration from a plurality of switches in the first stage to a specific switch in the second stage is not considered.
For example, if cells to be output to a specific output line of the switch from the n unit switches of the first stage are concentrated on the specific unit switch of the second stage, the load on the plurality of switches of the second stage becomes unbalanced. It becomes uniform and makes a large difference in queue length. As a result, the cell loss rate increases in the second-stage switch, the difference between the delay time in one line and the delay time in another line increases, and the buffer required for sequence control in the third-stage switch increases. The problem that the amount becomes large occurs. On the contrary, in order to realize the low cell loss rate and the reduction of the buffer amount, the line utilization rate to be set must be lowered, which leads to an increase in the call loss rate.

It is an object of the present invention to provide an improved packet switching system having a low cell loss rate and a call loss rate. It is another object of the present invention to provide a large capacity packet switching system with improved delay characteristics.

[0011]

In order to solve the above problems, in the packet switching system of the present invention, cells arriving from a plurality of unit switches in the first stage are not concentrated in a specific unit switch in the second stage. In addition, each unit switch of the first stage distributes the output cell to the unit switch of the second stage. Specifically, for example, each unit switch in the first stage buffers cells input from a plurality of input lines and sequentially distributes the cells to a plurality of output lines in one clock cycle. Further, the output line that is the starting position of the cell distribution cycle is changed for each clock and for each unit switch of the first stage arranged in parallel.

[0012]

According to the packet switching system of the present invention, the n first-stage unit switches arranged in parallel buffer the input cells respectively, and then sequentially add the cells to the second-stage m switches. Since the cells are distributed, even when the cells collectively arrive at the specific unit switches on the first stage, these cells are not concentrated on the specific unit switches on the second stage. Also, 1
Since the start position of the cell distribution cycle is changed for each unit switch in the second stage, the concentration of cells in the specific unit switch in the second stage, the resulting cell loss, and the reversal of the arrival order can be reduced. It is possible to suppress an increase in the buffer memory capacity to be prepared for the third-stage unit switch.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings.

First Embodiment: (1) Structure of Cell Format FIG. 2 shows the structure of a fixed-length packet (hereinafter referred to as a cell) transmitted in an ATM network. The cell 201 flowing on the transmission path has a length of 53 bytes and is composed of a 5-byte header and a 48-byte information section. The header is V
CI (Virtual Channel ID) and VPI (Virtual P
ath ID) information, and routing control in the switch is performed based on this VCI and VPI information.

In the packet switching system of the present invention, each unit switch in the first stage has a header conversion function,
The additional header 203 is added to the input cell 201. The additional header includes a sequence number (hereinafter referred to as “S.No.”) and an identification number (“S”) of the first-stage unit switch.
And the identification number ("S
3 ”), an output line number (“ H ”), and a time stamp (“ TS ”).

In the present invention, in order to distribute the load to the unit switches in the second stage as evenly as possible, a plurality of cells having the same VCI are connected to the output line in the final stage through different routes. send. Since the order of cells in the switch may be reversed due to the difference in the route,
In each unit switch of the third stage, the cell order is corrected based on "S.No." and "TS" added to the input cell. Further, each of the unit switches in the first to third stages includes “S” and “S” included in the additional header of the input cell.
The routing operation is performed based on the contents of "3" and "H".

(2) Configuration and operation of switchboard FIG. 1 shows the configuration of an ATM switch composed of a plurality of three-stage unit switches according to the present invention. Each stage has a plurality of unit switches 101-1 to 101- arranged in parallel.
n, 102-1 to 102-m, 103-1 to 103-n
Consists of.

First-stage unit switch groups 101-1 to 10-10
1-n designates input cells from arbitrary input line groups 104-1 to 104-n as arbitrary output line groups 109-1 to 109
In order to connect to the predetermined output line of −n, the input cell 201 shown in FIG. 2 is subjected to header conversion to form the internal cell 202, and then the respective load is evenly distributed to the second-stage unit switch group. Distribute so that

Second-stage unit switch groups 102-1 to 10-10
2-m sends the cell to a specific third-stage switch accommodating the target output line based on the route information indicated by the additional header section 203 of the cell 202 input from the unit switch group of the first stage. To do. Third stage unit switch group 10
3-1 to 103-n perform order control of the cell 202 sent from the preceding stage switch group, remove the additional header section 203 and return to the cell format 201 on the transmission path, and then set each cell to the target. Send to the output line.

FIG. 3 shows the details of the common buffer section 105 and the control circuit section 106 which constitute the first-stage unit switch 101. The cells input in parallel from the m input lines 104 are multiplexed by the MUX 301 and headed for the header conversion circuit 302.

The header conversion circuit 302 includes a delay element 30.
6, register 307, additional header table 308, clock control unit 309, TS counter 310, empty cell determination unit 311, S.S. It consists of a No counter 312. MUX3
The cell information input from 01 is sent to the register 7 via the delay element 306. Also, of the same cell information,
The contents of the VCI and VPI fields are as follows: additional header table 308, TS counter 310, empty cell determination unit 3
11, S.S. It is supplied to the No counter 312.

From the additional header table 308, the above V
Route information (“S”, “S3”, based on CI information,
“H”) is read.

The clock controller 309 sends a signal to the TS counter 310 every clock. TS counter 31
0 stores the current time, and when a signal comes from the clock control unit 309, the current time is revised (counted up). Then, the input of the VPI and VCI information is used as a read signal, and the current time is read as the “TS” of the input cell.

The empty cell determination unit 311 uses the above VCI and VP.
It is determined whether the input cell is an empty cell based on the I information. A cell input signal is sent to the No counter 312 and the output control circuit 5. S. The No. counter 312 manages “S.No” for each number of the outgoing line 109 of the exchange, and when receiving the cell input signal, “SN.” Corresponding to the outgoing line is received based on the VCI information.
"o" is read out, and this is counted up and output, and the updated "S.No" is stored in the original address position.

The route information (“S”, “S3”, and “H”), “TS”, and “S.No” are transferred to the register 307, output from the multiplexer 301, and delayed. It is added to the header portion of the cell sent to the register 307 via the element 306.

In the register 307, the cell (202) with an additional header is input to the common buffer 303. The common buffer 303 temporarily stores a plurality of cells that arrive within one clock cycle, and outputs these cells to the DMUX 304. The output control circuit 305 stores and reads cells in the common buffer 303.
The write address (“W / A”) and the read address (“R / A”) given by

The output control circuit 305 uses the empty address FIF.
O313, selectors 314 and 317, a synchronization buffer 315 corresponding to each output line 109, and R /
It is composed of an A storage buffer 316, a line selection circuit 318, a clock control unit 319, and a read clock 320.
The cell input signal sent from the empty cell determination unit 311 is the line selection circuit 318 and the empty address FIFO3.
Sent to 13.

Upon reception of the cell input signal, the vacant address FIFO 313 reads "W / A", and the common buffer 3
Send to 03. The "W / A" is also sent as data to the synchronization buffer 315 via the selector 314 and stored according to the line number given by the line selection circuit 318.

The clock controller 319 generates an initial value update signal and a read signal at the start timing of each clock cycle and sends them to the line selection circuit 318 and the synchronization buffer 315, respectively. The line selection circuit 318 detects the line number. It comprises a counter 321 and an initial value table 322. The initial value table 322 generates an initial value in response to the initial value update signal, and the line No. Counter 321
Starts from the line number indicated by the initial value and sequentially outputs the line number for one cycle to the selector 314. These line numbers are output by the empty cell determination unit 311.
From the output control circuit 305 in synchronization with the cell input signal.

The synchronization buffer 315 is for absorbing the shift caused by the multiplexing, and when receiving the read signal from the clock controller 319, the m buffers simultaneously read the information stored in R buffers. / A storage buffer 316.

The read clock 320 sends a read signal to the selector 317 and the DMUX 304 every clock. Upon receiving the signal, the selector 317 sequentially reads “R / A” from the R / A storage buffer 316 and sends it to the common buffer 303. Upon receiving the signal, the DMUX 304 reads the cells from the common buffer 303 according to the "R / A" sent from the selector 317, and sequentially sends them to the output line.

The line No. described above. Supply of the initial value to the counter 321 and the line number. For example, as shown in FIG. 5, the output of the line number from the counter 321 has different initial values for each unit switch, and the initial values are cyclically shifted at each clock cycle. For example, focusing on the switch 101-1, the initial value of the first clock is "1" and the line numbers change to 1, 2, 3, 4, ... M,
At the 2nd clock, the line number changes sequentially with "2" as the initial value, ... At the mth clock, the initial value becomes "m", and cyclically changes so as to return to "1" again at the next clock. Let

The relationship between cell input and output according to the above method is shown in FIG. (A) is a cell output pattern when cells are present in all input lines, and (b) is a cell output pattern when any input line is an empty cell. According to this method, if any input line is an empty cell, it is temporarily stored in the common buffer. Therefore, the input cell can be sequentially output to the selected output line regardless of the input line. The output line, which is an empty cell in the clock, steadily changes for each clock, and the load on each output line, that is, each second-stage unit switch can be equalized.

In the next switch 101-2, the initial value of the first clock is "2", the second clock is "3", ...
... By setting the m-th clock to "1", the initial value is cyclically changed so that the selection of the output line deviates from that of the switch 101-1. Similarly, switch 10
Also in 1-3 to 101n, the initial value is cyclically changed in the form of sequentially shifting so that the selection of the line number deviates from other switches.

According to the above configuration, for example, in the cell arriving at the unit switch 101-1 in the clock cycle mk + 1, the head cell is the output line "1", the second cell is the output line "2", and the third cell is the third cell. Are sequentially output to the output lines “3”, .... In the cells arriving at the unit switch 101-2 during this period, the first cell is output to the output line "2", the second cell is output to the output line "3", the third cell is output to the output line "4", .... It

Since the size of each unit switch is m × m, the maximum number of cells input to one unit switch at the same clock is m. At any given time, each unit switch selects a different output line, and the selection start line in each clock cycle is different, so that cells are concentrated in a specific unit switch in the second stage. Instead, the load is evenly distributed.

Second-stage unit switch groups 102-1 to 10-10
2-m, when the cell 202 with the additional header is input,
According to "S3" of the additional header section 203, the cell is set to 3
Send to the step switch.

In this embodiment, in the above-mentioned first-stage unit switch group, the load is distributed to the second-stage unit switch group. However, the usage rate becomes high, or the cell is placed on the specific output line for some reason. When concentrated, a difference occurs in the queue length of cells in the second-stage unit switch, which causes the cell order inversion. However, the reversal of cell order is 3
It is corrected in the unit switch 103 of the stage.

As shown in FIG. 1, the third-stage unit switch includes a plurality of sequence control circuit groups 108-1-1 to 108-1-m provided for the output line 109 and a third-stage unit switch. And a switching circuit 107 connected to a group of input lines to the predetermined sequence control circuit according to the "H" of the input cell.
Input cells from the (stage) unit switch group 102 are distributed by the switching circuit 107 to a sequence control circuit corresponding to the target output line.

FIG. 6 shows the configuration of the sequence control circuit. The sequence control circuit 108 includes a memory 601 and a write control circuit 60.
2. The read control circuit 603. The cells distributed from the switching circuit 107 to the order control circuit 108 corresponding to each output line are stored in the memory 601 according to “W / A” given by the write control circuit 602.
Cell reading from the memory 601 is performed according to “R / A” given by the read control circuit 603.

(3) Effect FIG. 6 shows an example of the effect of this embodiment. The graph shows an average burst length of 10 in an ATM three-stage switch with a switch size of 64 × 64 (unit switch size 8 × 8).
This is a result of performing a simulation with an intra-burst cell interval of 2, a multiplexing number of 16 and a usage rate of 0.8.

According to this result, the probability that the cell order inversion will occur is almost the same in both the conventional method and the method of this patent.
However, comparing the magnitudes of the reversals, it can be seen that the conventional method is larger than the present method. The magnitude of this sequence inversion is equal to the buffer capacity required for the cell sequence control in the third-stage switch, and the cell loss rate = 10 in this method.
In order to satisfy ⁴ to ⁴ , a buffer capacity of n × 43 cells (/ line) may be prepared, but the conventional method requires a buffer capacity of n × 55 cells. That is, by using this method formula, the buffer amount can be reduced to about 3/4.

[0043]

As described above, according to the present invention, 1
In the second-stage switches, the cells are distributed to the second-stage switches in consideration of the distribution of cells in the other first-stage switches, so that the load can be evenly distributed to the respective second-stage switches. As a result, the difference between the queue lengths of the second-stage switches is reduced, which leads to a reduction in the amount of buffer prepared for the second-stage switches and a reduction in the cell loss rate in the second-stage switches.

Further, the size of the inversion also becomes small in the order inversion of the cells caused by the difference in the queue lengths. Therefore, it is possible to reduce the buffer amount required for the sequence control in the third stage switch. As a result of the simulation, the amount of buffer required for order control can be reduced to 3/4 compared with the conventional method. Therefore, the line utilization rate can be set high while realizing the low cell loss rate and the reduction of the buffer amount, and it can be regarded as a large capacity one-stage switch as a whole.

[Brief description of drawings]

FIG. 1 is a system block diagram of an ATM three-stage switch using the present invention.

FIG. 2 is a block diagram of a cell in ATM, and a block diagram of a cell after header conversion according to the present system and an additional header.

FIG. 3 is a system block diagram of a first-stage switch of an ATM three-stage switch using the present invention.

FIG. 4 is a diagram showing a cell input / output relationship in a first-stage switch of an ATM three-stage switch using the present invention.

FIG. 5 is a table showing how to distribute cells in the first-stage switch.

FIG. 6 is a block diagram of a sequence control circuit in a third-stage switch of an ATM three-stage switch using the present invention.

FIG. 7 is a graph showing the effect of the present invention.

[Explanation of symbols]

101 ... First stage unit switch, 102 ... Second stage unit switch, 103 ... Third stage unit switch, 105 ... Common buffer, 106 ... Control circuit, 108 ... Sequence control circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kaoru Aoki Kaoru Aoki 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock company Hitachi Information & Communication Division

Claims (2)

[Claims] 1. A plurality of unit switches each of which has a plurality of input lines and a plurality of output lines and which operates to selectively send a packet input from the input lines to any one of the output lines. The switches between the unit switches are configured, the link between the passing unit switches is changed for each packet without setting a logical channel between the unit switches in advance, and each unit switch in the first stage is input from a plurality of input lines. Sequentially output the packets to a plurality of output lines, and each unit switch of the second stage outputs each packet input from the input line to the output line determined by the header information, and each unit switch of the third stage. In the packet switching system in which the output line is determined by the header information of each packet input from the input line and the output order of the packets is controlled for each output line, Each unit switch at the first stage includes means for multiplexing the input packet, and a buffer for temporarily holding the packet output from the multiplexing means,
Packet output control means for sequentially outputting the packets read from the buffer to a plurality of output lines while shifting the start output line position of packet output in each clock cycle in a predetermined order. Switching system. 2. The plurality of unit switches in the first stage perform the selecting operation of the output line so that the packets are output to the second stage unit switches which are different from each other at each output timing of the packet. The packet switching system according to claim 1.