JPH05268239A - Upc circuit - Google Patents

Abstract

PURPOSE:To reduce the circuit scale of a UPC circuit by storing the starting time of a regulated cycle by each cell kind and updating the starting time when the difference between a present time and the stored starting time of each cell kind comes to over the regulated cycle. CONSTITUTION:A storage part 61 previously stores the starting time tb of the regulated cycle T by each piece of cell kind information up. On the other hand, a timer 15 counts the present time (t) and a time difference deciding part 30 decides whether the time difference D1 between the present time of the timer 15 (t) and the starting time tb of each cell kind of the first storage part 61 is over the regulated cycle T of the cell kind with the input of cell kind information up. Then, a time updating part 40 updates the starting time of the cell kind of the first storage part 61 with the affirmative decision of the time difference deciding part 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a UPC circuit, and more particularly to a UPC circuit which controls the flow rate of cells by counting the number x of cells arriving during a prescribed period T.
B-ISDN (Broadband-Integrated Services Digit
The so-called ATM (Asynchronous T) that asynchronously transfers cells that are a type of fixed-length packet
ransfer mode) technology is being developed. In the ATM network, control is performed to limit the cell flow rate based on the traffic declaration value of the subscriber (specified cycle T, specified cell number X).
This control is policing control or UPC (Usage Parameter
r Control) is an essential technology for smooth operation of ATM networks. However, this traffic declaration value (T,
This makes implementation of the UPC circuit difficult because X) is different for each subscriber.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram of a conventional UPC circuit, which shows a UPC circuit based on the TX method. In the figure, 1 is a cell type information branch unit (SB), 2 is a cell delay unit (SM), 3 is a cell control unit (SC), and 70 ₀ to 70.
_n is a policing determination unit, 71 is a target cell filter (S
F), 72 is a cell number counter (SCTR), 73 is a timer counter (TCTR), and 74 is a comparator (CM).
P), 75 are parameter memories (PM), and 80 is an OR gate circuit.

A cell arriving at IN on the highway is
The predetermined header information (cell type information
Report) vp is branched (copied) and temporarily set in the cell delay unit 2.
Memorized in. On the other hand, the polishing determination unit 70_i(I =
0, 1, ..., Or n) the branched cell type information vp
_iThe traffic of the arriving cell is measured based on the
T _iNumber of cells that arrived during_iIs the specified number of cells X_iBeyond
It is determined whether or not Then, the cell control unit 3
Rising determination unit 70_iAccording to the judgment result of
If not, pass through the cell of the cell delay unit 2 as it is.
In case of violation, discard the cell or Markin
Perform the processing.

FIG. 7 is an operation timing chart of the conventional UPC circuit. Focusing on the policing judgment unit 70 ₀ , the traffic declaration value is, for example, the prescribed period T ₀ (=
During 3), cells up to the prescribed number of cells X ₀ (= 2) are passed. As a result, the timer counter 73 continuously counts the specified cycle T ₀ (= 3). Specifically, the timer counter 73 is loaded with the complement T ₀ ′ of the specified cycle T ₀ by the clock signal CLK ₁ generated at each cell passage time Δt, and then incremented by the clock signal CLK ₁ . When the prescribed period T ₀ is counted, the carry signal C is generated and the complement T ₀ ′ is loaded again. The timer counter 73 repeats this operation.

On the other hand, the cell number counter 72 has a specified cycle T _0.
The number of cells x ₀ arriving during is counted, and in the first cycle, x ₀ = 2 due to arrival of cells i ₁ and i ₂ . When cells i ₃ arrive further in succession, x ₀ = 3, and the comparator 74 determines that x ₀ > X ₀ , so the cells i ₃ are discarded. In the second cycle, cell i ₄ ,
i ₅ arrives and they are not discarded because they meet the declared traffic value. No cells have arrived in the following third and fourth cycles. In the fifth cycle, cells i ₆ and i ₇ arrive, and in the following sixth cycle, cells i ₈ and i ₇ ,
i ₉ has arrived. Since these also meet the traffic declaration values, they are not discarded.

However, such a traffic declaration value (T, X) is different for each subscriber. That is, the vp ₀ is T ₀ = 3, for vp ₁ is T ₁ = 7, also for vp _n is as T _n = 2. For this,
Conventionally, the policing judgment unit 70 ₀ to have a timer counter 73, a cell number counter 72, etc. for each cell type information vp.
Since 70 _n is provided, there is a drawback that the scale of the UPC circuit becomes large. The same can be said for the specified cell number X.

In the above example, the specified period T₀(= 3)
Specified number of cells between X₀Pass cells up to (= 2)
Despite the intent, the four burst sessions that arrived at some point
Ru i ₆~ I₉Has passed through. this
Is not reasonable for its original purpose of controlling policing.
Yes.

[0008]

As described above, the conventional U
In the PC circuit, the timer counter 7 is provided for each cell type information vp.
Policing judgment unit 7 having 3 and cell number counter 72, etc.
0 ₀ because it was provided to 70 _n, there is a disadvantage that a scale of UPC circuit increases. An object of the present invention is to provide a UPC circuit that controls policing of many types of cells with a simple configuration.

[0009]

The above problems can be solved by the structure shown in FIG. That is, the UPC circuit of the present invention controls the flow rate of cells by counting the number of cells x that arrive during the specified period T, and the timer 15 that counts the current time t and the start of the specified period T. The first storage unit 61 that stores the time t _b for each cell type information vp, and the current time t of the timer 15 and the start time t _b related to the cell type of the first storage unit 61 by the input of the cell type information vp And a time difference determination unit 30 that determines whether or not a time difference D _t between the time difference determination unit 30 and a time period D _t exceeds a specified period T related to the cell type, and the cell type of the first storage unit 61 is determined by an affirmative determination of the time difference determination unit 30. And a time update unit 40 that updates the start time t _{b according} to the above.

[0010]

In FIG. 1, 1 is a cell type information branching unit (S
B), 2 is a cell delay unit (SM), 3 is a cell control unit (S
C), 10 is a policing judgment unit, 13 is a cell type information generation unit, 15 is a timer, 21 is a comparator (CMP),
30 is a time difference determination unit, 40 is a time updating unit, 50 is a cell number updating unit, 60 is a memory, 61 is a first storage unit, and 63 is a second storage unit.

A cell arriving at IN on the highway is
The cell type information branching unit 1 branches (copies) predetermined header information (cell type information) vp, and temporarily stores it in the cell delay unit 2. On the other hand, in the policing judgment unit 10, the traffic of the arriving cell is measured based on the branched header information vp, and the traffic declaration value (T,
Based on X), it is determined whether or not the arrival cell is in violation. Then, according to the determination result of the policing determination unit 10, the cell control unit 3 passes the cell of the cell delay unit 2 as it is if the arriving cell is not a violation, and discards or marks the cell if it is a violation.

The operation of the policing judgment will be described in detail. The first storage unit 61 stores the start time t _{b of the} specified cycle T in advance.
Is stored for each cell type information vp. On the other hand, timer 1
5 counts the current time t, and the time difference determination unit 30 inputs the cell type information vp between the current time t of the timer 15 and the start time t _b of the cell type of the first storage unit 61. It is determined whether or not the time difference D _t exceeds the specified period T related to the cell type. Then, the time updating unit 40 determines the first storage unit 61 by the positive determination of the time difference determination unit 30.
The start time t _b related to the cell type of is updated.

Preferably, the time updating unit 40 sets the start time t _b of the first storage unit 61 to a time that is before the current time t and is closest to the current time t and is an integral multiple of the specified period T of the cell type. To update. Also preferably, the time updating unit 40
Updates the start time t _b of the first storage unit 61 to the current time t.

Further, preferably, there is provided a cell type information generating section 13 for generating arbitrary cell type information vp 'at a time other than the processing for the arrival cell of the main signal. Thereby, even if the cell of the main signal does not arrive for a long time, the pseudo cell type information vp ′ generated by the cell type information generating unit 13 is generated.
Thus, the time difference determination unit 30 and the time update unit 40 are energized, and the start time t _b of the first storage unit 61 is updated accordingly.

Preferably, the cell type information generating unit 13 is 1
Alternatively, a series of cell type information vp 'is generated intermittently. Further, preferably, the cell type information generating unit 13 generates the cell type information vp ′ in the empty cell time of the main signal. Also preferably, the second storage unit 63 that stores the number x of cells that have arrived during the specified period T for each cell type information vp, and the cell number update unit 50 that updates the number x of cells in the second storage unit 63. With and
When the time difference determination unit 30 makes an affirmative determination when the cell type information generation unit 13 generates the cell type information vp ′, the cell number update unit 50 determines the cell number x of the cell type in the second storage unit 63. To initialize.

[0016]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Note that the same reference numerals denote the same or corresponding parts throughout the drawings. FIG. 2 shows U of the first embodiment.
In the block diagram of the PC circuit, 1 is a cell type information branch unit (SB), 2 is a cell delay unit (SM), 3 is a cell control unit (SC), 10 is a policing judgment unit, and 11 is cell type information vp. Latch circuit (SL), 12 is an inverter circuit, 13 is a cell type information generating unit (SCTR), 14 is a selector, 15 is a timer, 16 is an OR gate circuit, 17,
18 is an AND gate circuit, 19 and 20 are inverter circuits, 21 is a comparator (CMP), 30 is a time difference determination unit, 31 and 32 are comparators (CMP), 33 is AN.
D gate circuit, 34 addition circuit, 35 subtraction circuit, 40
Is a time updating unit, 41 is a division circuit, 42 is a multiplication circuit, 43
Is an addition circuit, 44 is a subtraction circuit, 45 is an AND gate circuit, 50 is a cell number updating unit, 51 and 52 are selectors, 53
Is an adder circuit, 60 is a memory, and 61 is cell type information vp _i.
RAM (corresponding to the first storage unit in FIG. 1) that stores the start time t _ib of the specified cycle at a position addressed by (i = 0, 1, ..., Or n), and 62 stores the specified cycle T _i . RAM
Alternatively, ROM, 63 is a RAM (second storage unit) for storing the number of arriving cells, and 64 is a RAM for storing the prescribed number of cells X _i.
Alternatively, the ROMs 65 and 66 are AND gate circuits.

A cell arriving at IN on the highway is
In the cell type information branching unit 1, predetermined header information (VPI: Vi
rtual Path Identifier, VCI: Virtual Channel Id
entifier, CLP: Cell type information including Cell Loss Priority) vp is branched (copied) and temporarily stored in the cell delay unit 2. On the other hand, in the policing judgment unit 10, the traffic of the arriving cell is measured based on the branched header information vp, and the traffic declaration value (T,
Based on X), it is determined whether or not the arrival cell is in violation. Then, according to the determination result of the policing determination unit 10, the cell control unit 3 passes the cell of the cell delay unit 2 as it is if the arriving cell is not a violation, and discards or marks the cell if it is a violation.

The operation of the policing judgment will be described in detail. For example, the timer 15 is incremented by the clock signal CLK ₁ generated at each cell passage time Δt, and the current time t is cyclically counted at a cycle of T _max. There is.
The time difference determination unit 30 is energized by the generation of the cell type information vp, and the time difference D _ti between the current time t of the timer 15 and the start time t _ib of the cell type i of the RAM 61 is related to the cell type. It is determined whether or not the specified period T _i is exceeded.

More specifically, the comparator 31
Compares the current time t with the start time t _ib, and if t
If ≧ t _ib , it means that the timer 15 has not overflowed, so the AND gate circuit 33 is not energized. As a result, the adder circuit 33 calculates t ′ = t + 0 to obtain the current time t ′, and the subtraction circuit 35 calculates D _ti = t′−t _ib to obtain the time difference D _ti . On the other hand, if t <t _ib , it means that the timer 15 has overflowed, so AN
Energize the D gate circuit 33. As a result, the adder circuit 3
3 calculates t ′ = t + T _max to obtain the current time t ′, and the subtraction circuit 35 calculates D _ti = t′−t _ib to obtain the time difference D _ti . Then, the comparator 32 compares the obtained time difference D _ti with the specified period T _{i of the} RAM 62, and if D _ti ≧ T _i , outputs a logic 1 level which is a positive determination.

When the time difference determining unit 30 makes an affirmative decision, the time updating unit 40 sets the start time t _ib of the RAM 61 to a time that is an integer multiple of the specified period T _i that is earlier than the current time t and is closest to the current time t. Update. More specifically, the division circuit 41 calculates Q = D _ti / T _i and outputs a quotient Q. Multiplier circuit 42 outputs the QT _i = Q × T _i an integer multiple of the addition time QT _i of calculating the go prescribed period T _i of. Then, the adder circuit 43 calculates t _ib = t _ib + QT _i to obtain a new start time t _ib . Note that the calculated start time t
_{When ib} exceeds the period T _{max of the} timer 15, the AND gate circuit 45 is activated by the detection of the overflow OVF, which causes the subtraction circuit 44 to t _ib = t.
_ib −T _max is calculated to obtain a new start time t _ib . Then, this is written in the RAM 61 by the write pulse WP, and the start time t _ib is updated.

By the way, in reality, the cell of the main signal may not arrive for a long time. RAM in such cases
If the start time t _{ib of} 61 is left without being updated, the period T _{max of the} timer 15 repeatedly turns during that time,
The accurate time difference D _ti cannot be obtained. Therefore, the cell type information generating unit 13 is provided to generate the pseudo cell type information vp 'regularly or irregularly, and thereby the time difference determining unit 30 and the time updating unit 40 are activated to set the start time t _b . Update accordingly.

The cell type information generator 13 of the embodiment increments an internal counter by a predetermined clock signal CLK ₂ and outputs pseudo cell type information vp 'which changes sequentially. This cell type information vp '
Is applied to each address input A of the RAMs 61 to 64 via the selector 14. However, when the cell type information vp of the main signal cell arriving at IN on the highway is latched in the latch circuit 11, the cell type information generation unit 13 is deactivated by the cell arrival signal SP to that effect. Further, the selector 14 is connected to the terminal b side, and the cell type information vp of the arriving cell is RA.
It is applied to each address input A of M61 to 64.

Preferably, the cell type information generating unit 13 is
One or a series of cell type information vp 'is generated in a vacant time within the one-cell transit time Δt. By doing so, the process for the arrival cell of the main signal and the process for the cell type information vp ′ can be performed in a time-division manner within one cell passage time Δt. In this case, such one or a series of cell type information vp 'is intermittently generated with a gap of several cells or more. By doing so, the time difference determination unit 30 does not need to frequently perform the time difference determination process based on the cell type information vp ′, and the burden is reduced.
Further, preferably, the cell type information generating unit 13 generates the cell type information vp ′ in the empty cell time of the main signal.

On the other hand, the cell number updating unit 50 determines the cell arrival signal.
Positive determination of SP or comparator 32 (D_ti≧ T_i)
Arriving cell, activated by being at a logic 1 level
Number x _iUpdate. To be more specific, first of all,
Timing of inspection by the type information generator 33 (SP =
0) and D_ti<T_iIn case of, the cell number updating unit 50 is attached.
And the write pulse to the RAM 63 is not generated.
Yes. That is, the number of cells x_iIs not updated. But the cell type
Timing of inspection by the separate information generator 33 (SP = 0)
Even D_ti≧ T_iIn case of, the cell number updating unit 50 is attached.
A write pulse to the RAM 63 is also generated. This place
, The selector 52 is connected to the terminal a side, and the number of cells
x_iThe update value of is forced to "0".

On the other hand, when the main signal cell arrives (SP =
In 1), the cell number updating unit 50 is activated and the RAM 6
A write pulse to 3 is also generated. In this state, if D _ti <
In the case of T _i , the selector 51 is connected to the terminal a side and the selector 52 is connected to the terminal b side. As a result, the adder circuit 53 performs the operation of x _i = x _i +1 and the number of cells x _{i of the} RAM 63 is incremented by one. If D _ti ≧ T _i ,
The selector 51 is connected to the terminal b side, and the selector 52 is connected to the terminal b side. As a result, the adder circuit 53 makes the x _i
= 0 + 1 is performed, and the number of cells x _{i in the} RAM 63 is forcibly set to “1”. In addition, when the comparator 21 discards the violating cell, the
The D gate circuit 66 is de-energized, and the number of cells in the RAM 63 x _i
Is not updated. The specific operation of the UPC circuit of the first embodiment will be described below.

FIG. 3 is an operation timing chart of the UPC circuit of the first embodiment. The timer 15 counts the current time t in a cycle of T _max = 14, and the specified cycle T _i = 3 and the specified number of cells X _i = 2. In the first cycle, x _i = 2 due to the arrival of cells i ₁ and i ₂ . Further cell i ₃
Arrives, x _i = 3 even though D _ti <T _i (2 <3) is satisfied. Therefore, the comparator 21
Discards the cell i ₃ by judging x _i = X _i (2 = 2). Since cell i ₃ has been discarded, x _i = 2 remains.

When cell i ₄ arrives continuously, D _ti ≧
The second cycle is entered by T _i (3 = 3). In this second cycle, the arrival of the cells i ₄ and i ₅ satisfies the traffic declaration value, so that neither of them is discarded. And
Since the cell i has not arrived at the boundary between the second and third cycles, the contents of t _ib and x _i are unchanged. The cell type information generation unit 13 generates the pseudo cell type information vp _i ′ at an appropriate timing of S _i in the third cycle. In this case, the cell arrival signal SP = 0 and D _ti ≧ T _i (5>
3), the start time t _ib is updated to a time (= 6) that is an integer multiple of the specified cycle T _i that is before the current time t and is closest to the current time t. Further, the number of arrival cells x _i is forcibly set to “0”. Since the main signal cell i has not arrived in the fourth cycle, the contents of t _ib and x _i change as they are.

In the fifth cycle, cells i ₆ and i ₇ have arrived, and in the sixth cycle, cells i ₈ and i ₉ have arrived.
All of these meet the traffic declaration values and are not discarded. Thus, according to the first embodiment, the same policing control as that of the conventional FIG. 7 is realized with a simple configuration.

FIG. 4 is a block diagram of the UPC circuit of the second embodiment. In the figure, 40 is a time updating unit and 46 is an AND gate circuit. The time update unit 40 updates the start time t _{ib of the} RAM 61 to the current time t. That is, A
The ND gate circuit 46 is energized by D _ti ≧ T _i , and R
The current time t is provided as the new start time t _ib of the AM 61. The specific operation of the UPC circuit of the second embodiment will be described below.

FIG. 5 is an operation timing chart of the UPC circuit of the second embodiment. As in the first embodiment, the specified period T
_i = 3, and defines the cell number X _i = 2. The operations of the first and second cycles are the same as in the first embodiment. Since the main signal cell i has not arrived at the end of the second cycle, the contents of t _ib and x _i remain unchanged.

The cell type information generating unit 13 generates the pseudo cell type information vp _i ′ at an appropriate timing of S _i after the end of the second cycle. In this case, since the cell arrival signal SP = 0 and D _ti ≧ T _i (5> 3), the start time t _ib is updated to the current time t (= 8). That is,
In the second embodiment, the third cycle T from the current time t (= 8)
_i will start. In this way, when the main signal cell i is interrupted, the start time t _ib is always an integer multiple of the specified period T _i before the current time t and closest to the current time t as in the first embodiment. It is not necessary to update (= 6). Rather, by updating the start time t _ib to the current time t (= 8) as in the second embodiment, the subsequent 4
It is possible to effectively control the policing of the one burst cell i _{6 to} i ₉ .

That is, cell i₆Arrives, the cell arrival
Issue SP = 1 and D_ti≧ T_i(5> 3), so open
Start time t_ibIs updated at the current time t (= 13). Immediately
The 4th cycle T_iStarts from the current time t (= 13)
To do. In the fourth cycle, cell i₆, I
₇By the arrival of x_i= 2. But cells in succession
i₈Arrives, D_ti<T_i(2 <3)
Nevertheless, x_i= 3, so the comparator
21 is x_i= X_iBy the determination of (2 = 2), the cell i₈
Discard. This cell i₈The original policing system
It is reasonable for your purposes. And cell i₈Abolished
I discarded it so x_i= 2 remains. Cell i ₉Has arrived
Time is D_ti≧ T_iThe fifth cycle is entered by (3 = 3).

Thus, according to the second embodiment, the rational policing control is realized by the simple structure as compared with the conventional case of FIG. Although the policing determination unit 10 is described as a hardware configuration in the above embodiment, this portion may be realized by software processing by the CPU.

[0034]

As described above, according to the present invention, in the UPC circuit that controls the flow rate of cells by counting the number x of cells arriving during the specified period T, the timer 15 that counts the current time t , The first storage unit 61 that stores the start time t _b of the specified cycle T for each cell type information vp, and the current time t of the timer 15 and the first time when the cell type information vp is input.
Of the time difference determination unit 30 and the time difference determination unit 30 that determines whether or not the time difference D _t between the start time t _b related to the cell type of the storage unit 61 exceeds the specified cycle T related to the cell type. Since the time update unit 40 that updates the start time t _b related to the cell type of the first storage unit 61 by the affirmative determination is provided, the circuit scale of the UPC circuit can be significantly reduced as compared with the related art.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a block diagram of a UPC circuit of the first embodiment.

FIG. 3 is an operation timing chart of the UPC circuit of the first embodiment.

FIG. 4 is a block diagram of a UPC circuit according to a second embodiment.

FIG. 5 is an operation timing chart of the UPC circuit of the second embodiment.

FIG. 6 is a block diagram of a conventional UPC circuit.

FIG. 7 is an operation timing chart of a conventional UPC circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Cell type information branching unit 2 Cell delay unit 3 Cell control unit 10 Policing determination unit 13 Cell type information generation unit 15 Timer 21 Comparator 30 Time difference determination unit 40 Time update unit 50 Cell number update unit 60 Memory 61 First storage unit 63 Second storage

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Michio Kusanagi 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited (72) Inventor Naoaki Yamanaka 1-6, Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Incorporated (72) Inventor Yoichi Sato 1-16 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation

Claims (7)

[Claims] 1. A UP for controlling the flow rate of cells by counting the number of cells (x) arriving during a prescribed period (T).
In the C circuit, the timer (15) that counts the current time (t) and the start time (t _b ) of the specified cycle (T) are used as the cell type information (v
A first storage unit (61) for storing every p), and the present time (t) of the timer (15) and the cell type of the first storage unit (61) by inputting the cell type information (vp). The time difference determination unit (30) that determines whether the time difference (D _t ) from the start time (t _b ) exceeds the specified period (T) related to the cell type, and the time difference determination unit (30). A time update unit (40) for updating the start time (t _b ) related to the cell type in the first storage unit (61) by a positive determination.
PC circuit. 2. The time updating unit (40) includes a first storage unit (6).
1) start time (t _b) Before the current time (t)
The specified frequency for the cell type closest to the current time (t)
Contract characterized by updating at an integral multiple of the period (T)
UPC circuit according to claim 1. 3. The time updating unit (40) includes a first storage unit (6).
1) start time (t _b) Can be updated to the current time (t).
The UPC circuit according to claim 1, wherein: 4. The cell type information generating unit (13) for generating arbitrary cell type information (vp ′) at a time other than the processing of the arrival cell of the main signal.
UPC circuit. 5. The UPC circuit according to claim 4, wherein the cell type information generating unit (13) intermittently generates one or a series of cell type information (vp ′). 6. The UPC circuit according to claim 4, wherein the cell type information generating unit (13) generates the cell type information (vp ′) in an empty cell time of the main signal. 7. A second storage unit (63) for storing, for each cell type information (vp), the number of cells (x) that have arrived during a specified period (T), and a second storage unit (63). A cell number updating unit (50) for updating the cell number (x), wherein the cell number updating unit (50) is a cell type information generating unit (13).
When the time difference determination unit (30) makes a positive determination when the cell type information (vp ′) is generated by the second storage unit (6).
The UPC circuit according to claim 4, wherein the number of cells (x) related to the cell type of 3) is initialized.