JPH05268094A - Ladder shape da converter - Google Patents
Ladder shape da converterInfo
- Publication number
- JPH05268094A JPH05268094A JP6492092A JP6492092A JPH05268094A JP H05268094 A JPH05268094 A JP H05268094A JP 6492092 A JP6492092 A JP 6492092A JP 6492092 A JP6492092 A JP 6492092A JP H05268094 A JPH05268094 A JP H05268094A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- formula
- heat generation
- output voltage
- equal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はラダー形ＤＡコンバータ
に関し、特に、自己発熱によるドリフトの低減に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ladder type DA converter, and more particularly to reduction of drift due to self-heating.
【０００２】[0002]
【従来の技術】ディジタル信号とアナログ信号のインタ
フェースとして、ＤＡコンバータが用いられている。2. Description of the Related Art A DA converter is used as an interface between digital signals and analog signals.
【０００３】ＤＡコンバータは各種の構成のものが実用
化されているが、一般には、並列ディジタル信号をアナ
ログ信号に変換するものが用いられている。これは、デ
ィジタル信号の各ビットに応じた重み付けを有する電流
を生成する抵抗回路網を設け、ディジタル信号の各ビッ
トに対応したスイッチを介して各ビットの重み付けを有
する電流を加算するように構成されたものである。Although various types of DA converters have been put into practical use, generally used are those that convert parallel digital signals into analog signals. It is configured to provide a resistance network for generating a current having a weight corresponding to each bit of a digital signal, and to add the current having a weight of each bit through a switch corresponding to each bit of the digital signal. It is a thing.
【０００４】図３はラダー抵抗回路網を用いたラダー形
ＤＡコンバータの一例を示す接続図である。図におい
て、ＴＲＥＦは基準電圧ＶＲＥＦの入力端子である。Ｔ
−１〜Ｔ−ＮはＮビットで構成されるディジタル信号の
各ビットＢＩＴ−１（ＭＳＢ）〜ＢＩＴ−Ｎ（ＬＳＢ）
の入力端子、ＴＯＵＴはアナログ信号ＶＯＵＴの出力端
子である。Ｓ−１〜Ｓ−Ｎは切換スイッチで、ディジタ
ル信号の各ビットに対応するように設けられている。抵
抗ＲＢ−１〜ＲＢ−（Ｎ−１）とＲＡ−（Ｎ＋１）は直
列に接続され、抵抗ＲＢ−１の一端は入力端子ＴＲＥＦ
に接続され、抵抗ＲＡ−（Ｎ＋１）の他端はアースに接
続されている。抵抗ＲＡ−１〜ＲＡ−Ｎの一端は直列接
続された各抵抗ＲＢ−１〜ＲＢ−（Ｎ−１），ＲＡ−
（Ｎ＋１）の接続点に接続され、他端は対応する切換ス
イッチＳ−１〜Ｓ−Ｎの可動接点ａに接続されている。
切換スイッチＳ−１〜Ｓ−Ｎの一方の固定接点ｂは演算
増幅器Ａ１の反転入力端子に共通に接続され、他方の固
定接点ｃはアースに共通に接続されている。演算増幅器
Ａ１の非反転入力端子はアースに接続されている。そし
て、演算増幅器Ａ１の出力端子と反転入力端子の間には
帰還抵抗Ｒｆが接続されている。ここで、抵抗ＲＡ−１
〜ＲＡ−（Ｎ＋１）の抵抗値は２０ｋΩに設定され、抵
抗ＲＢ−１〜ＲＢ−（Ｎ−１），Ｒｆの抵抗値は１０ｋ
Ωに設定されていて、Ｒ−２Ｒラダー抵抗回路網を構成
している。FIG. 3 is a connection diagram showing an example of a ladder type DA converter using a ladder resistance network. In the figure, T REF is an input terminal for the reference voltage V REF . T
-1 to TN are bits BIT-1 (MSB) to BIT-N (LSB) of a digital signal composed of N bits
, T OUT is an output terminal for the analog signal V OUT . S-1 to SN are changeover switches, which are provided so as to correspond to each bit of the digital signal. The resistors RB-1 to RB- (N-1) and RA- (N + 1) are connected in series, and one end of the resistor RB-1 has an input terminal T REF.
The other end of the resistor RA- (N + 1) is connected to the ground. One ends of the resistors RA-1 to RA-N are connected in series to the resistors RB-1 to RB- (N-1), RA-.
It is connected to the connection point of (N + 1), and the other end is connected to the movable contact a of the corresponding changeover switches S-1 to SN.
One fixed contact b of the changeover switches S-1 to S-N is commonly connected to the inverting input terminal of the operational amplifier A1, and the other fixed contact c is commonly connected to the ground. The non-inverting input terminal of the operational amplifier A1 is connected to the ground. A feedback resistor Rf is connected between the output terminal and the inverting input terminal of the operational amplifier A1. Here, the resistance RA-1
~ RA- (N + 1) has a resistance value of 20 kΩ, and resistors RB-1 to RB- (N-1) and Rf have a resistance value of 10 k.
Is set to Ω and constitutes an R-2R ladder resistor network.
【０００５】[0005]
【発明が解決しようとする課題】このような回路構成に
おいて、基準電圧ＶＲＥＦを一定とすると、Ｒｆ以外の
抵抗はすべて一定の負荷（発熱）で動作するが、帰還抵
抗Ｒｆは出力に依存して自己発熱する。In such a circuit configuration, when the reference voltage V REF is constant, all the resistors other than Rf operate with a constant load (heat generation), but the feedback resistor Rf depends on the output. Self-heats.
【０００６】ここで、帰還抵抗Ｒｆの絶対温度係数を１
００ｐｐｍ／℃として自己発熱の影響を推定する。帰還
抵抗Ｒｆの抵抗値を１０ｋΩ、ＶＯＵＴを１０Ｖとする
と、帰還抵抗Ｒｆの発熱は１０ｍＷになる。そして、帰
還抵抗Ｒｆから外部への熱抵抗を５０℃／Ｗとすると、
Δｔ＝０．５℃になり、５０ｐｐｍ程度の誤差になって
しまう。Here, the absolute temperature coefficient of the feedback resistor Rf is set to 1
The effect of self-heating is estimated to be 00 ppm / ° C. When the resistance value of the feedback resistor Rf is 10 kΩ and V OUT is 10 V, the heat generation of the feedback resistor Rf is 10 mW. Then, if the thermal resistance from the feedback resistor Rf to the outside is 50 ° C./W,
Δt = 0.5 ° C., resulting in an error of about 50 ppm.
【０００７】モノリシック構成の場合、各抵抗での相対
温度係数は小さくなるが、絶対温度係数は相対温度係数
に比べて大きい。従って、全体の精度を上げる場合、相
対温度係数に加え、絶対温度係数も小さくする必要があ
る。In the case of the monolithic structure, the relative temperature coefficient of each resistor is small, but the absolute temperature coefficient is larger than the relative temperature coefficient. Therefore, in order to improve the overall accuracy, it is necessary to reduce the absolute temperature coefficient in addition to the relative temperature coefficient.
【０００８】また、抵抗Ｒｆとパッケージ外部との熱抵
抗による時定数は長いため、上記現象に伴う出力電圧の
整定に時間がかかってしまうという問題もある。本発明
は、このような従来の問題点に鑑みてなされたものであ
り、その目的は、絶対温度係数の影響が軽減でき、出力
電圧の整定時間が短縮できるラダー形ＤＡコンバータを
提供することにある。Further, since the time constant due to the thermal resistance between the resistor Rf and the outside of the package is long, there is also a problem that it takes time to settle the output voltage due to the above phenomenon. The present invention has been made in view of such conventional problems, and an object thereof is to provide a ladder type DA converter capable of reducing the influence of the absolute temperature coefficient and shortening the settling time of the output voltage. is there.
【０００９】[0009]
【課題を解決するための手段】本発明に係るラダー形Ｄ
Ａコンバータは、ラダー抵抗回路網と電流加算演算増幅
器用の帰還抵抗が１チップ化されたラダー形ＤＡコンバ
ータにおいて、前記帰還抵抗の近傍に帰還抵抗と熱的に
結合された温度制御用抵抗を設けたことを特徴とするも
のである。A ladder type D according to the present invention
The A converter is a ladder type DA converter in which a ladder resistor network and a feedback resistor for a current addition operational amplifier are integrated into one chip, and a temperature control resistor thermally coupled to the feedback resistor is provided in the vicinity of the feedback resistor. It is characterized by that.
【００１０】[0010]
【作用】温度制御用抵抗は、絶対温度係数が出力精度に
影響する帰還抵抗近傍での発熱が一定になるように制御
する。The temperature control resistance is controlled so that the heat generation is constant near the feedback resistance whose absolute temperature coefficient affects the output accuracy.
【００１１】これにより、絶対温度係数の影響を軽減で
き、出力電圧の整定時間が短縮できる。As a result, the influence of the absolute temperature coefficient can be reduced and the settling time of the output voltage can be shortened.
【００１２】[0012]
【実施例】以下、図面を参照して、本発明の実施例を詳
細に説明する。図１は本発明の一実施例の要部接続図で
あり、図３と共通する部分には同一の符号を付けてそれ
らの再説明は省略する。図１では、図３の帰還抵抗Ｒｆ
の近傍に、帰還抵抗Ｒｆと熱的に結合された状態で温度
制御用抵抗Ｒｃも１チップ化されている。該温度制御用
抵抗Ｒｃには出力電圧に対応した信号が印加され、帰還
抵抗Ｒｆの近傍での発熱が一定になるように制御され
る。Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a connection diagram of essential parts of one embodiment of the present invention, in which parts common to those in FIG. 3 are assigned the same reference numerals and re-explanation thereof is omitted. In FIG. 1, the feedback resistor Rf of FIG.
A temperature control resistor Rc, which is thermally coupled to the feedback resistor Rf in the vicinity of, is also integrated into one chip. A signal corresponding to the output voltage is applied to the temperature control resistor Rc so that heat generation near the feedback resistor Rf is controlled to be constant.
【００１３】図２は図１の１チップ化された抵抗回路網
を用いたラダー形ＤＡコンバータの具体例の接続図であ
る。演算増幅器Ａ２及び乗算器Ａ３は温度制御用抵抗Ｒ
ｃの発熱量を制御する制御回路を構成している。乗算器
Ａ３は３つの入力端子ａ，ｂ，ｃと１個の出力端子ｄを
備えていて、入力端子ａには抵抗Ｒを介して出力電圧Ｖ
ＯＵＴが入力されるとともに抵抗Ｒを介して基準電圧Ｖ
ＲＥＦが入力され、入力端子ｂには抵抗Ｒを介して出力
電圧ＶＯＵＴが入力されるとともに抵抗Ｒを介して基準
電圧−ＶＲＥＦが入力され、入力端子ｃには抵抗Ｒを介
して演算増幅器Ａ２の出力電圧Ｖｃが入力され、出力端
子ｄは演算増幅器Ａ２の反転入力端子に接続されてい
る。演算増幅器Ａ２の非反転入力端子はアースに接続さ
れ、演算増幅器Ａ２の反転入力端子と出力端子間には抵
抗Ｒが接続され、演算増幅器Ａ２の出力端子は温度制御
用抵抗Ｒｃの一端に接続されている。温度制御用抵抗Ｒ
ｃの他端はアースに接続されている。FIG. 2 is a connection diagram of a concrete example of a ladder type DA converter using the resistance circuit network which is made into one chip in FIG. The operational amplifier A2 and the multiplier A3 are provided with a temperature control resistor R
A control circuit for controlling the heat generation amount of c is configured. The multiplier A3 has three input terminals a, b, c and one output terminal d, and the input terminal a has an output voltage V via a resistor R.
A reference voltage V is input via the resistor R while OUT is input.
REF is input, the output voltage V OUT is input to the input terminal b via the resistor R, the reference voltage −V REF is input to the input terminal b via the resistor R, and the operational amplifier is input to the input terminal c via the resistor R. The output voltage Vc of A2 is input, and the output terminal d is connected to the inverting input terminal of the operational amplifier A2. The non-inverting input terminal of the operational amplifier A2 is connected to ground, the resistor R is connected between the inverting input terminal and the output terminal of the operational amplifier A2, and the output terminal of the operational amplifier A2 is connected to one end of the temperature control resistor Rc. ing. Temperature control resistor R
The other end of c is connected to ground.
【００１４】帰還抵抗Ｒｆでの発熱をＰｆとすると、 Ｐｆ＝ＶＯＵＴ ２／Ｒｆ…(1) になる。If the heat generated by the feedback resistor Rf is Pf, then Pf = V OUT 2 / Rf (1)
【００１５】帰還抵抗Ｒｆ及び温度制御用抵抗Ｒｃでの
発熱をＰｋとおき、仮にここでの発熱を次式で表すとす
る。 Ｐｋ＝ＶＲＥＦ ２／Ｒｆ…(2) このとき、温度制御用抵抗Ｒｃでの発熱Ｐｃが以下のよ
うになるように演算増幅器Ａ２の出力電圧Ｖｃを制御す
ればよい。It is assumed that the heat generated by the feedback resistor Rf and the temperature control resistor Rc is Pk, and the heat generated here is represented by the following equation. Pk = V REF 2 / Rf (2) At this time, the output voltage Vc of the operational amplifier A2 may be controlled so that the heat generation Pc at the temperature control resistor Rc becomes as follows.
【００１６】Ｐｃ＝Ｐｋ−Ｐｆ…(3) Ｖｃ２／Ｒｃ＝（ＶＲＥＦ ２／Ｒｆ）−（ＶＯＵＴ ２／Ｒｆ）…(4) ここで、Ｒｃ＝Ｒｆなら、 Ｖｃ２＝ＶＲＥＦ ２−ＶＯＵＴ ２…(4)´ 一方、乗算器Ａ３は、Ｉ３＝Ｉ１×Ｉ２／Ｉ４で表され
る伝達関数を持っている。そして、これら各電流は以下
のように表される。Pc = Pk-Pf (3) Vc 2 / Rc = (V REF 2 / Rf)-(V OUT 2 / Rf) (4) If Rc = Rf, then Vc 2 = V REF 2 -V OUT 2 (4) 'On the other hand, the multiplier A3 has a transfer function represented by I 3 = I 1 × I 2 / I 4 . Then, each of these currents is expressed as follows.
【００１７】 Ｉ１＝（ＶＯＵＴ／Ｒ）＋（ＶＲＥＦ／Ｒ）…(5) Ｉ２＝（ＶＯＵＴ／Ｒ）−（ＶＲＥＦ／Ｒ）…(6) Ｉ４＝Ｖｃ／Ｒ…(7) Ｉ３＝｛（ＶＯＵＴ＋ＶＲＥＦ）／Ｒ｝×｛（ＶＯＵＴ−ＶＲＥＦ）／Ｒ｝× ×（Ｒ／Ｖｃ）…(8) Ｖｃ＝−ＲＩ３…(9) (8) 式と(9) 式を整理すると、 −Ｖｃ＝（ＶＯＵＴ＋ＶＲＥＦ）×（ＶＯＵＴ−ＶＲＥＦ）／Ｖｃ…(10) になる。この(10)式は、帰還抵抗Ｒｆ及び温度制御用抵
抗Ｒｃ近傍での発熱を一定にする条件を表す(4) 式と等
しくなる。I 1 = (V OUT / R) + (V REF / R) (5) I 2 = (V OUT / R)-(V REF / R) (6) I 4 = Vc / R ... (7) I 3 = {( V OUT + V REF) / R} × {(V OUT -V REF) / R} × × (R / Vc) ... (8) Vc = -RI 3 ... (9) (8 When the equations (9) and (9) are arranged, −Vc = (V OUT + V REF ) × (V OUT −V REF ) / Vc (10). The expression (10) is equal to the expression (4) that represents the condition for keeping the heat generation near the feedback resistance Rf and the temperature control resistance Rc constant.
【００１８】これらから明らかなように、図２の回路構
成によれば、帰還抵抗Ｒｆの自己発熱によるドリフトの
影響を軽減でき、出力電圧の整定時間が短縮できる。な
お、(5) 式及び(6) 式が以下のようになるように構成し
てもＶｃの極性が異なるのみでＰｃは同一になり、同様
の効果が得られる。As is apparent from the above, according to the circuit configuration of FIG. 2, the influence of drift due to self-heating of the feedback resistor Rf can be reduced, and the settling time of the output voltage can be shortened. Even if the equations (5) and (6) are configured as follows, Pc is the same except that the polarity of Vc is different, and the same effect can be obtained.
【００１９】 Ｉ１＝−（ＶＯＵＴ／Ｒ）＋（ＶＲＥＦ／Ｒ）…(5)´ Ｉ２＝（ＶＯＵＴ／Ｒ）＋（ＶＲＥＦ／Ｒ）…(6)´ また、信号変化に比べて熱時定数は大きいので、演算増
幅器Ａ２及び乗算器Ａ３は比較的低速なデバイスでよ
く、安価に構成できる。I 1 = − (V OUT / R) + (V REF /R)...(5 ) ′ I 2 = (V OUT / R) + (V REF / R) ... (6) ′ Also signal changes Since the thermal time constant is larger than that of, the operational amplifier A2 and the multiplier A3 may be relatively slow devices and can be inexpensively constructed.
【００２０】[0020]
【発明の効果】以上説明した本発明によれば、ラダー抵
抗回路網と同一のチップ上に抵抗を１本追加するだけで
ラダー抵抗回路網の絶対温度係数を小さくする必要はな
く、安価かつ低速なデバイスよりなる付加回路と組み合
わせることによって、高精度で出力電圧の整定時間が短
いラダー形ＤＡコンバータが提供できる。According to the present invention described above, it is not necessary to reduce the absolute temperature coefficient of the ladder resistor network by only adding one resistor on the same chip as the ladder resistor network, and the cost is low and the speed is low. A ladder type DA converter with high accuracy and a short settling time of the output voltage can be provided by combining with an additional circuit composed of various devices.
【図１】本発明の一実施例の要部接続図である。FIG. 1 is a connection diagram of essential parts of an embodiment of the present invention.
【図２】図１の１チップ化された抵抗回路網を用いたラ
ダー形ＤＡコンバータの具体例の接続図である。FIG. 2 is a connection diagram of a specific example of a ladder type DA converter using the resistance circuit network formed into one chip in FIG.
【図３】従来のラダー形ＤＡコンバータの一例を示す接
続図である。FIG. 3 is a connection diagram showing an example of a conventional ladder type DA converter.
ＴＲＥＦ 基準電圧入力端子 Ｔ−１〜Ｔ−Ｎ ディジタル信号入力端子 ＴＯＵＴ 出力端子 ＲＡ，ＲＢ ラダー抵抗 Ｒｆ 帰還抵抗 Ｒｃ 温度制御用抵抗 Ｒ 抵抗 Ｓ１〜ＳＮ 切換スイッチ Ａ１，Ａ２ 演算増幅器 Ａ３ 乗算器T REF reference voltage input terminal T-1 to TN digital signal input terminal T OUT output terminal RA, RB ladder resistance Rf feedback resistance Rc temperature control resistance R resistance S1 to SN changeover switch A1, A2 operational amplifier A3 multiplier
Claims (1)
用の帰還抵抗が１チップ化されたラダー形ＤＡコンバー
タにおいて、 前記帰還抵抗の近傍に帰還抵抗と熱的に結合された温度
制御用抵抗を設けたことを特徴とするラダー形ＤＡコン
バータ。1. A ladder type DA converter in which a feedback resistor for a ladder resistor network and a current addition operational amplifier is integrated into one chip, and a temperature control resistor thermally coupled to the feedback resistor is provided in the vicinity of the feedback resistor. A ladder type DA converter characterized by being provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6492092A JPH05268094A (en) | 1992-03-23 | 1992-03-23 | Ladder shape da converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6492092A JPH05268094A (en) | 1992-03-23 | 1992-03-23 | Ladder shape da converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05268094A true JPH05268094A (en) | 1993-10-15 |
Family
ID=13271968
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6492092A Pending JPH05268094A (en) | 1992-03-23 | 1992-03-23 | Ladder shape da converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05268094A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9553603B2 (en) | 2015-03-30 | 2017-01-24 | Lapis Semiconductor Co., Ltd. | R-2R ladder resistor circuit, ladder resistor type D/A conversion circuit, and semiconductor device |
-
1992
- 1992-03-23 JP JP6492092A patent/JPH05268094A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9553603B2 (en) | 2015-03-30 | 2017-01-24 | Lapis Semiconductor Co., Ltd. | R-2R ladder resistor circuit, ladder resistor type D/A conversion circuit, and semiconductor device |
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