JPH05267945A - Amplifier provided with overload control circuit - Google Patents

Amplifier provided with overload control circuit

Info

Publication number
JPH05267945A
JPH05267945A JP4062938A JP6293892A JPH05267945A JP H05267945 A JPH05267945 A JP H05267945A JP 4062938 A JP4062938 A JP 4062938A JP 6293892 A JP6293892 A JP 6293892A JP H05267945 A JPH05267945 A JP H05267945A
Authority
JP
Japan
Prior art keywords
amplifier
terminal
voltage
input
control signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4062938A
Other languages
Japanese (ja)
Inventor
Shuichi Koreeda
修一 是枝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4062938A priority Critical patent/JPH05267945A/en
Publication of JPH05267945A publication Critical patent/JPH05267945A/en
Withdrawn legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE:To provide the amplifier with an overload control circuit for detecting an excessive signal input from a supply current to an FET. CONSTITUTION:A variable attenuator 1 for receiving an input signal from an input terminal 11 increases the attenuation quantity by an input of a control signal S3 from a comparator 3, and avoids an excessive signal input of an amplifier 2 having an FET. The amplifier 2 for outputting an amplifying signal to an output terminal 12 receives a positive drain voltage from a terminal 15 by a terminal 14, and receives a negative gate voltage from a terminal 16 by a terminal 13. In an overload state of the amplifier 2, in which a voltage S1 of the terminal 14 is lower than a reference voltage from a reference voltage input terminal 17, a comparator 3 outputs a control signal S3.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は過大信号入力(過負荷)
を防止することができる過負荷制御回路付き増幅器に関
する。
BACKGROUND OF THE INVENTION The present invention relates to an excessive signal input (overload).
The present invention relates to an amplifier with an overload control circuit capable of preventing the above.

【0002】[0002]

【従来の技術】従来のこの種の過負荷制御回路付き増幅
器は、FET(フィールド・エフェクト・トランジス
タ)を増幅素子とする増幅器と、この増幅器の前段に接
続され制御信号の入力により減衰量を増加させる可変減
衰器と、上記増幅器の前段に接続され上記増幅器の入力
信号レベルを検出する検波器と、この検波器出力と予め
設定されている過負荷レベルとを比較して上記検波器出
力が上記過負荷レベルより大きいときには上記制御信号
を発生する可変減衰器制御手段とを備えていた。そし
て、上記増幅器への過大入力が検知されると、上記可変
減衰器の減衰量を増加させて上記増幅器の過負荷状態を
解消させていた。
2. Description of the Related Art A conventional amplifier with an overload control circuit of this type is an amplifier having an FET (field effect transistor) as an amplifying element and is connected to the preceding stage of this amplifier to increase the attenuation amount by inputting a control signal. The variable attenuator for detecting the input signal level of the amplifier connected to the preceding stage of the amplifier, and comparing the detector output with a preset overload level, the detector output And a variable attenuator control means for generating the control signal when the load level is higher than the overload level. When an excessive input to the amplifier is detected, the attenuation amount of the variable attenuator is increased to eliminate the overload state of the amplifier.

【0003】[0003]

【発明が解決しようとする課題】上述した従来の過負荷
制御回路付き増幅器は、信号伝送路に上記増幅器の過負
荷状態を検知する検波器を必要とするため、小型・軽量
化が困難であるという欠点があった。この欠点は極端な
小型軽量化が要求される衛星搭載用増幅器においては特
に重大となる。
The above-mentioned conventional amplifier with an overload control circuit requires a detector for detecting the overload state of the amplifier in the signal transmission line, and thus it is difficult to reduce the size and weight. There was a drawback. This drawback is particularly serious in the satellite-mounted amplifier which requires extremely small size and light weight.

【0004】[0004]

【課題を解決するための手段】本発明の過負荷制御回路
付き増幅器は、FETを増幅素子とする増幅器と、前記
増幅器の前段に接続され制御信号の入力により減衰量を
増加させる可変減衰器と、前記FETのドレイン電流を
検知するドレイン電流検知手段と、検知された前記ドレ
イン電流が予め定めた第1の基準値以上のときには前記
制御信号を発生する第1の制御信号発生手段とを備えて
いる。
An amplifier with an overload control circuit according to the present invention comprises an amplifier having an FET as an amplifying element, and a variable attenuator connected to the preceding stage of the amplifier for increasing an attenuation amount by inputting a control signal. A drain current detecting means for detecting a drain current of the FET, and a first control signal generating means for generating the control signal when the detected drain current is equal to or more than a predetermined first reference value. There is.

【0005】また、前記FETのドレイン電流を検知す
る代りに前記FETのゲート電流を検知するゲート電流
検知手段と、前記第1の制御信号発生手段の代りに検知
された前記ゲート電流が予め定めた第2の基準値以上の
ときには前記制御信号を発生する第2の制御信号発生手
段とを備えてもよい。
Further, instead of detecting the drain current of the FET, the gate current detecting means for detecting the gate current of the FET and the detected gate current instead of the first control signal generating means are predetermined. A second control signal generating means for generating the control signal when the second reference value or more is obtained may be provided.

【0006】[0006]

【実施例】次に本発明について図面を参照して説明す
る。
The present invention will be described below with reference to the drawings.

【0007】図1は本発明の第1の実施例の回路図であ
る。この過負荷制御回路付き増幅器の入力端子11から
入力された信号は可変減衰器1を通り、FETを増幅素
子とする増幅器2に入力される。この増幅器2からの出
力信号は出力端子12に出力される。増幅器2内のFE
Tのドレイン(D)には、正電源端子15の正電圧(+
V)が抵抗器R4を介して供給された電圧であるドレイ
ン電圧S1がドレイン電源端子14から供給される。ま
た、上記FETのゲート(G)には、負電源端子16の
負電圧(−V)を抵抗器R2およびR3によって分圧し
さらに抵抗器R1を通った電圧であるゲート電圧がゲー
ト電源端子13から供給される。そして、端子14の電
圧S1がコンパレータ3の一方の入力端に加えられ、上
記コンパレータ3の他方の入力端には基準電圧入力端1
7から第1の基準電圧S2が加えられる。
FIG. 1 is a circuit diagram of a first embodiment of the present invention. A signal input from the input terminal 11 of the amplifier with the overload control circuit passes through the variable attenuator 1 and is input to the amplifier 2 having the FET as an amplification element. The output signal from the amplifier 2 is output to the output terminal 12. FE in amplifier 2
The drain (D) of T has a positive voltage (+
The drain voltage S1 which is the voltage V) supplied via the resistor R4 is supplied from the drain power supply terminal 14. Further, the gate (G) of the FET is divided from the negative voltage (-V) of the negative power supply terminal 16 by the resistors R2 and R3, and further, the gate voltage which is the voltage passing through the resistor R1 is supplied from the gate power supply terminal 13. Supplied. The voltage S1 at the terminal 14 is applied to one input terminal of the comparator 3, and the reference voltage input terminal 1 is applied to the other input terminal of the comparator 3.
A first reference voltage S2 from 7 is applied.

【0008】ここで、端子14の電圧S1が増幅器2の
過負荷の判断基準とされる第1の基準電圧S2より低い
場合に、増幅器2は過負荷と判断される。即ち、増幅器
2への入力電力が増すにつれて端子14に供給されるド
レイン電流が増加し、従って抵抗値R4による電圧降下
により端子14の電圧が低下するが、過負荷状態の端子
14の電圧S01を予め測定しておき、上記第1の基準
電圧S2を上記電圧S01に設定しておくことで、上記
判断が可能となる。
Here, when the voltage S1 at the terminal 14 is lower than the first reference voltage S2 which is the reference for judging the overload of the amplifier 2, the amplifier 2 is judged to be overloaded. That is, as the input power to the amplifier 2 increases, the drain current supplied to the terminal 14 increases, and therefore the voltage of the terminal 14 decreases due to the voltage drop due to the resistance value R4. The above determination can be made by measuring in advance and setting the first reference voltage S2 to the voltage S01.

【0009】コパレータ3は、上記電圧S1が上記第1
の基準電圧S2より低いと、制御信号S3を発生して可
変減衰器1の減衰量を増加させる。従って、増幅器2の
入力レベルは低下し、増幅器2の過負荷状態を回避でき
る。
In the comparator 3, the voltage S1 is the first voltage
When the voltage is lower than the reference voltage S2, the control signal S3 is generated to increase the attenuation amount of the variable attenuator 1. Therefore, the input level of the amplifier 2 is lowered, and the overloaded state of the amplifier 2 can be avoided.

【0010】図2は本発明の第2の実施例の回路図であ
る。この過負荷制御回路付き増幅器は、図1の実施例回
路とほぼ同じであるが、コパレータ3の一方の入力端に
は、抵抗器R1とR2の接続点(P点)からの電圧S4
が加えられ、上記コンパレータ3の他方の入力端には基
準電圧入力端17から第2の基準電圧S5が加えられ
る。
FIG. 2 is a circuit diagram of the second embodiment of the present invention. This amplifier with an overload control circuit is almost the same as the circuit of the embodiment shown in FIG. 1, except that the voltage S4 from the connection point (point P) of the resistors R1 and R2 is applied to one input terminal of the comparator 3.
Then, the second reference voltage S5 is applied from the reference voltage input terminal 17 to the other input terminal of the comparator 3.

【0011】この図2の実施例においては、P点の電圧
S4が増幅器2の過負荷の判断基準とされる第2の基準
電圧S5より低い場合に、増幅器2は過負荷と判断され
る。即ち、増幅器2への入力電力が増すにつれて端子1
3に供給されるゲート電流が増加し、従って抵抗値R1
による電圧降下により端子13の電圧が低下するが、過
負荷状態の端子13の電圧S02を予め測定しておき、
上記第1の基準電圧S5を上記電圧S02に設定してお
くことで、上記判断が可能となる。
In the embodiment shown in FIG. 2, the amplifier 2 is judged to be overloaded when the voltage S4 at the point P is lower than the second reference voltage S5, which is the reference for judging the overload of the amplifier 2. That is, as the input power to the amplifier 2 increases, the terminal 1
3, the gate current supplied to 3 increases, and thus the resistance value R1
Although the voltage of the terminal 13 drops due to the voltage drop due to, the voltage S02 of the terminal 13 in the overloaded state is measured in advance,
The determination can be made by setting the first reference voltage S5 to the voltage S02.

【0012】コパレータ3は、上記電圧S4が上記第2
の基準電圧S5より低いと、制御信号S3を発生して可
変減衰器1の減衰量を増加させる。従って、増幅器2の
入力レベルは低下し、増幅器2の過負荷状態を回避でき
る。
In the comparator 3, the voltage S4 is the second voltage.
When the voltage is lower than the reference voltage S5, the control signal S3 is generated to increase the attenuation amount of the variable attenuator 1. Therefore, the input level of the amplifier 2 is lowered, and the overloaded state of the amplifier 2 can be avoided.

【0013】[0013]

【発明の効果】以上説明したように本発明は、増幅器の
FETへの供給電流を検知して上記増幅器の過負荷状態
を検出するので、信号伝送路に上記増幅器の過負荷状態
を検知する検波器を必要とせず、容易に小型・軽量化を
達成できる効果がある。これは、極端な小型軽量化が要
求される衛星搭載用増幅器においては特に有効である。
As described above, according to the present invention, the supply current to the FET of the amplifier is detected to detect the overload state of the amplifier. Therefore, the detection for detecting the overload state of the amplifier in the signal transmission line is performed. There is an effect that it is possible to easily reduce the size and weight without using a vessel. This is particularly effective for an on-board amplifier that requires extremely small size and light weight.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明による第1の実施例の回路図である。FIG. 1 is a circuit diagram of a first embodiment according to the present invention.

【図2】本発明による第2の実施例の回路図である。FIG. 2 is a circuit diagram of a second embodiment according to the present invention.

【符号の説明】[Explanation of symbols]

1 可変減衰器 2 増幅器 3 コンパレータ 11 入力端子 12 出力端子 13 ゲート電源端子 14 ドレイン電源端子 15 正電源端子 16 負電源端子 17 基準電圧入力端 1 Variable Attenuator 2 Amplifier 3 Comparator 11 Input Terminal 12 Output Terminal 13 Gate Power Supply Terminal 14 Drain Power Supply Terminal 15 Positive Power Supply Terminal 16 Negative Power Supply Terminal 17 Reference Voltage Input Terminal

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 FETを増幅素子とする増幅器と、前記
増幅器の前段に接続され制御信号の入力により減衰量を
増加させる可変減衰器と、前記FETのドレイン電流を
検知するドレイン電流検知手段と、検知された前記ドレ
イン電流が予め定めた基準値以上のときには前記制御信
号を発生する制御信号発生手段とを備えることを特徴と
する過負荷制御回路付き増幅器。
1. An amplifier using an FET as an amplifying element, a variable attenuator connected to the preceding stage of the amplifier to increase an attenuation amount by inputting a control signal, and a drain current detecting means for detecting a drain current of the FET. An amplifier with an overload control circuit, comprising: a control signal generating means for generating the control signal when the detected drain current is equal to or higher than a predetermined reference value.
【請求項2】 FETを増幅素子とする増幅器と、前記
増幅器の前段に接続され制御信号の入力により減衰量を
増加させる可変減衰器と、前記FETのゲート電流を検
知するゲート電流検知手段と、検知された前記ドレイン
電流が予め定めた基準値以上のときには前記制御信号を
発生する制御信号発生手段とを備えることを特徴とする
過負荷制御回路付き増幅器。
2. An amplifier using an FET as an amplifying element, a variable attenuator connected to a preceding stage of the amplifier for increasing an attenuation amount by inputting a control signal, and a gate current detecting means for detecting a gate current of the FET. An amplifier with an overload control circuit, comprising: a control signal generating means for generating the control signal when the detected drain current is equal to or higher than a predetermined reference value.
JP4062938A 1992-03-19 1992-03-19 Amplifier provided with overload control circuit Withdrawn JPH05267945A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4062938A JPH05267945A (en) 1992-03-19 1992-03-19 Amplifier provided with overload control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4062938A JPH05267945A (en) 1992-03-19 1992-03-19 Amplifier provided with overload control circuit

Publications (1)

Publication Number Publication Date
JPH05267945A true JPH05267945A (en) 1993-10-15

Family

ID=13214746

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4062938A Withdrawn JPH05267945A (en) 1992-03-19 1992-03-19 Amplifier provided with overload control circuit

Country Status (1)

Country Link
JP (1) JPH05267945A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4005676A1 (en) * 1990-02-22 1991-08-29 Buchtal Gmbh Radar wave absorber for building - uses ceramic plates attached to building wall with directly attached reflective layer
JP2010199714A (en) * 2009-02-23 2010-09-09 Nec Corp Excessive input determination circuit and amplifying device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4005676A1 (en) * 1990-02-22 1991-08-29 Buchtal Gmbh Radar wave absorber for building - uses ceramic plates attached to building wall with directly attached reflective layer
JP2010199714A (en) * 2009-02-23 2010-09-09 Nec Corp Excessive input determination circuit and amplifying device

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Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19990608