JPH05266225A - Microcomputer - Google Patents

Abstract

PURPOSE:To prevent the third person from easily taking out contents of an incorporated ROM in a microcomputer provided with the incorporated ROM and another memory. CONSTITUTION:An incorporated ROE read inhibiting part 19 is provided which invalidates data outputted from an incorporated ROM 6 in accordance with the output of a logic gate 18. A read inhibiting logic gate 21 which is opened and closed based on the output of the logic gate 18 is inserted to each data output line 20 of the incorporated ROM 6 to constitute this incorporated ROM read inhibiting part 19, and data outputted from the incorporated ROM 6 is invalidated when the incorporated ROM 6 is accessed by a program stored in the memory other than the incorporated ROM 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to confidentiality of information stored in a built-in ROM in a microcomputer provided with a built-in ROM and other memories.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing an example of a conventional microcomputer having a built-in ROM and a memory other than the above. In the figure, 1 is a microcomputer, 2 is an external bus that serves as a path for data, addresses, and various control signals between the microcomputer 1 and external devices, and 3 is a built-in RO accessible via the external bus 2.
External memory as a memory other than M, 4 is a CPU core,
Reference numeral 5 is an input / output unit for exchanging data, addresses and various control signals with the external bus 2, 6 is a built-in ROM for storing programs and data, 7 is a built-in RAM as a memory other than the built-in ROM 6, and 8 is a microcomputer. It is an internal bus that serves as a path for data, addresses, and various control signals between blocks in one. The CPU core 4 has an instruction fetch unit 10 that reads an instruction from each of the memories via the internal bus 8, an instruction decoding unit 11 that decodes the instruction read by the instruction fetch unit 10, and an instruction decoding unit. A control unit 12 that generates a control signal for executing an instruction based on the information of the instruction obtained in 11, an execution unit 13 that executes an instruction by performing an operation or the like by the control signal of the control unit 12, and the instruction fetch unit. 10 and a program counter 14 which indicates the address of the instruction to be fetched.

FIG. 5 is a block diagram of the inside of the control unit 12 in FIG. In the figure, 23 is an instruction decoding unit 11.
Depending on the command information input from the micro ROM2
4, a control circuit for controlling the micro program counter 22, 22 is a micro program counter indicating the address of the micro ROM 24, and 24 is the microcomputer 1
This is a micro ROM that stores information for controlling the hardware configuring the above as data, and outputs the read control information as a control signal.

FIG. 6 is a conceptual diagram showing an example of an address space of a microcomputer including a conventional built-in ROM and a memory other than that. In this example, 4 KB out of 64 KB (kilobytes) of the entire address space is built-in ROM
6, 1 KB is mounted as the built-in RAM 7.
The external memory 3 can be expanded to the remaining 59 KB. For example, addresses from H'0000 (H'XXXX indicates that XXX is represented in hexadecimal notation, and so on) to H'0FFF are assigned to the built-in ROM 6, and the built-in ROM 6 is assigned according to this range of addresses.
Can access. Similarly, the internal RAM 7 and the external memory 3 are H'1000 to H'13FF and H'14, respectively.
Addresses such as 00 to H'FFFF are assigned. Hereinafter, when the address of the built-in ROM 6 is referred to, it represents an arbitrary address assigned to the built-in ROM 6.

Next, the operation of executing the program will be described with reference to FIG. The instruction fetch unit 10 fetches the instruction stored at the address indicated by the program counter 14 via the internal bus 8, or the internal bus 8, the input / output unit 5, and the external bus 2 by the input / output unit 9. Normally, a microcomputer with a built-in ROM has a built-in R
Although the instruction is stored in the OM 6, it is also possible to fetch the instruction on the internal RAM 7 as a memory other than the internal ROM and the external memory 3. The instruction decoding unit 11 decodes the fetched instruction and sends the result to the control unit 12. The control unit 12 generates a control signal for executing the instruction based on the information and sends it to the execution unit 13, and the execution unit 13 executes the instruction. The program is executed by repeating the above operation.

Next, referring to FIG. 4, a third party has built-in ROM 6
The operation of taking out the contents of the built-in ROM 6 to the outside for the purpose of knowing the contents of the program stored in will be described. First, the following instructions are stored in the built-in RAM 7. LDA [address of built-in ROM 6] STA [address of external memory 3] However, the instructions LDA and STA have the following functions. LDA: The data stored at the address indicated by the operand is stored in the register. STA: The register value is stored at the address indicated by the operand. The instruction fetch unit 10 fetches the instruction LDA [address of the built-in ROM 6] stored in the built-in RAM 7 via the internal bus 8 by the input / output unit 9. The execution unit 13 executes this instruction by the control signal generated from the decoding result. That is, the built-in RO indicated by the operand
The data stored at the address of M6 is stored in a register (not shown) in the execution unit 13 via the input / output unit 9 and the internal bus 8. Next, the instruction fetch unit 10 fetches the instruction STA [address of the external memory 3] stored in the internal RAM 7 via the internal bus 8 by the input / output unit 9. The execution unit 13 executes this instruction by the control signal generated from the decoding result. That is, the value of the register is stored in the address of the external memory 3 indicated by the operand via the input / output unit 9, the internal bus 8, the input / output unit 5, and the external bus 2. By repeating the above operation while incrementing the operand addresses of the instructions LDA and STA, the entire contents of the internal ROM 6 can be transferred to the external memory 3.

[0007]

Conventional built-in ROM 6
And the other memory, the microcomputer 1 is configured as described above.
There is a problem that the contents of the built-in ROM 6 can be taken out by a program stored in a memory other than 6 and a third person can easily know the contents of the built-in ROM 6.

The present invention has been made to solve the above problems, and an object thereof is to obtain a microcomputer 1A in which the contents of a built-in ROM cannot be easily taken out to the outside.

[0009]

A microcomputer 1A according to a first invention outputs to a first address comparator 15 for detecting that the value of the program counter 14 is not an address of the internal ROM 6 and an address bus. A second address comparator 16 for detecting that the stored value is the address of the built-in ROM 6, and an operand access indicating that an address is output to access the data stored in the memory as an operand. The signal line 17 and the first and second address comparators 15 and 1
A logic gate 18 for inputting the output signal of 6 and the operand access signal, and a built-in ROM read prohibiting section 19 for invalidating the data output from the built-in ROM 6 according to the output of the logic gate 18 are provided. Built-in ROM
If the built-in ROM 6 is accessed by a program stored in a memory other than
The data output from 6 is invalidated.

Microcomputer 1 according to the second invention
A includes the built-in ROM read prohibiting section 19 in which a read prohibiting logic gate 21 which is opened / closed based on the output of the logic gate is inserted into each data output line 20 of the built-in ROM 6.

[0011]

Operation: Microcomputer 1A according to the first invention
Is a signal indicating that the value of the program counter 14 output from the first address comparator 15 is not the address of the internal ROM 6 and the value output to the address bus output from the second address comparator 16. A signal indicating that the address is the address of the built-in ROM 6 and that the address is output from the control section through the operand access signal line 17 to access the data stored in the memory as an operand. When all the operand access signals are turned on, the logic gate 18 which inputs these signals outputs a signal which turns on the built-in ROM read prohibiting section 19.

Microcomputer 1 according to the second invention
When a turn-on output signal is input from the logic gate 18, the read-out prohibiting logic gate 21 turns on, and is invalidated regardless of the value output to each data output line 20 of the internal ROM 6. Only the processed data is output to the internal bus 8.

[0013]

FIG. 1 shows an embodiment of a microcomputer 1A having a built-in ROM according to the present invention and a memory other than that. In the figure, the same parts as those in FIG. In the figure, 15 is a first address comparator that detects that the value of the program counter 14 is not the address of the internal ROM 6, and 16 is a second address comparator that detects that the address output to the internal bus 8 is the address of the internal ROM 6. Address comparator, 17 is an operand access signal line indicating that the CPU core 4 outputs an address for accessing the data stored in the memory as an operand, and 18 is the first address comparator 15 and the second address comparator.
, A logic gate for inputting a signal output from the address comparator 16 and an operand access signal, 19 is a logic gate 18
It is a built-in ROM read-out prohibiting section that inputs a signal output from the built-in ROM and invalidates the data output from the built-in ROM 6.

Built-in ROM read prohibiting section 19 according to the present invention
FIG. 2 shows a circuit diagram inside the device. In the figure, 20 is the number of bus lines, a data output line through which the built-in ROM 6 outputs data, 21 is inserted in each of the data output lines 20, the input is connected to the logic gate 18, and the output is the data bus. Is a read-inhibit logic gate connected to.

The internal block diagram of the control unit 12 in FIG. 1 is the same as that in FIG. Among the control signals output from the micro ROM 24, there is usually a signal indicating that the operand is being accessed. This signal line is connected to the operand access signal line.

The operation of the built-in ROM read prohibiting section 19 will be described with reference to FIG. When the logic gate 18 outputs "0" (described in positive logic, the same applies to the following), the output of the read inhibit logic gate 21 is the built-in RO.
The value output to the data output line 20 by M6 is output to the internal bus 8 as it is. When the logic gate 18 outputs "1", the read inhibit logic gate 21 outputs the internal ROM.
6 becomes '1' regardless of the value output to the data output line 20, the data of the internal ROM 6 output to the internal bus 8 is invalidated, and reading is prohibited.

Next, referring to FIG. 1, the program has a built-in RO.
The operation when stored in M6 will be described. The address space of the microcomputer 1A according to the present invention is the same as that of the conventional example shown in FIG. The instruction fetch unit 10 has a built-in R via the internal bus 8 by the input / output unit 9.
Fetch the instruction stored in OM6. When the instruction is fetched, the CPU core 4 does not output the address in order to access the data stored in the memory as an operand, so the control unit 12 sets "0" to the operand access signal line 17. Output. Since the value of the program counter 14 is the address of the built-in ROM 6, the first address comparator 15 outputs "0" to the logic gate 18. Since the address output to the internal bus 8 is the address of the built-in ROM 6, the second address comparator 16 outputs "1". As a result, the logic gate 18
Outputs "0" and the built-in ROM read prohibition section 19 has built-in R
Enables reading of OM6. The instruction decoding unit 11 decodes the fetched instruction and sends the result to the control unit 12. The control unit 12 generates a control signal for executing the instruction based on the information and sends it to the execution unit 13. When the execution unit 13 executes an instruction, it may access the data stored in the memory as an operand and the operand access signal may become "1". However, when the program stored in the internal ROM 6 is executed, As long as the first address comparator outputs "0", the built-in ROM read prohibition unit 19 always enables the built-in ROM 6 to be read.
The program is executed by repeating the above operation.

Next, with reference to FIG. 1, an operation in which a third party tries to take out the contents of the built-in ROM 6 to the outside by the same method as shown in the conventional example will be described. First, the following instructions are stored in the built-in RAM 7. LDA [address of built-in ROM 6] STA [address of external memory 3] Instructions LDA and STA are the same as those used in the description of the conventional example. The instruction fetch unit 10 uses the input / output unit 9 via the internal bus 8 to store the instruction L stored in the internal RAM 7.
Fetch DA [address of built-in ROM 6]. When the instruction is fetched, the CPU core 4 does not output the address in order to access the data stored in the memory as an operand, so the control unit 12 sets "0" to the operand access signal line 17. Output. Since the value of the program counter 14 is not the address of the built-in ROM 6, the first address comparator 15 has the logic gate 18
'1' is output for. Since the address output to the internal bus 8 is the address of the built-in ROM 6, the second address comparator 16 outputs "1". As a result, the logic gate 18 outputs "0" and the built-in ROM read prohibition unit 19
Makes it possible to read the internal ROM 6. The execution unit 13 executes this instruction by the control signal generated from the decoding result. That is, the internal ROM indicated by the operand
The data stored at the address 6 is stored in a register (not shown) in the execution unit 13 via the input / output unit 9 and the internal bus 8. At this time, since the CPU core 4 outputs an address for accessing the data stored in the memory as an operand, the control unit 12 outputs "1" to the operand access signal line 17. Since the value of the program counter 14 is not the address of the built-in ROM 6, the first address comparator 15 outputs "1" to the logic gate 18. Since the address output to the internal bus 8 is the address of the built-in ROM 6, the second address comparator 16 outputs "1". As a result, logic gate 1
8 outputs "1" and the built-in ROM read prohibiting section 19 prohibits reading of the built-in ROM 6. Therefore, the value stored in the register in the execution unit 13 is not the value in the built-in ROM 6 but is always data in which all bits are "1". Next, the instruction fetch unit 10 fetches the instruction STA [address of the external memory 3] stored in the internal RAM 7 via the internal bus 8 by the input / output unit 9. The execution unit 13 executes this instruction by the control signal generated from the decoding result.
That is, the value of the register is stored in the address of the external memory 3 indicated by the operand via the input / output unit 9, the internal bus 8, the input / output unit 5, and the external bus 2. The above operation is command L
The contents of the built-in ROM 6 cannot be transferred to the external memory 3 even by repeating the DA and STA operands while incrementing, and all the data written in the external memory 3 is data with all bits being "1".

FIG. 3 shows a table in which the values of the program counter 14 and the addresses to be read are summarized as to whether or not the memory can be read. Reading of the built-in ROM 6 by a program stored in the built-in RAM 7 as a memory other than the built-in ROM 6 and the external memory 3 is prohibited. In the case of other combinations, the built-in ROM 6 can be read out, and the normal program can be executed without any trouble.

In the present embodiment, data having all bits of "1" is always output instead of the output value of the built-in ROM 6 to invalidate the data, but the read-inhibit logic gate 21 is constituted by a NOR gate. By doing so, the data in which all the bits are “0” may be always output.

[0021]

According to the first invention, the first address comparator detects that the value of the program counter is not the address of the built-in ROM, and the value output to the address bus is stored in the built-in ROM. A second address comparator for detecting an address, an operand access signal line indicating that an address is output to access the data stored in the memory as an operand, and the first and second A logic gate for inputting the output signal of the address comparator and the operand access signal, and a built-in ROM read prohibition unit for invalidating the data output from the built-in ROM according to the output of the logic gate. If you try to access the built-in ROM by a program stored in a memory other than the built-in ROM, Because invalidating the data et output can not third parties taken easily outside the contents of the chip ROM, on confidentiality of the microcomputer is improved.

According to the second aspect of the invention, the built-in ROM read prohibition section is constituted by inserting a read-inhibit logic gate which is opened / closed based on the output of the logic gate, into each data output line of the built-in ROM. When a program stored in a memory other than the built-in ROM tries to access the built-in ROM, the data output from the built-in ROM can be invalidated and the reading of the contents can be prohibited. The confidentiality of can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a microcomputer 1A according to the present invention.

FIG. 2 is a circuit diagram showing an example of a built-in ROM read inhibit unit according to the present invention.

FIG. 3 is a diagram showing whether or not the memory of the microcomputer 1A according to the present invention can be read.

FIG. 4 is a block diagram showing an example of a conventional microcomputer 1.

FIG. 5 is a block diagram showing an example of a conventional control unit.

FIG. 6 is a conceptual diagram showing an example of an address space of a conventional microcomputer 1.

[Explanation of symbols]

 1, 1A Microcomputer 3 External memory (memory other than built-in ROM) 6 Built-in ROM 7 Built-in RAM (memory other than built-in ROM) 8 Internal bus 10 Instruction fetch section 11 Instruction decode section 12 Control section 13 Execution section 14 Program counter 15th 1 address comparator 16 second address comparator 17 operand access signal line 18 logic gate 19 built-in ROM read prohibition unit 20 data output line 21 built-in ROM read prohibition logic gate

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[Procedure amendment]

[Submission date] September 16, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 1

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0002

[Correction method] Change

[Correction content]

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing an example of a conventional microcomputer having a built-in ROM and a memory other than the above. In the figure, 1 is a microcomputer, 2 is an external bus that serves as a path for data, addresses, and various control signals between the microcomputer 1 and external devices, and 3 is a built-in RO accessible via the external bus 2.
External memory as a memory other than M, 4 is a CPU core,
Reference numeral 5 is an input / output unit for exchanging data, addresses and various control signals with the external bus 2, 6 is a built-in ROM for storing programs and data, 7 is a built-in RAM as a memory other than the built-in ROM 6, and 8 is a microcomputer. It is an internal bus that serves as a path for data, addresses, and various control signals between blocks in one. The CPU core 4 is an internal bus
8 to exchange data, address and various control signals
An input / output unit 9, an instruction fetch unit 10 for reading an instruction from each of the memories via the internal bus 8, an instruction decoding unit 11 for decoding the instruction read by the instruction fetch unit 10, and an instruction for this instruction. A control unit 12 that generates a control signal for executing an instruction based on the information of the instruction obtained by the decoding unit 11, an execution unit 13 that executes an operation and the like by the control signal of the control unit 12, and the instruction described above. The program counter 14 indicates the address of the instruction fetched by the fetch unit 10.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0009

[Correction method] Change

[Correction content]

[0009]

A microcomputer 1A according to a first invention outputs to a first address comparator 15 for detecting that the value of the program counter 14 is not an address of the internal ROM 6 and an address bus. A second address comparator 16 for detecting that the stored value is the address of the built-in ROM 6, and the built-in ROM
And an operand access signal line 17 indicating that an address is output to access the other data stored in the memory as an operand, and outputs of the first and second address comparators 15 and 16. Logic gate 18 for inputting a signal and the operand access signal
And the built-in ROM according to the output of the logic gate 18.
When a program stored in a memory other than the built-in ROM is used to access the built-in ROM 6, a data output from the built-in ROM 6 is provided. Invalidate.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction content]

[0021]

According to the first invention, the first address comparator detects that the value of the program counter is not the address of the built-in ROM, and the value output to the address bus is stored in the built-in ROM. A second address comparator for detecting an address, the built-in ROM, and
An operand access signal line indicating that an address is output to access data other than the above stored in the memory as an operand, output signals of the first and second address comparators, and the operand access signal And a built-in ROM read-out prohibiting unit that invalidates the data output from the built-in ROM according to the output of the logic gate. The program is stored in a memory other than the built-in ROM. Built-in RO
If you try to access M, the data output from the built-in ROM will be invalidated.
The contents of can not be taken out easily, and the confidentiality of the microcomputer is improved.

[Procedure Amendment 5]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

Claims (2)

[Claims] 1. An internal ROM, a memory other than that, an instruction fetch unit for reading an instruction from each of the memories via an internal bus, and an instruction decoding unit for decoding the instruction read by the instruction fetch unit. , A control unit for generating a control signal for executing an instruction according to the information of the instruction obtained by the instruction decoding unit, an execution unit for executing an instruction by performing an operation or the like by the control signal of the control unit, and the instruction fetch In a microcomputer provided with a program counter indicating an address of an instruction to be fetched by the unit, a first address comparator for detecting that the value of the program counter is not the address of the built-in ROM, and output to the address bus. A second address comparator that detects that the value is the address of the built-in ROM, and the data stored in the memory. An operand access signal line indicating that an address is output to access the data as an operand, a logic gate for inputting the output signals of the first and second address comparators and the operand access signal, and The built-in RO according to the output of the logic gate
A built-in ROM read prohibition unit that invalidates the data output from M is provided, and when the built-in ROM is accessed by a program stored in a memory other than the built-in ROM, the data output from the built-in ROM is A microcomputer characterized by being disabled. 2. The built-in ROM read prohibition section is configured by inserting a read prohibition logic gate opened and closed based on the output of the logic gate into each data output line of the built-in ROM. The microcomputer according to claim 1.