JPH05265853A - Signal processor - Google Patents

Abstract

PURPOSE:To provide a data memory bank access system capable of speeding up a processing when the signal processor has the two arrangements of two operand inputs. CONSTITUTION:In this signal processor, an arithmetic part 101 shows a logical arithmetic circuit and a multiplication circuit, etc. First and second general-purpose registers 102 and 103 are used as registers for inputting operands to the arithmetic part 101 and as registers for saving/preserving data. A data memory 104 is provided with plural data memory banks. A sub bus 105 is provided with a bus multiplexer 108 to select which one of these sub buses 105 is connected to an internal data bus X106 and an internal data bus Y 107. Therefore, the bank storing the data of two operands can be connected to the sub bus 105 corresponding to the processing, and two operands can be simultaneously accessed in any case.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processor, and more particularly to a method of accessing a data memory bank.

[0002]

2. Description of the Related Art A general signal processor separates a program memory and a data memory due to micro program control, and further performs two-operand simultaneous reading, so that a plurality of independent data memories are used. ,
It has a special architecture to achieve high-speed arithmetic performance, such as having multiple independent data buses.

The periphery of the data memory of the conventional signal processor will be described with reference to the drawings. FIG. 3 is a block diagram of a data memory of a conventional signal processor and its peripherals. In FIG. 3, an arithmetic unit 301 indicates a logical operation circuit, a multiplication circuit, etc. in the case of a signal processor. First general-purpose register 302, second general-purpose register 3
Reference numeral 03 is used as a register for inputting an operand to the arithmetic unit 301 and a register for saving / saving data.
The data memory X304 and the data memory Y305 are
Each has multiple data memory banks.
The buses X306 and Y307 are two internal data buses X and Y for reading two operands simultaneously. The internal data bus X306 is connected to the data memory X304, and the internal data bus Y307 is connected to the data memory Y305.

Thus, in one machine cycle, the bank having the data memory X304 and the data memory Y3
The two operands required for the operation can be read simultaneously from the bank having 05.

[0005]

A general signal processor has an originally required memory mounted in one chip, but the memory capacity in the chip is limited. Therefore, for effective use of memory and high-speed processing, it is necessary to perform a data array that makes the best use of the structure of the data memory based on analysis of operation patterns during programming.

That is, when the two operand inputs to the arithmetic unit 301 are two arrays, the first operand and the data memory Y305 are stored in the data memory X304.
Storing the second operand in the data memory X3
More efficient than storing two operands in 04.

A specific example will be shown. A0-an, b0
The processing shown in FIG. 5 is performed on four types of data, each consisting of n + 1 pieces of bn, c0 to cn, and d0 to dn.

In FIG. 5, processing A of n + 1 loops,
Process B and process C are executed in this order. First, a statistic of the number of simultaneous accesses between two-operand arrays is collected and optimal mapping is performed. In this case, as shown in FIG. 4, a0-an and c0-c are stored in the data memory X304 of FIG.
n, b0 to bn and d0 to d in the data memory Y305
It is optimal to store each n, and the actual program configuration is as shown in FIG.

In FIG. 6, instructions that can be simultaneously executed in one machine cycle are shown in one line. The processing of FIG. 5 is specifically shown in FIG. 6, and processing A, processing B, and processing C are executed in this order.

In the conventional signal processor, the process B in which two operands are stored in the same data memory even if optimal data mapping is performed as shown in FIG. If such a process is included, it becomes impossible to simultaneously access two operands in this part, which causes a problem that the processing time becomes redundant for a signal processor that requires high speed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a signal processor having an access to a data memory bank capable of reducing the processing time in view of the above problems.

[0012]

The structure of the present invention comprises an arithmetic unit, a general-purpose register, a data memory having a plurality of banks, and two internal data buses for simultaneously reading two operands. In the signal processor,
Means for varying the data memory bank connected to the two internal data buses is provided.

[0013]

FIG. 1 is a block diagram of the periphery of a data memory of a signal processor according to an embodiment of the present invention. The description of the same parts in FIG. 1 as in FIG. 3 will be omitted.

In FIG. 1, this embodiment is different from the conventional one in that the data memories 304 and 3 which are independent in the past are used.
05 are placed in one space and each bank
The sub-bus 105 up to the multiplexer 108, and which of the sub-buses 105 are the two internal data buses X1
06, a bus multiplexer 108 for selecting whether to connect to the internal data bus Y107. In this embodiment, there are four data memory banks and four sub buses.

As in the prior art, a0 to an and b0 to b
Consider the processing shown in FIG. 7 with respect to four types of data of n + 1 each of n, c0 to cn, and d0 to dn.

FIG. 7 shows that the process A, the process B, and the process C having the loop n + 1 times are sequentially processed.

In this case, as shown in FIG.
Four types of data of n, b0 to bn, c0 to cn, d0 to dn can be stored in each data memory bank.

Therefore, the actual program is as shown in FIG. In FIG. 8, one line shows instructions that can be executed simultaneously in one machine cycle.

The sub-buses 0, 1, 2, 3 in FIG. 8 correspond to the sub-buses 0, 1, 2, 3 in FIG. In FIG. 8, the ranges of the processes A, B, and C are indicated by arrows.

In the conventional signal processor, the optimum data
Even if mapping is performed, if a process in which two operands are stored in the same data memory is included, it is not possible to simultaneously access two operands for this part. There has been a problem that the processing time becomes redundant for the processor.

However, in the signal processor of this embodiment, the bank storing 2-operand data can be connected to the sub-bus according to the processing, and the 2-operand simultaneous access is possible in any case. The redundancy of can be suppressed. Here, the switching of the sub-bus shown in the above-mentioned flow chart is a short time from the overall processing.

As described above, the signal processor according to the present embodiment can make the data memory banks connected to the two internal data buses variable.
It has a bus and a bus multiplexer.

As described above, the signal of the present embodiment
The processor can reduce the redundant processing and the processing time for the two-operand instruction.

[0024]

According to the conventional signal processor, even if the optimum data mapping is performed from the statistical value of the number of simultaneous accesses of two operands, the processing in which two operands are stored in the same data memory is included. In this case, since it is not possible to simultaneously access two operands in this portion, there has been a problem that the processing time becomes redundant for a signal processor that requires high speed. According to the above, a bank storing 2-operand data can be connected to the sub-bus. In any case, since 2-operand simultaneous access is possible, there is an effect that processing redundancy can be suppressed.

[Brief description of drawings]

FIG. 1 is a block diagram around a data memory of a signal processor according to an embodiment of the present invention.

FIG. 2 is a data mapping diagram for the signal processor of the embodiment of FIG.

FIG. 3 is a block diagram of a data memory of a conventional signal processor and its periphery.

FIG. 4 shows data in the case of a conventional signal processor.
It is a mapping diagram.

FIG. 5 is a flowchart showing conventional data processing.

FIG. 6 is a flowchart showing a specific example of FIG.

FIG. 7 is a flowchart showing data processing according to the embodiment of this invention.

FIG. 8 is a flowchart showing a specific example of FIG.

[Explanation of symbols]

101, 302 operation unit 102, 103, 302, 303 general-purpose register 104 data memory having a plurality of banks 105 sub-bus for each bank 106, 306 internal data bus X 107, 307 internal data bus Y 108 sub-bus Multiplexer A, B, C that selects which of the two is connected to two internal data buses

Claims (1)

[Claims] 1. A signal provided with an arithmetic unit, a general-purpose register, a data memory having a plurality of banks, and two internal data buses for simultaneously reading two operands.
A signal processor, characterized in that, in the processor, means for changing a data memory bank connected to the two internal data buses is provided.