JPH05265713A - Four fundamental rule arithmetic operation unit - Google Patents

Abstract

PURPOSE:To simplify the constitution and also to reduce the cost of an arithmetic unit by combining plural registers into a storage means in order to carry out the four fundamental rule arithmetic operations with a single adder. CONSTITUTION:An adder 6 adds the augend stored in a Z register 2c (Z) to the addend stored in a Y register 2b (Y) in an addition mode. The result of this addition is stored in the register (Z). Meanwhile the adder 6 adds the minuend stored in the register Z to the subtrahend stored in the register Y in a subtraction mode. Then, the result of this addition is stored in the register Z. In a multiplication mode, the adder 6 successively adds together the ORs secured of the bits of the multiplicand stored in an Z register 2a (X) with the multiplier stored in the register Y. The result of this addition is stored in the register Z as the result of multiplication. In a division mode, the adder 6 adds the dividend stored in the register Z and the divisor stored in the register Y. Then, the output of the adder 6 is stored in the register X as the result of division.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a four arithmetic operation device for performing four arithmetic operations of addition, subtraction, multiplication and division on input two numbers.

[0002]

2. Description of the Related Art In some four arithmetic operation devices for performing four arithmetic operations on an inputted two numbers, some arithmetic units are configured by software. In order to perform particularly multiplication and division processing in the arithmetic unit having such a configuration, necessary instruction codes must be stored in advance in the memory, and the instruction code according to the arithmetic mode must be read from the memory to execute the processing. Therefore, there is a problem that the processing time becomes long. Therefore, as shown in FIGS. 11 and 12, there is a four arithmetic operation device in which arithmetic processing is performed by hardware.

The multiplication device shown in FIG. 11 is provided with adders whose number is equal to the bit width by which multiplication is possible.

The arithmetic processing is executed in parallel for each number of bits. For example,

When performing the multiplication process shown in [Formula 1], the multiplier is input to each of the AND gates 50i (i = 1 to n) provided in the preceding stage of the adder in order from the lower bit, and the multiplicand is set. Input by shifting 1 bit at a time,
The outputs of the AND gates 501 and 502 are added in the first-stage adder 601. The addition result of the first-stage adder 601 is input to the next-stage adder 602 together with the output of the third AND gate 503. At this time,
Carry-out Co indicating whether or not there is a carry in adder 601 is input as carry-in Ci of adder 602 at the next stage. In this way, the adder 60i (i = 2 to n
By adding the addition result of the previous stage adder in 1), the output of the final addition adder 60n-1 can be obtained as the multiplication result.

[0005]

[Equation 1]

Further, as shown in FIG. 12, the dividing device adds an adder corresponding to the number of bit widths of the divisor.

This divider is provided with a calculator, for example,

In the case of performing the division shown in Equation 2, the adder 70i (i
= 1 to n) in order from the highest digit of the multiplicand, and the 2's complement of the divisor or the divisor itself,
The most significant bit of the addition result in each adder is inverted to obtain the division result. In this case, in the adders after the second-stage adder 702, the most significant bit of the addition result in the previous-stage adder is set to the EXNOR gate 80.
i (i = 1 to n-1) is input together with the divisor, and it is selected whether the divisor is used as the input of the adder or the two's complement of the divisor is used.

[0008]

[Equation 2]

[0009]

However, in the above-mentioned conventional four arithmetic unit, an adder corresponding to the number of bits of the multiplicand and the dividend is required in multiplication and division, and the circuit configuration becomes complicated and large in size. There was a problem that caused an increase in cost.

An object of the present invention is to provide a four arithmetic operation device capable of executing all four arithmetic operations by a single adder, simplifying the configuration of the device, and realizing cost reduction. is there.

[0011]

A four arithmetic operation device of the present invention stores designation means for designating an operation mode of addition, subtraction, multiplication or division, and a multiplicand in a multiplication mode or a division result in a division mode. And a second storage means for storing an addend in the addition mode, a subtraction in the subtraction mode, a multiplier in the multiplication mode, or a divisor in the division mode, and an augend and an addition result in the addition mode, and subtraction. Third storage means for storing a dividend and a subtraction result in the mode, a multiplication result in the multiplication mode, or a dividend in the division mode;
A single adder that is connected to the third storage means and adds the data stored in each storage means.

[0012]

In the present invention, in the addition mode, the augend stored in the third storage means and the addend stored in the second storage means are added in the adder, and the addition result is the third addition result. Is stored in the storage means. In the subtraction mode, the minuend stored in the third storage means and the subtraction stored in the second storage means are added in the adder, and the addition result is the second addition result.
Is stored in the storage means.

In the multiplication mode, the logical sum of the multiplicand stored in the first storage means and each bit of the multiplier stored in the second storage means is sequentially added in the adder, and the addition result is the multiplication result. It is stored in the third storage means.
Further, in the subtraction mode, the multiplicand stored in the third storage means and the divisor stored in the second storage means are added in the adder, and the output of this adder is stored in the first storage means as the division result. Remembered. Therefore, each operation mode of addition, subtraction, multiplication and division is executed by a single adder.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing the configuration of a four arithmetic unit according to an embodiment of the present invention. The four arithmetic units 1 are X, Y,
It has three Z registers 2a to 2c. The X register 2a is the first storage means of the present invention, and stores the multiplicand in the multiplication mode or the division result in the division mode. The Y register 2b is the second storage means of the present invention, and stores the addend in the addition mode, the subtraction in the subtraction mode, the multiplier in the multiplication mode, or the divisor in the division mode. The Z register 2c is the third storage means of the present invention, and stores the augend and addition result in the addition mode, the subtraction and subtraction result in the subtraction mode, the multiplication result in the multiplication mode, or the dividend in the division mode.

The X register 2a is selectively supplied via the selector 3 to each of the AND gates 4a to 4h as one input. The AND gates 4a to 4h are provided in correspondence with the number of bits that can be calculated in the four arithmetic unit 1. Further, the selector 3 opens and closes according to the switching signal SW3 set when the arithmetic mode is selected, and in the closed state, the selector input Si which is the output of the X register 2a.
Is the selector output So, and when it is opened, the selector output So
The value of is 1.

The data stored in the Y register 2b is E
It is supplied as one input to each of the XNOR gates 5a to 5h. The EXNOR gates 5a-5h are AN
Similar to the D gates 4a to 4h, they are provided corresponding to the number of bits operated in the four arithmetic operation device 1, and the output thereof is the other input of the AND gates 4a to 4h. The AND gates 4a to 4h take the logical product of the selector output So of the selector 3 and the outputs of the EXNOR gates 5a to 5h, and input the result to the adder 6. The storage content of the Z register 2c is input to the adder 6. The adder 6 stores the contents stored in the Z register 2c and the AND gates 4a to 4
The output of h is added, and the addition result is input to the Z register 2c.

The output signal of the most significant bit of the output of the adder 6 is input to the X register 2a, and
It is input to the D terminal of the flip-flop 7. The flip-flop 7 has a Q according to the states of the set terminal and the reset terminal set by the switching signals SW1 and SW2.
The output is supplied as the other input of the EXNOR gates 5a to 5h. The Qbar output is input to the adder 6 as carry-in Ci. The X register 2a has a switching signal SW4 set when the arithmetic mode is selected.
Is input, and it is determined whether to store the output signal of the most significant bit of the adder 6 according to the switching signal SW4.

FIG. 2 is a diagram showing a setting state of the switching signal in each mode in the above four arithmetic operation device. As shown in the figure, in the addition mode, the switching signal S
Only W1 is set to "1" and the remaining switching signal SW2
~ SW4 is set to "0".

When the switching signal SW1 is set to "1" and the switching signal SW2 is set to "0", the Q output of the flip-flop 7 is always "1". Also,
The selector 3 is opened because the switching signal SW3 is "0", and the selector output So becomes "1". Further, by setting the switching signal SW4 to "0", the register input Ri of the X register 2a, which is the output of the most significant bit of the adder 6, is invalidated.

In the subtraction mode, the switching signal S
By inverting W1 and SW2, the Q output of the flip-flop 7 is always "0". The selector 3 and the X register 2a are the same as in the addition mode. In the division mode, the Q output of the flip-flop 7 is always "1" as in the addition mode, and the switching signal SW3
Is "1", the selector 3 is closed and its selector output So becomes the value of the selector input Si. The state of the X register 2a is similar to the addition mode and the subtraction mode.

In the division mode, the switching signal SW
Since both 1 and SW2 are set to "1", the Q output of the flip-flop 7 becomes the content of the D input. The state of the selector 3 is similar to the states of the addition mode and the subtraction mode, and the selector output So thereof is always "1". In addition, since the X register 2a is set to the switching signal SW4 "1", it validates the register input Ri and stores it.

When the addition arithmetic processing is performed using the four arithmetic operation device configured as described above, the augend is set in the Z register 2c and the addend is set in the Y register 2b. At the same time, the switching signals SW1 to SW4 are set to the state shown in FIG. As a result, the EXNOR gate 5
Since the Q output of the flip-flop 7 input to each of a to 5h and the selector output So of the selector 3 input to the AND gates 4a to 4h are both "1",
The addend set in the Y register 2b is input to the adder 6 as it is, added with the augend set in the Z register 2c, and the addition result is stored in the Z register 2c.

In the subtraction mode, the minuend is Z register 2
c, and the decrement is set in the Y register 2b. At the same time, the switching signals SW1 to SW4 are set to the state shown in FIG. Therefore, the AND gate 4a
The selector output So input to ~ 4h is "1", but the Q output of the flip-flop 7 input to the EXNOR gates 5a to 5h becomes "0", and the subtraction set in the Y register 2b is set for each bit. Is output from the EXNOR gates 5a to 5h and input to the adder 6.
Therefore, the adder 6 adds the subtrahend set in the Z register 2c and the two's complement of the subtrahend set in the Y register 2b, and as a result, the value obtained by subtracting the subtrahend from the subtrahend is stored in the Z register 2c. ..

FIG. 3 shows the processing in the multiplication mode using the above four arithmetic unit 1. To start the operation in the multiplication mode, first, all of the registers 2a to 2c are once cleared, and the switching signals SW1 and SW2 are set to "1" and "0", respectively, and the Q output of the flip-flop 7 is fixed to "1". After that, the switching signal SW3 is set to "1" to close the selector 3 and the selector output So is used as the selector input Si (n1). Next, a multiplier is set in the X register 2a and a multiplicand is set in the Y register 2b (n
2).

In this state, for example, the above-mentioned

When performing the multiplication process shown in [Formula 1], the X register 2
The multiplier "1001" set in a is input to the AND gates 4a to 4h one by one in order from the least significant bit through the selector 3, and the multiplicand "1101" set in the Y register 2b is 1 bit. EXNO
AND gate 4 via each of R gates 5a-5d
a to 4d. Now, since the least significant bit of the multiplier "1001" set in the X register 2a is "1", the multiplicand "1101" is directly input to the adder 6 via the AND gates 4a to 4d and is in the clear state. It is added to the contents of the Z register 2c as it is. Therefore, the output of the adder 6 becomes "1101" and is stored in the Z register 2c in this state. (N3-n5).

Next, the value set in the Y register 2b is shifted to the left (upper side) by 1 bit (n6). The multiplicand shifted in this way is transferred to the EXNOR gates 5b ...
Input to the AND gates 4b to 4e via 5e. At this time, the data “0” of the second least significant bit stored in the X register 2a is input to the AND gates 4b to 4e through the selector 3 and the adder 6 receives the AN signal.
As an output of the D gates 4b to 4e, "0000" is input in a state of being shifted left by one bit. This data is Z
It is added to "1101" stored in the register 2c and stored again in the Z register 2c.

As described above, each bit of the multiplier is ANDed with the multiplicand, and the result is obtained in the Z register 2c.
Process of adding the previous addition result stored in (n3
~ N6) is repeated. This allows the Z register 2
Finally, the result of multiplication of the multiplicand and the multiplier is stored in c.

FIG. 4 shows a processing procedure in the division mode using the above four arithmetic unit 1. When the arithmetic processing in the division mode is started, the registers 2a to 2c are first cleared and the switching signal SW3 is set to "0" to open the selector 3 (n11).

As a result, the selector output S of the selector 3
o is always set to "1". Next, the dividend is set in the Z register 2c and the divisor is set in the Y register 2b (n1
2).

For example, the above-mentioned

When the division operation shown in Equation 2 is performed, "011010" is set in the Z register 2c and "011" is set in the Y register 2b. Then, the value of the divisor 011 set in the Y register 2b and the Q of the flip-flop 7 are set.
EXNOR gate 5
The outputs a to 5c are input to the adder 6 via the AND gates 4a to 4c.

On the other hand, the upper 3 of the dividend from the Z register 2c
Input the bit data “011” to the adder 6 and perform AND
It is added to the outputs of the gates 4a to 4c (n14). In the division mode, the switching signal SW as shown in FIG.
Since both 1 and SW2 are "1", the Q output of the flip-flop 7 becomes the value of the D input. When the arithmetic processing is started, the outputs of the adder 6 are all "0", and the EXNO
The Q output input to the R gates 5a to 5h is "0".

Therefore, in the first processing of n13, the outputs of EXNORs 5a to 5c become the two's complement "101" of the divisor "011" set in the Y register 2B, and the adder 6 outputs the data "011" of the upper 3 bits of the dividend. "And the two's complement of the divisor" 101 "are added, and the data of the most significant bit of the output of the adder 6 which is the addition result is stored in the X register 2a (n14). The data of the most significant bit of the output of the adder 6 is D of the flip-flop 7.
Input to the terminal.

The processing of n13 and n14 is sequentially executed by using the data of the lower two digits of the addition result of the preceding stage and the data of the digit next to the dividend. EXNOR in each addition processing
The outputs from the gates 5a to 5c change according to the contents of the most significant bit of the previous addition result. That is, when the most significant bit in the previous addition result is "0", the two's complement "101" of the divisor is input to the adder 6, and the most significant bit of the previous addition result is "1". In this case, the divisor “011” is directly input to the adder 6. In this way, the most significant bit of each addition result is sequentially set to the X register 2a.
, And the data stored in the X register 2a can be inverted to obtain the division result. At the time of this inversion, since the X register 2a is composed of a plurality of flip-flops as is well known, it can be easily obtained by taking out the Qbar output from each flip-flop.

As described above, according to this embodiment, the contents set in the registers 2a to 2c in each operation mode are changed and the switching signals SW1 to SW4 are set as shown in FIG. Adder 6
Can be used to perform all four arithmetic operations.

FIG. 5 is a block diagram showing the configuration of a fuzzy inference device using the above four arithmetic operations device. The fuzzy inference apparatus 11 includes a ROM 12 for storing fuzzy rules and membership functions, a RAM 13 for temporarily storing results of operations using the fuzzy rules and membership functions,
An input / output unit 14 for inputting input data that constitutes a conditional unit of a fuzzy rule, and an input / output unit 14 for outputting an inference result. A four arithmetic unit 15 for performing arithmetic processing related to fuzzy inference and a sequence control circuit for controlling sequential processing related to fuzzy inference. 1
6 and 6. Of these, the four arithmetic operations section 15
Is configured by the four arithmetic operation device of the present invention.

FIG. 6 is a diagram showing a conditional part membership function used for fuzzy inference in the fuzzy inference apparatus. As shown in the figure, the conditional part membership function has a triangular shape, and the goodness of fit Y for each label is represented by the minimum coordinate value and slope of each membership function. That is, the goodness of fit Y of the input data is given by Y = (PI-Pm) × Am. The processing procedure for calculating the goodness of fit Y is shown in FIG.
Shown in. When the input of the input data PI is accepted (n2
1), the label to which this input PI belongs is searched (n
22-n25). RAM for searching this label
Counter m allocated to 13 predetermined memory areas
Is used to compare the value of the input data PI with the coordinate Pm of each label, and the label when the value of the input PI exceeds the coordinate data Pm is set as the compatible label.

After that, using the above-mentioned arithmetic device 1 for four rules, first, in the arithmetic expression of the compatibility Y, (PI-Pm) is calculated. That is, the value of the input PI is set in the Z register 2c shown in FIG. 1, the value of the intersection position Pm with the input axis on the left side of the label to which the input PI corresponds is set in the Y register 2b, and the switching signals SW1 to SW4 are set. The subtraction mode shown in FIG. 2 is set to the state, and the above-described subtraction mode arithmetic processing is executed (n27). Then, the Y register 2b
The inclination Am of the label corresponding to is read out from the ROM 12 and set, and the X register 2a stores (PI-Pm)
Set the contents of the Z register 2c which is the subtraction result of (n
27). Using the X register 2a and the Y register 2b, the adder 6 executes the arithmetic processing for multiplying the gradient Am (n28, n29). Through the above processing, the conformance degree Y of the input data PI in the condition part is obtained.

FIG. 8 is a diagram showing a singleton of the conclusion part used for the fuzzy inference in the fuzzy inference apparatus 11. FIG. 9 shows a processing procedure for obtaining a definite value of fuzzy inference by calculating the centroid value from the goodness of fit y of the conditional part using this singleton. The center of gravity G in the singleton shown in FIG. 8 is obtained by G = (ΣXY) / ΣY. Therefore, in the calculation of the center of gravity, RA
In the register B assigned to M13, the height ym of each singleton is sequentially added. Then, the X register 2a
Set the coordinate value xm of the singleton to Y register 2b
The height ym is set to (n32). This X register 2a
And the Y register 2b are used to perform x × y multiplication, and the multiplication result is stored in the Z register 2c (n33). This n3
The processes 1 to n33 are executed for all singletons (n34, n35).

At this time, by setting only the x and y values for each singleton in the X register 2a and the Y register 2b, the operation result of Σx × y for each singleton is cumulatively stored in the Z register 2c. You can go. That is, in the process of x × y in each singleton, the logical product operation with the multiplicand is performed in order from the least significant bit of the multiplier, and the logical product operation result of each bit is added in the Z register 2c. The multiplication result is stored in the Z register 2c, and the contents of the Z register 2c in which the previous multiplication result is stored in the multiplication process for the next singleton also include:
Σxy can be obtained by sequentially adding the bitwise logical product results of the multipliers in this multiplication process.

In the above processing, the value of Σy is the RAM 13
The value of Σxy stored in the register B in the Z register 2
stored in c. Next, a calculation for obtaining the reception G is performed using this stored content. That is, the storage content of the register B is set in the Y register 2b (n36), and the dividend already stored in the Z register 2c in the calculation process of Σxy is set to Y.
Divide by the value of register 2b. The most significant bit MSB (Z / Y) in this division result is stored in the X register 2a (n37). The value obtained by inverting the value stored in the X register 2a as the result of this division becomes the value of the center of gravity G which is the inference result of the fuzzy inference.

As described above, according to this embodiment, the four arithmetic operations device 16 of the present invention can be used in the four arithmetic operations unit 16 to execute fuzzy inference. As described above, by using the four arithmetic operations device 1 of the present invention as a part of the fuzzy inference device 11, the configuration of the fuzzy inference device 11 is simplified,
There is an advantage that space saving and cost reduction can be realized. Further, since the multiplication process and the division process have a small influence on the circuit board having the bit width, it is easy to estimate the circuit scale before designing, and there is an advantage that an estimation difference is unlikely to occur.

[0042]

According to the present invention, since all four arithmetic operations can be executed by a single adder, it is necessary to use an adder for multiplier and divisor bits in multiplication and division operations. Compared with the arithmetic device, the configuration can be extremely simplified, and there is an advantage that the device can be downsized and the cost can be reduced. In addition, there is little influence that the bit width in the multiplication / division operation has on the circuit scale, and there is an advantage that the circuit scale can be easily estimated at the time of design.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a four arithmetic operation device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a setting state of a switching signal in each arithmetic mode in the same four arithmetic operation device.

FIG. 3 is a flowchart showing a processing procedure of a multiplication mode in the four arithmetic operation device.

FIG. 4 is a flowchart showing a processing procedure of a division mode in the arithmetic device of the same four rules.

FIG. 5 is a diagram showing a configuration of a fuzzy inference device using the same four arithmetic operation device.

FIG. 6 is a diagram showing a condition part membership function used for fuzzy inference in the fuzzy inference apparatus.

FIG. 7 is a flowchart showing a procedure for calculating a degree of belonging to a conditional part in the fuzzy inference apparatus.

FIG. 8 is a diagram showing a conclusion part singleton used for fuzzy inference in the fuzzy inference apparatus.

FIG. 9 is a flowchart showing a procedure of a centroid value calculation processing in the fuzzy inference apparatus.

FIG. 10 is a diagram showing a configuration of a multiplication processing unit in a conventional four arithmetic operation device.

FIG. 11 is a diagram showing a configuration of a division processing unit of the conventional four arithmetic operation device.

[Explanation of symbols]

 1-Four arithmetic operation device 2a-X register (first storage means) 2b-Y register (second storage means) 2c-Z register (third storage means) 3-Selector (designating means) 6-Adder 7 -Flip-flop (designating means)

Claims (1)

[Claims] 1. Designating means for designating an operation mode of addition, subtraction, multiplication or division; first storage means for storing a multiplicand in a multiplication mode or a division result in a division mode; and addition in an addition mode. Second storage means for storing a number, a subtraction in the subtraction mode, a multiplier in the multiplication mode, or a divisor in the division mode, and an augend and an addition result in the addition mode, a subtraction and subtraction result in the subtraction mode, and a multiplication result in the multiplication mode. , Or a third storage means for storing the dividend in the division mode, and a single adder connected to the first to third storage means and adding the data stored in each storage means. A four arithmetic unit characterized by the above.