JPH05260417A - Drive circuit for liquid crystal matrix display device - Google Patents

Abstract

PURPOSE:To facilitate the circuit integration by providing an N-bit shift register, N-sets of M(2M<=J)-bit latch circuit, M-sets of voltage sources, a switch circuit and a summing amplifier circuit adding voltages. CONSTITUTION:An N-bit shift register 1 shifts picture data D1 inputted from a picture data input terminal T11 synchronously with a clock CK from a clock terminal T12. Picture data D1-DM are respectively stored in N-sets of M-bit (2M<=J, a binary bit number corresponding to a gradation number J) latch circuits 21-2N. Switch circuits S311-S3NM are switched by a latch pulse PL from a latch input terminal T21 to select and output voltages V1-VM of power supply lines C1-CM corresponding to the data. Then summing characteristics 41-4M add the data and the result is outputted as data drive outputs V01-V0M.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for a liquid crystal matrix type display device, and more particularly to a drive circuit for a liquid crystal matrix type display device which performs gradation display.

[0002]

2. Description of the Related Art Generally, in a liquid crystal matrix type display device, when gradation display of brightness is performed, it is necessary to apply a drive output voltage corresponding to the brightness to a data line.

In the conventional drive circuit for a liquid crystal matrix type display device of this type, as shown in FIG. 3, image data DI inputted from an image data input terminal T71 is supplied to a clock terminal T.
N-stage M that shifts in synchronization with the clock CK from 72
Shift register group 7 including bit shift registers 71 to 7N, and corresponding N M-bit latch circuits 81
Latch circuit group 8 including 1 to 81N, and selector circuit 9
It was equipped with and. The selector circuit 9 includes selectors 911 to 91N and transistors Q11 to QJ1, Q12 to QJ2, ...
Transistor groups 921 to 92N composed of Q1N to QJN
It was equipped with and. The drains of the J transistors in the transistor group are connected to the power source line terminals T911 to T9 of the voltages V1 to VJ corresponding to the J gradations, respectively.
It is connected to 1J. And J of each transistor group
The sources of the individual transistors are commonly connected,
They are connected to the corresponding output terminals T921 to T92N. Here, N is the number of data lines, J is the number of gradations, M is the number of binary bits corresponding to the number of gradations J, that is, 2 ^M
≦ J.

Next, the operation of the conventional drive circuit for a liquid crystal matrix type display device will be described.

First, M-bit digital image input data DI represented by J gradation is input from the image input terminal T71 of the shift register group 7. Next, the clock terminal T72
Image input data D by the clock CK input from
I is sequentially transferred to the shift registers 71 to 7N, which are M-bit shift register groups. Next, the latch input terminal T
By the latch pulse PL input from 81, the image data D1 to D stored in the shift registers 71 to 7N
N is transferred to the corresponding latch circuits 811 to 81N, respectively.

Next, the latched image data L1 to LN held in the latch circuits 811 to 81N are input to the corresponding selectors 911 to 91N of the selector circuit 9. The selectors 911 to 91N select the transistors corresponding to the M-bit input data value of the respective transistor groups and make them conductive. For example, selector 9
In the case of 11, for example, Q11 of the transistors Q11 to QJ1 is selected and made conductive. Therefore, in this case, the voltage V1 is selected and output to the output terminal T921 as the output voltage VO1 for driving the data line.

The conventional liquid crystal matrix type display device of this type generally has a pixel number of 640 × 400 and a gradation number of about 8. 2. Description of the Related Art In recent years, liquid crystal matrix type display devices are capable of high-definition and multicolor display, and therefore the number of required gradations tends to increase. For example, for full-color display, the required number of gradations is about 256. Become.

However, in the conventional drive circuit for a liquid crystal matrix type display device, the number of output transistors increases in proportion to the number of gradations J. For example, if the number of data output lines is 12
When the number of gradations is 0 and the number of gradations is 256, the number of required output transistors is 30720. Since the output transistor reduces the output ON resistance, the required chip area becomes larger than that of the transistor for the logic circuit. Also, the number of corresponding selectors is the same as the number of gradations, that is, 256 are required, and the number of selector output lines is also required to be 256.

Further, a circuit for supplying 256 voltage levels corresponding to 256 gradations also needs to have a low impedance because these voltages are directly applied as output signals. The number of input terminals is also required to be 256 or more.

[0010]

In the above-mentioned conventional drive circuit for a liquid crystal matrix type display device, the number of output transistors, the number of selectors and the number of output lines thereof increase in proportion to the number of gradations. Since the chip size becomes extremely large, there is a drawback that it is difficult to form an IC. In addition, a circuit that supplies a number of voltage levels corresponding to the number of gradations needs to have low impedance because these voltages are directly applied as output signals, and the circuit configuration is difficult when the number of input terminals is increased. There was a drawback.

[0011]

According to the drive circuit for a liquid crystal matrix type display device of the present invention, a data line of a liquid crystal matrix type display device in which N data lines and scanning lines are arranged orthogonal to each other is used. In a drive circuit for a liquid crystal matrix type display device for applying a data output corresponding to each gradation, an N-bit shift register for sequentially shifting a data signal in synchronization with a shift clock, and image data controlled by the data signal. N Ms (2 ^M ≤ J) that store
A combination of a bit latch circuit, M voltage sources having different voltages, and the M voltage sources corresponding to the data signals held in the N latch circuits is selected to select a first and second combination. A switch circuit that outputs a voltage,
And a summing amplifier circuit for summing the first and second voltages.

[0012]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a drive circuit for a liquid crystal matrix type display device of the present invention.

As shown in FIG. 1, the liquid crystal matrix type display device driving circuit of the present embodiment has an image data input terminal T1.
Image data DI input from the clock terminal T12
N-bit shift register 1 that shifts in synchronization with the clock CK from
2N latch circuit group 2 and latch circuits 21 to 2N
Controlled by the power supply lines C1 to V1 of voltages V1 to VM, respectively.
N sets of M switch circuits S311 to S3 for switching CMs
1M, S321 to S32M, ... S3N1 to S3NM switch circuit group 3 and N summing amplification circuits 41 to 4
And a summing amplifier circuit group 4 of N. The addition amplification circuit 41 is configured to include an operational amplifier O41 and resistors R411 to 41M and R41F. The other addition amplification circuits 42 to 4N have the same configuration. Here, N is the number of data lines, M is the number of binary bits corresponding to the number of gradations J, that is, 2 ^M ≤J.

Next, the operation of this embodiment will be described.

FIG. 2 is a time chart of the circuit of this embodiment shown in FIG.

First, the input data DI is input from the image input terminal T11 of the shift register 1. Next, the input data DI is sequentially shifted by the shift register 1 by the clock CK input from the clock terminal T12,
It is transferred to the latch circuit group 2 as a latch circuit control signal. Next, in the latch circuit group 2, the shift register 1
When the bit value corresponding to each of the latch circuits 21 to 2N is “1”, the image data D1 to DM are stored.

Next, the latched image data L1 to LN held in the latch circuits 811 to 81N are transferred to the switch circuit group 3 as the switch control signal by the latch pulse PL input from the latch input terminal T21. .. In the switch circuit group 3, the latch image data L
1 to LN are corresponding switch circuits S311 to S31
M, S321 to S32M, ... S3N1 to S3NM are opened and closed, and the voltage V1 of the power supply lines C1 to CM corresponding to the data is set.
~ VM is selected and output.

For example, the first data of the data input to the switch circuits S311 to S31M corresponding to the latch circuit 21.
If ~ 3 bits are "1", S311 to S313 are turned on and voltages V1 to V3 are output.

Each set of switch circuits S of the switch circuit group 3
311 to S31M, S321 to S32M, ... S3N1
The respective voltages output from S3NM are input to the respective addition amplification circuits 41 to 4N of the addition amplification circuit group 4. For example, the above switch circuits S311 to S31M
The voltages V1 to V3 from are input to the summing amplifier circuit 41, and the operational amplifier A41 and the resistors R411 to R413 and R4.
It is added by the addition amplifier circuit including 1F and output as the data line drive output VO1. The data line drive outputs VO2 to VOM are similarly generated and output. The voltage VR is the reference voltage of the operational amplifier A41.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made. For example, a transfer gate may be used as a switch element of a switch circuit, and a resistance element may be formed of a high-resistance wiring such as polysilicon to facilitate IC implementation without departing from the gist of the present invention. Of course.

[0022]

As described above, the drive circuit for a liquid crystal matrix type display device of the present invention comprises an N-bit shift register and N M (2 ^M ≤J) -bit latch circuits for storing image data. Grayscale by providing M voltage sources, a switch circuit that selects a combination of corresponding voltage sources according to the data signals held in N latch circuits, and an addition amplification circuit that adds voltages. As the number increases, the number of output transistors, the number of selectors, the number of output lines thereof, and the like can be significantly reduced as compared with the related art, so that the increase in chip size can be suppressed and the IC can be easily manufactured. There is. Also, a circuit that supplies a voltage level corresponding to the number of gradations does not need to have a low impedance because these voltages are not directly applied as an output signal, and the number of input terminals can be reduced as compared with the conventional circuit so that the circuit configuration is easy. The effect is that

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a drive circuit for a liquid crystal matrix type display device of the present invention.

FIG. 2 is a time chart showing an example of the operation of the drive circuit for the liquid crystal matrix type display device of the present embodiment.

FIG. 3 is a block diagram showing an example of a conventional drive circuit for a liquid crystal matrix display device.

[Explanation of symbols]

1, 71 to 7N shift register 2, 8 latch circuit group 3 switch circuit group 4 addition amplification circuit group 7 shift register group 9 selector circuit 21 to 2N, 81 to 8N latch circuit 41 to 4N addition amplification circuit 911 to 91N selector 921 to 921 92N transistor group O41 to 04N operational amplifier Q11 to QJ1, Q12 to QJ2, ... Q1N to QJN
Transistors R411 to R41M, R41F, R321 to R32M,
R42F, ... R3N1 to R3NM, R42F resistors S311 to S31M, S321 to S32M, ... S3N1
~ S3NM switch circuit

Claims (2)

[Claims] 1. A liquid crystal matrix display in which data outputs respectively corresponding to J gradations are applied to the data lines of a liquid crystal matrix display device in which N data lines and scanning lines are arranged orthogonally to each other. In an apparatus drive circuit, an N-bit shift register that sequentially shifts a data signal in synchronization with a shift clock, and an N-bit control register that stores image data controlled by the data signal.
A combination of M (2 ^M ≦ J) bit latch circuits, M voltage sources having different voltages, and M voltage sources corresponding to the data signals held in the N latch circuits. 2. A drive circuit for a liquid crystal matrix type display device, comprising: a switch circuit for selecting and outputting a first voltage and a second voltage; and a summing amplifier circuit for adding the first and second voltages. 2. The drive for a liquid crystal matrix display device according to claim 1, wherein the switch circuit includes a transfer gate as a switch element, and the summing amplifier circuit includes a resistance element formed of a wiring of polysilicon. circuit.