JPH05260350A - Automatic equalizer - Google Patents

Abstract

PURPOSE:To reduce the cost of the automatic equalizer by reducing the scale of an equalization circuit in the automatic equalizer which eliminates linear distortion of a signal resulting from orthogonal-modulating a video signal and a digital data signal with a symbol period T. CONSTITUTION:An equalizer circuit 14 consists of series connection of an I axis use transversal filter whose tap interval is T/2, a Q axis use short transversal filter whose tap interval is T/2, and a Q axis use transversal filter whose tap interval is T. A CPU 23 employs a RAM 21 and a ROM 22 and implements correlation calculation and tap coefficient correction calculation or the like based on signals before and after I axis waveform equalization and on signals before and after Q axis waveform equalization to correct the tap coefficient of the equalization circuit 14. A digital data signal whose linear distortion is eliminated is outputted from the equalization circuit 14 by implementing the operation above for a prescribed number of times.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention transmits a video signal and a digital data signal having a symbol period T by quadrature modulation,
The present invention relates to an automatic equalizer that obtains a desired digital data signal by automatically removing linear distortion such as ghost that occurs during transmission on the receiving side.

[0002]

2. Description of the Related Art In recent years, attempts have been made to transmit a television signal by modulating a digital signal on a quadrature axis in a band of 1 MHz or less where the television signal is transmitted in both sidebands and multiplexing it with a video signal. This situation is described in Reference 1 (Patent Publication, Japanese Patent Laid-Open No. 2-
156786).

Normally, linear distortion such as ghost occurs in the transmission system. FIG. 10 shows the phase relationship between the digital multiplexed signal (m) after band shaping and the video signal (v). In addition,
There is a ghost with delay time τ seconds and intensity g. As shown in this figure, the video signal (v) is on the in-phase (I) axis,
Digital multiplexed signals (m) are present on the orthogonal (Q) axis.

By the way, the amplitudes of the ghost components m'and v'of the digital multiplex signal (m) and the video signal (v) are g.
Double. The phases of these signals are rotated from the main signal by a phase φ determined by the delay time τ and the RF carrier frequency. Therefore, the signal component SQ appearing in the Q-axis direction is given by the equation (1). SQ = m + gmcosφ + gvsinφ (1) where the first term is the main signal component of the desired digital multiplex signal, the second term is the ghost component of the digital multiplex signal, and the third term is the leakage ghost component of the video signal. is there. The period T of the digital multiplexed signal (m) is T = 10 / (4fsc) = 0.698 [μs] (2). Where fsc is the frequency of the color subcarrier and is 3.57
It is 9545 MHz.

As disclosed in Document 2 (“Noda et al.,“ Digital audio multiplex system and compatibility for current NTSC television broadcasting ”, Journal of Television Society, Vol. 42, No. 9, 1988), The level of the multiplexed signal needs to be lower than the level of the video signal by about 32 dB. This is to reduce interference with a general television receiver. Therefore, the leakage ghost component of the video signal superimposed on the digital multiplex signal, that is, the third term in the equation (1), is easily larger than the main signal component of the digital multiplex signal.

On the other hand, the signal component SI appearing in the I-axis direction is expressed by the equation (3). SI = v + gvcosφ−gmsinφ (3) Here, the first term is the main signal component of the video signal, the second term is the ghost component of the video signal, and the third term is the leakage ghost component of the digital multiplex signal.

The automatic equalizer reproduces an undistorted digital multiplexed signal by removing the second and third terms of the equation (1). Hereinafter, the configuration and operation of a conventional automatic equalizer will be described with reference to the drawings.

FIG. 11 is a diagram showing the structure of a conventional automatic equalizer. In this figure, the I-axis signal component is supplied to an A / D (analog / digital) converter 11 for 10-bit processing via a terminal 10. Further, the Q-axis signal component is supplied to the A / D converter 13 for 10-bit processing via the terminal 12. The digital signals output from the A / D converters 11 and 13 are both supplied to the equalization circuit 27.

The output of the A / D converter 11 is also supplied to the I-axis input waveform memory 17. Further, the signal equalized by the I-axis signal component in the equalization circuit 27 is supplied to the I-axis output waveform memory 19. In addition, the Q-axis signal components before and after the equalization process are supplied to the Q-axis input / output waveform memories 18 and 20, respectively.

By the way, the CPU 23 and each waveform memory 17-
20, tap coefficient memory 16, RAM 21, ROM 22
And are connected by a data bus and an address bus. C
The PU 23 uses the RAM 21 in accordance with a program stored in advance in the ROM 22 to perform correlation calculation, tap coefficient correction calculation, etc. on the I-axis and Q-axis signal components.
Then, the obtained tap coefficient is supplied to the equalization circuit 27 via the tap coefficient memory 16. The equalization circuit 27 performs waveform equalization processing based on the supplied tap coefficient.

A normal video signal is supplied to the timing signal generation circuit 28, and a clock C having a cycle T / 2 is supplied.
K and various timing signals are generated and supplied to each circuit.

The reference signal required for waveform equalization is shown in FIG. FIG. 12A shows a reference signal for removing the leaked and crowded component of the video signal. This is a GCR (Ghost Caching) already inserted in the 18th and 281th lines of the broadcast wave.
ncell Reference) signal. Details of this are described in Reference 3 (Sugimori, "EDTV Technology in Broadcasting Stations", Journal of the Television Society, Vol.43, No.5, 1989) and the like. Incidentally, the ghost removal delay time range when using the GCR signal is 44.
7 [μs]. The digital multiplexed signal is shown in FIG.
As shown in (b), it is multiplexed in the part excluding the GCR signal and the previous line. In this case, the reference signal for removing the ghost component of the digital multiplex signal is the data itself of the digital multiplex signal. It should be noted that, as described above, blocking the digital multiplex signal within a predetermined range within the vertical retrace feedback is disclosed in Document 1.

Next, the configuration of the equalization circuit 27 will be described with reference to FIG. The output of the I-axis A / D converter 11 is supplied to a transversal filter (TF) 31. The TF 31 operates at the clock CK, that is, the cycle T / 2. The structure of this TF31 is shown in FIG.

The signal supplied in FIG.
Is supplied to a group of 128 latches 41 connected in series via. A clock CK (not shown) is applied to each of the latch groups 41, and a signal delayed every T / 2 seconds is applied to each of the 128 multiplier groups 42. The multiplier group 42 has tap coefficients of CI, -6 to CI, respectively.
121 coefficients are provided. The number of bits of this tap coefficient is 4 (Iga, and et al, “Ghost Clean System,
“IEEE Trans.on CE, Vol.36, No.9, Nov.1990) is 10 or more. 128 of multiplier group 42
The individual output signals are added by the adder 43 and output from the terminal 46. That is, TF31 has a tap interval T / 2 of 12
It is an 8-tap TF. Here, the tap interval T / 2 is T / 2 = 5 / (4fsc) = 0.349 [μs] (4). Therefore, 1 with a tap coefficient of CI, -6 to CI, 121
The 28-tap TF31 is -2.1 to 42.3 [μs].
Has a ghost removal delay time range of.

On the other hand, the output of the A / D converter 13 for the Q axis is added to the delay circuit 33 via the terminal 32. Delay circuit 3
Reference numeral 3 is composed of 6 latches to which a clock CK (not shown) is added, and a delay of 6 * (T / 2) is performed. The TF 31 output and the delay circuit 33 output are added by the adder 34. As a result, the leaked ghost component of the video signal including the previous ghost is removed. The output of the adder 34 is T
It is supplied to F38. The TF 38 has a 128-tap configuration with the same tap interval T / 2 as the TF 31. The TF 38 removes the ghost component of the digital multiplex signal. Here, the tap coefficient of the TF 38 is expressed as CQ, -6 to CQ, 121. The number of bits is also 10, and the ghost removal delay time range of the TF 38 is also −2.1 to 42.3 [μs]. The TF 38 output is the output of the equalization circuit 27.

Next, the operation of the conventional automatic equalizer will be described. FIG. 15 is a flow chart for explaining the operation of the conventional automatic equalizer. Note that the signal processing described below is in ROM
CPU2 according to the program stored in advance in
3 is performed by using the RAM 21 and the like.

First, when power is turned on, tuning is switched, etc., the equalization operation is started (S10). Next, the tap coefficient stored in the tap coefficient memory 16 is initialized (S30). This state is shown in equations (5) and (6). CI, i = 0, i = -6,121 (5) CQ, O = 1 CQ, i = 0, i = -6,121, where i ≠ 0 (6) That is, the TF31 for I-axis equalization All tap coefficients are "0"
As for the tap coefficient of the TF 38 for Q-axis equalization, only the main tap coefficient CQ.O is "1", and the other tap coefficients are all "0". Then, the I-axis correction count flag FI is set to "0" (S
12).

Next, the I-axis input waveform memory 17 and the I-axis output waveform memory 19 respectively store GCR signals {XI, i} {Y.
I, i} is captured. I axis input waveform memory 17 has A
From the output of the / D converter 11 to the I-axis output waveform memory 19
The GCR signals are respectively fetched from the outputs of the adder 34 (S13). The CPU 23 performs the 8-field sequence GCR calculation specified in Reference 3 etc. on the captured GCR signal to generate an input impulse waveform {xI, i} and an output impulse waveform {yI, i} ( S14). Then, the correlation calculation shown in the equation (7) is performed (S15).

[0019]

[Equation 1] Then, the tap coefficient correction calculation shown in the equation (8) is performed (S16). CI, i, new = CI, i, old−αdI, i where i = −6,121 (8) where α is a positive minute value. Next, "1" is added to the I-axis correction number flag FI (S17), and the predetermined value NI indicating the predetermined tap coefficient correction number is compared with the I-axis correction number flag FI (S18). When it does not reach the predetermined value, it is determined that the predetermined number of times has not been reached, and the process returns to S13. If it has reached the predetermined value, it is determined that the tap coefficient has been corrected a predetermined number of times, and the process proceeds to step S19 to start the correction of the Q-axis tap coefficient. At this point, the leaked ghost component of the video signal has been removed.

In S19, the Q-axis correction number flag FQ is set to "0". Next, Q axis input waveform memory 18 and Q
Digital multiplexed signals {xQ, i} {yQ, i} are loaded into the axis output waveform memory 20 and respectively. The Q-axis input waveform memory 18 receives the adder 34 output, and the Q-axis output waveform memory 20 receives the digital multiplexed signal from the TF 38 output (S31). After that, the error waveform calculation shown in the equation (9) is performed (S32). eQ, i = yQ, i-dec (yQ, i) (9) Here, dec (yQ, i) is the determination value of yQ, i. Then, using the error waveform obtained by the equation (9), (1
The correlation calculation represented by the equations (0) and (11) is performed (S3).
3).

[0021]

[Equation 2] Here, the reason why the expressions (10) and (11) are separated is that the cycle T / is calculated based on the multiplexed data transmitted in the cycle T.
Since the signal processing is performed with the clock 2 of CK, (9)
This is because, among the waveforms obtained from the equation, the actually significant error waveform is every other sample, as indicated by the circled numbers in FIG. Then, the tap coefficient correction calculation shown in the equation (12) is performed based on the correlation calculation result obtained by the equations (10) and (11) (S34). CQ, i, new = CQ, i, old-αdQ, i where i = -6,121 (11) where α is a small positive value. Then, "1" is added to the Q-axis correction number flag FQ (S24), and the predetermined value NQ indicating the predetermined tap coefficient correction number is compared with the Q-axis correction number flag FQ (S25). When it does not reach the predetermined value, it is determined that the predetermined number of times has not been reached, and the process returns to S31. If the predetermined value has been reached, the tap coefficient correction operation is stopped (S26), assuming that the tap coefficient has been corrected a predetermined number of times.

Since the TFs 31 and 38 both have 128 taps, the total number of taps in the equalization circuit 27 is 256. On the other hand, the I-axis and Q-axis waveform memories 17 to 20 have a small capacity (10 bits * 128),
Low speed (2 / T = 4 fsc / 5 = 2.86 MHz) and time division use are also possible. Further, the tap coefficient memory 16 is C
It holds I, -6 to CI, 121 and CQ, -6 to CQ, 121, but has a small capacity (10 bits * 256). Therefore, using the current integrated circuit technology, RAM21, ROM22,
All digital parts including the CPU 23 other than the equalizer circuit of the automatic equalizer can be made into one chip. On the other hand, Reference 5 (Matsue et al., “Ghost Clean System Control I
C ", Annual Conference of the Television Society, 24-8, 1991
As shown in (1), TF of 128 taps can be integrated into one chip in the current digital IC integration technology. Therefore, in the case of the conventional example, the equalization circuit 27 requires at least two chips of TF. That is, about 2/3 of the circuit scale of the digital section of the automatic equalizer is the equalizer circuit. Therefore, the equalization circuit has been an obstacle to cost reduction of the automatic equalization device.

[0023]

Present digital ICs
When using the integration technology, the automatic equalizer can be configured with at least 3 chips. However, the equalization circuit alone requires at least two chips. Therefore, the equalization circuit has been an obstacle to cost reduction of the automatic equalization device.

An object of the present invention is to reduce the cost of an automatic equalizer by reducing the circuit scale of the equalizer circuit.

[0025]

In an automatic equalizer for supplying a video signal transmitted by quadrature modulation and digital data having a symbol period T to equalize distortion contained in the digital data, the video signal , A first transversal filter having a tap interval of T / 2, an addition unit that adds the output of the first transversal filter and the digital data, and a tap that receives the addition result of the addition unit as an input It comprises a second transversal filter having a number of taps smaller than the number of taps of the first transversal filter at an interval T / 2, and an equalizing means for inputting an output of the second transversal filter.

[0026]

With the above means, the circuit scale of the automatic equalizer itself is reduced by reducing the circuit scale of the equalization circuit.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the overall structure of the present invention will be described before describing the embodiments according to the present invention. FIG. 7 is a diagram showing the overall configuration of the present invention. Note that this is disclosed in Document 1.
Further, FIG. 8 shows frequency bands of various signals.

The signal received by the antenna 70 is supplied to the tuner 71 and converted into an IF signal. The IF signal is composed of a video signal (V) modulated on the in-phase (I) axis and a digital multiplex signal (M) modulated on the quadrature (Q) axis, and includes a Nyquist filter 72 and a BPF (band pass filter). ) 77 and.

The transmission band of the video signal (V) is the same as that of the conventional NTSC signal, as shown in FIG.
It is modulated. The video signal (V) is band-shaped by the Nyquist filter 72 and then supplied to the video detector 74 and the audio detector 73 to generate the conventional video signal and audio signal.

The band of the digital multiplexed signal (M) is shown in FIG.
+0.716 MH for orthogonal carrier as shown in (b)
With z (4 fsc / (10 * 2)), the level is half, +0.7
It has a raised cosine shape in which the 5 MHz level is "0". By such band shaping, the digital multiplexed signal (M) having the period T T = 10/4 fsc = 0.698 [μs] (12) shown in the equation (12) is transmitted. BPF77
The spectrum of the digital multiplexed signal (M) at the output of 1 is shaped in advance so as to have the inverse Nyquist characteristic on the transmitting side, as shown in FIG. The output signal of the BPF 77 is supplied to the carrier regenerator 79 and the sync detectors 78 and 80. Then, the carrier wave regenerator 79 demodulates the carrier wave {-sin (ωIFt)} for demodulating the digital multiplexed signal (M) modulated on the quadrature (Q) axis and the video signal (V) modulated on the in-phase axis. Carrier for {cos (ωIF
t)} is generated. The synchronous detectors 78 and 80 demodulate the digital multiplexed signal (M) and the video signal (V), respectively, using these demodulation carriers.

Normally, linear distortion such as ghost occurs in the transmission system. FIG. 9 shows the phase relationship between the digital multiplexed signal (M) after band shaping and the video signal (V). There is a ghost with a delay time of τ seconds and an intensity of g. As shown in this figure, a video signal (V) is present on the in-phase (I) axis and a digital multiplexed signal (M) is present on the quadrature (Q) axis.

The amplitudes of the ghost components M'and V'of the digital multiplexed signal (M) and the video signal (V) are g.
Double. The phases of these signals are rotated from the main signal by a phase θ determined by the delay time τ and the RF carrier frequency. Therefore, the signal component SQ appearing in the Q-axis direction is (13)
It becomes like a formula. SQ = M + gMcosθ + gVsinθ (13) where the first term is the main signal component of the desired digital multiplex signal, the second term is the ghost component of the digital multiplex signal, and the third term is the leakage ghost component of the video signal. is there.

As disclosed in Document 2, the level of the multiplexed signal needs to be lower than the level of the video signal by about 32 dB. This is to reduce interference with a general television receiver. Therefore, the leakage ghost component of the video signal superimposed on the digital multiplex signal, that is, the third term of the equation (13) is easily larger than the main signal component of the digital multiplex signal.

On the other hand, the signal component SI appearing in the I-axis direction is given by the equation (14). SI = V + gVcos [theta] -gMsin [theta] (14) Here, the first term is the main signal component of the video signal, the second term is the ghost component of the video signal, and the third term is the leakage ghost component of the digital multiplex signal. Automatic equalizer (13)
By removing the second and third terms of the equation, a distortion-free digital multiplex signal is reproduced.

An embodiment according to the present invention will be described in detail below with reference to the drawings. FIG. 1 is a diagram showing the configuration of an embodiment according to the present invention. The same components as those of the related art are designated by the same reference numerals.

In FIG. 1, the I-axis signal component is supplied to an A / D converter 11 for 10-bit processing via a terminal 10. Further, the Q-axis signal component is supplied to the A / D converter 13 for 10-bit processing via the terminal 12. The digital signals output from the A / D converters 11 and 13 are both equalization circuits 1.
4 is supplied.

The output of the A / D converter 11 is also supplied to the I-axis input waveform memory 17. Further, the signal equalized by the I-axis signal component in the equalization circuit 14 is supplied to the I-axis output waveform memory 19. In addition, the Q-axis signal components before and after the equalization process are supplied to the Q-axis input / output waveform memories 18 and 20, respectively.

By the way, the CPU 23 and each waveform memory 17-
20, tap coefficient memory 16, RAM 21, ROM 22
And are connected by a data bus and an address bus. C
The PU 23 uses the RAM 21 in accordance with a program stored in advance in the ROM 22 to perform correlation calculation, tap coefficient correction calculation, etc. on the I-axis and Q-axis signal components.
Then, the obtained tap coefficient is supplied to the equalization circuit 14 via the tap coefficient memory 16. The equalization circuit 14 performs waveform equalization processing based on the supplied tap coefficient.

Further, the timing signal generating circuit 25 is supplied with the video signal output from the video detector 74, and the cycle T /
The two clocks CK, the clock CK2 having the cycle T, and various timing signals are generated and supplied to each circuit.

FIG. 2 shows a configuration example of the equalization circuit 14. I
The output of the A / D converter 11 for the shaft is supplied to a transversal filter (TF) 31 via a short circuit 30. The TF 31 operates at the clock CK, that is, the cycle T / 2. The structure of this TF31 is shown in FIG.

The signal supplied in FIG. 3 is supplied to a group of 128 latches 41 connected in series via a terminal 40. The latch group 41 has a clock C (not shown).
K is added, and signals delayed by T / 2 seconds are added to 128 multiplier groups 42, respectively. This multiplier group 42 has CI, -6 to CI, 12 as tap coefficients, respectively.
A factor of 1 is provided. The number of bits of this tap coefficient is 10 or more. The 128 output signals of the multiplier group 42 are added by the adder 43 and output from the terminal 46.
That is, TF31 is a 128-tap TF with a tap interval T / 2.
Is. Here, the tap interval T / 2 is 0.349 [μ
s]. Therefore, the 128-tap TF31 having a tap coefficient of CI, -6 to CI, 121 is -2.1 to 42.3 [μ
s] ghost removal delay time range.

On the other hand, the output of the A / D converter 13 for the Q axis is added to the delay circuit 33 via the terminal 32. Delay circuit 3
Reference numeral 3 is composed of 6 latches to which a clock CK (not shown) is added, and a delay of 6 * (T / 2) is performed. The TF 31 output and the delay circuit 33 output are added by the adder 34. As a result, the leaked ghost component of the video signal including the previous ghost is removed.

The digital multiplexed signal from which the leaked ghost component of the video signal has been removed by the adder 34 has a tap interval T.
It is supplied to the TF 35 with a tap number of 13 at / 2. The tap coefficients are expressed as CQ, -6 to CQ, 6. The TF 35 can stably perform waveform equalization such as removal of a proximity ghost regardless of the sample phase. It has been shown in many documents that the TF with the tap interval T / 2 does not depend on the sample phase to perform stable equalization, and for example, document 6 (JGProaki
s, “Digital Communications,” McGrawhill Book Comp
any, 1989). The digital multiplex signal subjected to waveform equalization such as removal of proximity ghosts in the TF 35 is thinned out by the sampler 36 every other signal sequence. The timing of thinning out is synchronized with the clock CK2 of the cycle T generated by the timing signal generation circuit 25. Sampler 36
The digital multiplex signal thinned out in the cycle T at is supplied to the TF 37 having a tap number of 58 and a tap interval T. TF3
7 is the tap interval of TF shown in FIG. And the tap coefficient is CQ, i, where i = 8,10,1
2, ..., 122. The reason that i is only an even number here is for convenience of explanation of the tap correction algorithm described later. Since the dependence of the sample phase on the equalization performance has already been removed by the TF35, the TF37 is sufficient for so-called normal ghost waveform equalization.

Next, the operation of the embodiment shown in FIG. 1 will be described with reference to the flowchart of FIG. The signal processing described below is performed by the CPU 23 using the RAM 21 according to a program stored in the ROM 22 in advance.

First, when power is turned on, channel selection is switched, etc., the equalization operation is started (S10). Next, the tap coefficient stored in the tap coefficient memory 16 is initialized (S11). This state is shown in equations (15) and (16). CI, i = 0, i = -6,121 (15) CQ, O = 1 CQ, i = 0, i = -6 to 6,8,10, ..., 122 However, i ≠ 0 (16) That is, I axis etc. All tap coefficients of TF31 for conversion are "0"
As for the tap coefficients of the TFs 35 and 37 for Q-axis equalization, only the main tap coefficient CQ, O is "1" and the other tap coefficients are "0".
Then, the I-axis correction number flag FI is set to "0" (S12).

Next, in the I-axis input waveform memory 17 and the I-axis output waveform memory 19, the GCR signal {XI, i} {Y is input.
I, i} is captured. I axis input waveform memory 17 has A
From the output of the / D converter 11 to the I-axis output waveform memory 19
The GCR signals are respectively fetched from the outputs of the adder 34 (S13). The CPU 23 performs the 8-field sequence GCR calculation specified in Reference 3 etc. on the captured GCR signal to generate an input impulse waveform {xI, i} and an output impulse waveform {yI, i} ( S14). After that, the correlation calculation shown in the equation (17) is performed (S15).

[0047]

[Equation 3] Then, the tap coefficient correction calculation shown in Expression (18) is performed (S16). CI, i, new = CI, i, old−αdI, i where i = −6,121 (18) where α is a positive minute value. Next, "1" is added to the I-axis correction number flag FI (S17), and the predetermined value NI indicating the predetermined tap coefficient correction number is compared with the I-axis correction number flag FI (S18). When it does not reach the predetermined value, it is determined that the predetermined number of times has not been reached, and the process returns to S13. If it has reached the predetermined value, it is determined that the tap coefficient has been corrected a predetermined number of times, and the process proceeds to step S19 to start the correction of the Q-axis tap coefficient. At this point, the leaked ghost component of the video signal has been removed.

In S19, the Q-axis correction number flag FQ is set to "0". Next, Q axis input waveform memory 18 and Q
Digital multiplexed signals {xQ, i} {yQ, i} are loaded into the axis output waveform memory 20 and respectively. The Q-axis input waveform memory 18 receives the output of the adder 34, and the Q-axis output waveform memory 20 receives the digital multiplexed signal from the TF 37 output (S20). At this time, {xQ, i} and {yQ, i
} Are captured in the T / 2 cycle and the T cycle, respectively, as shown in FIG. After that, the error waveform calculation shown in the equation (19) is performed (S21). eQ, i = yQ, i-dec (yQ, i) (19) Here, dec (yQ, i) is the determination value of yQ, i. Then, using the error waveform obtained by equation (19), (20),
The correlation calculation represented by the equations (21) and (22) is performed (S22).

[0049]

[Equation 4] Here, the reason why the equations (20) to (22) are divided is that the input waveform {xQ, i} and the output waveform {yQ, i} giving the error waveform are each the cycle T / 2 as shown in FIG. This is because it is obtained with and T. Therefore, unlike the conventional example, the error waveforms for each T in this embodiment are all meaningful.

Next, the tap coefficient correction calculation shown in equation (23) is performed (S23). CQ, i, new = CQ, i, old-αdQ, i where i = -6 to 6,8,10,12, ....., 122 (23) where α is a positive small value is there. Then, "1" is added to the Q-axis correction number flag FQ (S24), and the predetermined value NQ indicating the predetermined tap coefficient correction number is compared with the Q-axis correction number flag FQ (S25). When it does not reach the predetermined value, it is determined that the predetermined number of times has not been reached, and the process returns to S31. If the predetermined value has been reached, the tap coefficient correction operation is stopped (S26), assuming that the tap coefficient has been corrected a predetermined number of times.

T required for the equalizing circuit 14 in this embodiment.
The number of F taps is 128 taps for TF31, 13 taps for TF35, and 58 taps for TF37.
There are 9 taps. Therefore, the scale of the TF is reduced to 78% as compared with the conventional 256 taps.

Next, another configuration example of the equalization circuit 14 will be described. FIG. 6 is a diagram showing another configuration of the equalization circuit 14. The same components as those in FIG. 2 are designated by the same reference numerals, and the description thereof will be omitted. Here, a short 13-tap TF for Q-axis equalization
Up to 35, it is the same as the equalization circuit shown in FIG.

The output digital multiplex signal of the TF 35, which has been subjected to waveform equalization such as removal of proximity ghosts stably regardless of the sample phase, is supplied to the adder 60. Also adder 60
The TF63 output having the number of taps 58 and the tap interval T is supplied to, and the addition result is supplied to the addition input of the decision unit 61 and the subtractor 62. The determiner 61 performs the determination operation with the clock CK2 having the cycle T, and outputs the output (2 bits).
Is guided to the subtraction input of the subtractor 62 and the TF 63. The 2-bit judgment value corresponds to a 4-value digital multiplex signal. With such a configuration, the same Q-axis output error waveform calculation result as in S21 of FIG. 4 can be obtained in real time from the output of the subtractor 62.

The number of bits of the input signal of the TF63 is reduced from "10" to "2" as compared with the TF37 shown in FIG.
The circuit size of the multiplier that almost determines the circuit size of the TF is approximately proportional to the product of the number of bits of the two inputs of the multiplier.
As a result, the circuit scale of the TF63 becomes ⅕ of that of the TF37. The tap coefficient of TF63 is CQ, i, where i =
It is written as 8, 10, 12, ..., 122. Here, the reason that i is only an even number is for convenience of explanation of the tap correction algorithm as in the equalization circuit shown in FIG. The output of TF63 is supplied to the adder 60,
It is a so-called decision feedback type configuration. It is shown in Reference 6 etc. that this configuration exhibits better equalization performance than the equalization circuit shown in FIG. 2 if tap coefficients are determined while paying attention to stability.

The operation of this equalization circuit is almost the same as that of the flowchart of FIG. The difference is that instead of the Q-axis output waveform, Q-axis output waveform error {eQ, i}
Is directly stored in the Q-axis output waveform memory 20, and the Q-axis output waveform error calculation can be omitted accordingly.

If the circuit scale is normalized with 1 tap of the conventional example having a 10-bit × 10-bit multiplier, the TF normalization circuit scale required for the equalization circuit 14 of this configuration is TF31.
Is 128, TF35 is 13, and TF63 is 12 (= 58 /
5), the total is 153. Therefore, 2 of the conventional example
Compared with 56, the scale of TF is reduced to 60%, and even with the current integrated circuit technology, the equalization circuit can be reduced from 2 chips to 1 chip. This enables a significant cost reduction.

As described above, the I-axis transversal filter having the tap interval T / 2 and the tap interval T / 2 are used.
Of the Q-axis short transversal filter and the Q-axis transversal filter of tap interval T are connected in series to reduce the circuit scale of the equalization circuit, and thus the circuit scale of the automatic equalizer. be able to. This can reduce the price of the automatic equalizer.

[0058]

The I-axis transversal filter with tap interval T / 2, the short transversal filter for Q-axis with tap interval T / 2, and the Q-axis transversal filter with tap interval T are connected in series. By doing so, the circuit scale of the automatic equalizer can be reduced by reducing the circuit scale of the equalization circuit. Therefore, the price of the automatic equalizer can be reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a configuration of an embodiment according to the present invention.

FIG. 2 is a configuration diagram showing a configuration of a specific example of the equalization circuit 14.

FIG. 3 is a configuration diagram showing a configuration of a TF31.

FIG. 4 is a flowchart illustrating the operation of FIG.

FIG. 5 is an explanatory diagram illustrating input / output characteristics of the TF37.

FIG. 6 is a configuration diagram showing a configuration of another specific example of the equalization circuit 14.

FIG. 7 is a configuration diagram showing the overall configuration of the present invention.

FIG. 8 is an explanatory diagram illustrating frequency bands of various signals in FIG.

FIG. 9 is an explanatory diagram illustrating distortion components of a video signal and a digital multiplex signal.

FIG. 10 is an explanatory diagram illustrating various signal components on Cartesian coordinates.

FIG. 11 is a configuration diagram showing a conventional configuration.

FIG. 12 is an explanatory diagram illustrating a reference signal.

FIG. 13 is a configuration diagram showing a configuration of an equalization circuit 27.

FIG. 14 is a configuration diagram showing a configuration of TF31.

15 is a flowchart illustrating the operation of FIG.

FIG. 16 is an explanatory diagram illustrating the input / output characteristics of the TF38.

[Explanation of symbols]

14 ... Equalization circuit, 16 ... Tap coefficient memory, 17 ... I-axis input waveform memory, 18 ... Q-axis input waveform memory, 19 ... I
Axis output waveform memory, 20 ... Q axis output waveform memory, 21 ...
RAM, 22 ... ROM, 23 ... CPU, 25 ... Timing signal generating circuit.

Claims (2)

[Claims] 1. An automatic equalizer, which is supplied with a video signal transmitted by quadrature modulation and digital data of a symbol period T, and which equalizes distortion included in the digital data, receives the video signal as an input. A first transversal filter having a tap interval T / 2, an addition unit that adds the output of the first transversal filter and the digital data, and a tap interval T / 2 that receives the addition result of the addition unit as an input.
Second transversal filter and equalization means that receives the output of the second transversal filter as an input, and the second transversal filter has a tap number equal to that of the first transversal filter. An automatic equalizer characterized by having fewer taps than filters. 2. The automatic equalizer according to claim 1, wherein the equalizing means includes a decision feedback type transversal filter having a tap interval T.