JPH05260273A - Method and device for processing picture - Google Patents

Abstract

PURPOSE:To provide picture processing method and device for outputting a high quality picture by counting prescribed reference information so as to change-over the density growing direction of a density pattern. CONSTITUTION:The clock signal K0 of a frequency at the one-forth of 230 MHz:57.6MHz is provided, the clock signals K1, K2 and K3 whose phases are respectively delayed by 90 deg. in the same frequency are provided and the four clock signals with phase deviations are properly selected so as to be counted so that a signal for printing a black area inside 300 line picture elements is generated, the pulse width of pulse width modulation is controlled based on the signal and a halftone picture at a 300 line picture element unit is realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing method and apparatus for performing halftone processing based on multivalued image information and outputting a high quality multi-tone image.

[0002]

2. Description of the Related Art In recent years, a laser beam printer using electrophotography has been used in an output device of a computer, an output unit of a facsimile device, a so-called digital copying machine for printing image data read from an image scanner, or the like. . The laser beam printer used for these prints at a resolution of, for example, 300 dots / inch.

Therefore, in order to record a halftone image using the conventional laser beam printer, for example, a dither method or density is used as a halftone image processing method which has been conventionally known with a dot unit of about 300 dots / inch as a minimum dot unit. A method of processing using a pattern method is adopted. However, in the above-mentioned conventional halftone image processing method, in order to express the density of 64 gradations, for example, a dot matrix composed of 64 dots consisting of 8 dots in the main scanning × 8 dots in the sub scanning is used to express the halftone. Since it is expressed as a pixel unit of, the resolution of the halftone pixel becomes rough (here, 37.5).
Below a pixel / inch, the pixel / inch will be referred to as a "line"), and the resolution is remarkably reduced, which is not satisfactory in terms of image quality.

When the resolution is increased to, for example, 150 lines, the density that can be expressed becomes 4 gradations. Conversely, when the resolution is 75 lines, the density that can be expressed is 16 gradations. There is a conflicting relationship. Generally, 20
It can be said that it is a relatively high-quality halftone image when resolution of 0 line or more and density expression of 64 gradations or more are possible.

In recent years, a laser beam printer having a resolution of 600 dots / inch has been announced or commercialized. Even with this printer, according to the dither method of the prior art, the resolution of the halftone image was 75 lines and the image quality was not sufficient yet to express the density of 64 gradations. As a first method for improving the above-mentioned inconvenience, a digital multi-valued image signal is received and converted into an analog signal once, and the analog signal and a separately generated periodic analog voltage signal of a triangular wave or a sawtooth wave are generated at a voltage level. There is known a method of comparing, generating a binarized signal subjected to pulse width modulation, and driving a laser by the signal to record to obtain a halftone image.

A method of this kind will be briefly described with reference to FIG. In the same figure, a triangular wave voltage signal for reference which is periodically generated and an input density voltage signal which is digital-analog converted from the input digital image data signal are voltage-compared by an analog voltage comparator, and obtained by the comparison result. The laser is driven by a pulse signal to print a halftone image. In this case, each halftone pixel is
It is printed as a pixel whose density grows from the center of the pixel. In addition, a conventional example using a sawtooth wave is shown in FIG.
Shown in. In this case, each halftone pixel is printed as a pixel whose density grows from the left end of the pixel to the right or from the right end to the left.

However, the above method requires the use of expensive circuit elements in order to handle high-speed analog signals. In addition, a circuit that requires a volume that adjusts the signal voltage to correct variations in the waveform voltage accuracy of the triangular wave, or changes the element constants due to environmental changes such as temperature, and consequently changes the pulse width. There was also a problem that the above stability was not sufficient.

In particular, the slope portion of the triangular wave or sawtooth wave is not linear because the charge / discharge using the capacitor is used, and even if the voltage at the starting point and the ending point of the waveform is adjusted, It is difficult to eliminate the curving distortion that occurs, and this distortion has caused deterioration of image quality in halftone density expression that occurs from an electric circuit. FIG. 65 schematically shows this state. In the figure, indicates the ideal characteristic of the input image density versus the output image density, and indicates the characteristic in the above-mentioned triangular wave voltage system. And, shows the characteristics in the present invention.

Furthermore, when a circuit is constructed, many so-called discrete parts such as resistance elements and capacitors are required, so that it is difficult to reduce the number of parts of the circuit to achieve integration. A second method for improving the above problems is proposed in Japanese Patent Application No. 62-236204. This method receives a digital multi-valued signal,
This is a method of setting a count number of a counter that counts a high-frequency clock according to the digital signal and digitally obtaining a pulse width according to the count number. This method is more stable in the reproducibility of the pulse width than the above analog type pulse width modulation circuit, and is also stable against environmental changes such as temperature.

However, since the above-mentioned method adopts the method of counting the clock, there is a limit frequency in the operation of the digital circuit. Therefore, the minimum step width of the obtained pulse width is defined by the limit frequency of the digital circuit. Therefore, there is a limit in improving the gradation. Also, for example, 8 sheets of 300 dots / inch /
For laser beam printers having a printing speed of minutes, a large number of application softwares for handling character text are sold. Therefore, according to the present invention, in consideration of compatibility with the application software, character text, that is, the resolution of a binary image (300 dots / inch) and the resolution of a multi-valued image obtained by pulse width modulation (300 pixels / inch). It is also possible to make the same. by this,
The resolution map on the memory of the binary image and the multivalued image on the host computer connected to the laser beam printer can be made the same, and the ease of handling the data is enabled.

In order to reproduce a halftone image of 300 lines using the above laser printer, an image clock corresponding to 300 dots / inch is created by dividing the 1.8 MHz into 64 equal to 64 gradations. You can However, in this case, the frequency of the clock to be counted by the counter for setting the pulse width is 115.2 MHz, and it is difficult or impossible to configure the circuit with standard logic such as TTL or CMOS, which is expensive. ECL
It had to be configured with logic. Furthermore, even if the ECL logic is tried to be realized, it is difficult or impossible to print a halftone image having more than 128 steps and higher gradation.

Next, even when the gradation of a halftone image is obtained, there are the following points to be further improved in printing with high image quality. A halftone image printed by the method of FIG. 60 is printed as shown in FIG. That is, since the density of each pixel grows from the central portion of the pixel, the printed image becomes an image in which vertical line streaks are conspicuous. This vertical line streak causes deterioration in image quality.

Further, the halftone image printed by FIG. 61 or the conventional digital counting method described above is printed as shown in FIG. That is, each pixel grows from the left end of the pixel to the right, or all the pixels grow from the right end of the pixel to the left, so that the printed image is also an image in which streaks of vertical lines are conspicuous. Also in this case, the image quality is deteriorated. Similarly, FIG. 64 shows an example of a halftone image according to a conventional example in which a subscanning line is grouped into two lines and a halftone image of 300 lines is similarly printed by a printer of 600 dpi. The image quality had deteriorated.

The present invention has been made to solve the above problems, and an image processing method capable of outputting a high-quality image by counting predetermined reference information and switching the density growth direction of a density pattern, and The purpose is to provide a device. Another object of the present invention is to improve the image quality by changing the density growth direction of the halftone pixels for each sub-scanning line so that the streaks of the vertical lines in the recorded halftone image are inconspicuous. And to provide a device.

[0015]

[Means for Solving the Problems] and

In order to achieve the above object, the configuration of the present invention counts reference information in a predetermined direction in an image processing apparatus that performs halftone processing based on multivalued image information and outputs a multi-tone image. And a density pattern generation means for generating at least two kinds of density patterns having different density growth directions of image formation, and the density pattern generation means for generating the density pattern according to the count value of the reference information counting means. The feature is that the concentration growth direction is switched.

According to another aspect of the invention, in an image processing apparatus for performing halftone processing based on multi-valued image information and outputting a multi-gradation image, a reference signal counting circuit for counting reference signals in the main scanning direction. Means and density pattern generating means for generating at least two kinds of density patterns having different density growth directions of image formation, and the density growth direction of the density pattern is changed according to the count value of the reference signal counting means. It is characterized by switching.

Further, according to another aspect of the invention, in an image processing apparatus which performs halftone processing based on multi-valued image information and outputs a multi-gradation image, the line number counting for counting the number of lines in the sub-scanning direction is performed. Means and density pattern generating means for generating at least two kinds of density patterns having different density growth directions for image formation, and the density growth direction of the density pattern is changed according to the count value of the line number counting means. It is characterized by switching.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described in detail below with reference to the drawings. 1 and 2 are views showing an engine portion of a laser beam printer to which the present invention is applied. In FIG. 1, reference numeral 1 is a sheet that is a recording medium, and 2 is a sheet cassette that holds the sheet 1. The reference numeral 3 separates only the uppermost one of the sheets 1 placed on the sheet cassette 2, and the leading end of the separated sheet is conveyed by the drive means (not shown) to the position of the feed rollers 4, 4 '. The paper feeding cam intermittently rotates every time paper is fed, and one paper is fed corresponding to one rotation.

Reference numeral 18 denotes a reflection type photo sensor, which detects the absence of paper by detecting the reflected light of the paper 1 through a hole 19 provided at the bottom of the paper cassette 2. When the sheet 1 is conveyed to the roller portion by the sheet feeding cam 3, the sheet feeding rollers 4 and 4 ′ rotate while pressing the sheet 1 lightly.
The paper 1 is conveyed. When the sheet is conveyed and the leading end reaches the position of the registration shutter 5, the conveyance of the sheet 1 is stopped by the registration shutter 5, and the sheet feeding rollers 4, 4 '.
Generates conveyance torque while slipping on the sheet 1 and continues to rotate. In this case, by driving the registration solenoid 6 to release the registration shutter 5 in the upward direction, the sheet 1 is sent to the transport rollers 7, 7 '. The registration shutter 5 is driven in synchronism with the transmission timing of an image formed by forming an image of the laser beam 20 on the photosensitive drum 11. In addition, 21
Is a photo sensor, and detects whether or not the sheet 1 is present at the position of the resist shutter 5.

Here, the optical system will be described with reference to FIG. A rotary polygon mirror 52 is driven by a motor 53. The laser driver 50 drives the semiconductor laser 51 according to a pulse width modulation signal sent from a halftone signal processing circuit described later. The laser beam 20 from the semiconductor laser 51 driven by the laser driver 50 is scanned in the main scanning direction by the rotary polygon mirror 52, and the f-θ lens 5 arranged between the rotary polygon mirror 52 and the reflection mirror 54.
After passing through 6, the light is guided onto the photosensitive drum 11 via the reflection mirror 54, forms an image on the photosensitive drum 11, scans in the main scanning direction, and forms a latent image on the main scanning line 57. in this case,
When the printing density is 300 dots / inch and the printing speed is 8 sheets / minute (: A4 size or letter size), the laser lighting time for recording one dot is about 540 nanoseconds. When the printing density is 600 dots / inch and the printing speed is 8 sheets / minute, the laser lighting time for recording one dot is about 135 nanoseconds.

The beam detector 55 arranged at the scanning start position of the laser beam 20 is
Is detected to detect a BD signal which is a synchronization signal for determining the image writing start timing in the main scanning direction. After that, the sheet 1 is sent to the photosensitive drum 11 section by obtaining the carrying torque by the carrying rollers 7, 7'instead of the paper feeding rollers 4, 4 '. A latent image is formed on the surface of the photosensitive drum 11 charged by the charger 13 by the exposure of the laser beam 20. The latent image of the portion exposed by the laser beam 20 is visualized as a toner image by the developing device 14, and then the toner image is transferred onto the paper surface of the paper 1 by the transfer charger 15. A cleaner 12 cleans the surface of the photosensitive drum portion 11 after the transfer onto the sheet 1.

After the toner image is transferred onto the paper 1, the toner image is fixed by the fixing rollers 8 and 8 ', and the paper is discharged onto the paper discharge tray 10 by the discharge rollers 9 and 9'. Further, reference numeral 16 denotes a paper feed table, which enables not only paper feed from the paper cassette 2 but also manual paper feed from the paper feed tray 16 one by one. Paper manually fed to the manual feed roller 17 on the paper feed tray 16 is
Like the paper feed rollers 4 and 4 ', the paper is slightly pressed by the manual paper feed roller 17 so that the leading edge of the paper is the registration shutter 5.
It is conveyed until it reaches, and slips and rotates there. The subsequent transport sequence is exactly the same as when feeding from a cassette.

The fixing roller 8 contains a fixing heater 24, and controls the surface temperature of the fixing roller 8 to a predetermined temperature based on the temperature detected by the thermistor 23 that makes a slip contact with the roller surface of the fixing roller 8. Then, the toner image on the sheet 1 is thermally fixed. A photo sensor 22 detects whether or not there is a sheet at the positions of the fixing rollers 8 and 8 '.

Such a printer (printer engine section)
3, is connected to the controller 200 by an interface means, and receives a print command and an image signal from the controller 200 to perform a print sequence. The signals transmitted and received by this interface means will be briefly described below. FIG. 3 shows the above-described printer 100 and a controller 20 that generates image data.
It is a figure which shows the interface signal between 0. Each of the interface signals shown in the figure will be described below.

PPRDY signal: This signal is sent from the printer 100 to the controller 200, and is a signal notifying that the printer 100 is turned on and the printer 100 is in an operable state. CPRDY signal: a signal sent from the controller 200 to the printer 100, and the controller 200
Is a signal indicating that the controller 200 has been turned on and the controller 200 is in an operable state.

RDY signal: A signal sent from the printer 100 to the controller 200, and the printer 1
When 00 receives a PRNT signal described later, it is a signal indicating that the printing operation can be started or continued anytime. For example, when the paper cassette 2 is out of paper and the print operation cannot be executed, this signal becomes "false".

PRNT signal: A signal sent from the controller 200 to the printer 100, and is a signal for instructing to start the print operation or continue the print operation. Upon receiving this signal, the printer 100 starts the printing operation. VSREQ signal: a signal sent from the printer 100 to the controller 200. When the RDY signal sent from the printer 100 is in the "true" state, the controller 200 sets the PRNT signal to "true" to start the printing operation. Printer 1 is sent, the printer 1
00 is a signal indicating that the image data can be received. In this state, VSYNC described later
It becomes possible to receive a signal.

VSYNC signal: This signal is sent from the controller 200 to the printer 100, and is a signal for synchronizing the sending timing of image data in the sub-scanning direction. Due to this synchronization, the toner image formed on the drum is transferred onto the paper in synchronization with the paper in the sub-scanning direction. This relationship is shown in FIG. In the figure, the image signal VDO is started to be transmitted in synchronization with the BD signal, which will be described later, in the main scanning direction from the time point when the time T1 has elapsed from the leading edge of the VSYNC signal.

BD signal: This signal is sent from the printer 100 to the controller 200, and is a signal for synchronizing the sending timing of image data in the main scanning direction. Due to this synchronization, the toner image formed on the drum is transferred onto the paper in synchronization with the paper in the sub-scanning direction. This signal indicates that the scanning laser beam is at the starting point of main scanning. This relationship is shown in FIG. In the figure, the image signal VDO is started to be transmitted when time T2 has elapsed from the leading edge of the BD signal.

VDO signal: a signal sent from the controller 200 to the printer 100, and a signal for sending image data to be printed. This signal is transmitted in synchronization with the VCLK signal described later. The controller 200 receives code data such as a PCL code transmitted from a host device or the like, generates a character bit signal generated from a character generator corresponding to the code data, or a Postscript code transmitted from the host device. Of the vector code, and generates graphic bit data corresponding to the code, or multi-valued data read from the image scanner, and outputs these data as V
It is transmitted to the printer 100 as a 6-bit VDO signal of DO0 to VDO5. On the other hand, the printer 100 modulates the laser according to the signal and prints. In addition, here
Although the VDO signal is 6 bits, even if it is 8 bits,
It goes without saying that even 10 bits can be applied without departing from the object of the present invention.

VCLK signal: This is a signal sent from the controller 200 to the printer 100, and is the above-mentioned VCLK.
It is a synchronization signal for transmitting and receiving a DO signal. VCLKN signal: a signal sent from the controller 200 to the printer 100, which is synchronized with the above VCLK signal, and has a frequency N times that of the VCLK signal.

SC signal: A "command" that is a signal sent from the controller 200 to the printer 100, and a signal sent from the printer 100 to the controller 200. It is a bidirectional serial signal that transmits and receives "status" bidirectionally. This signal is used as a synchronization signal when transmitting or receiving and an SBSY signal and C which will be described later.
And the BSY signal. Here, the “command” does not have an 8-bit serial signal, and for example, the controller 200 determines whether the paper feeding mode is a mode of feeding from a cassette or a mode of feeding from a manual feed port.
Is command information for instructing the printer 100. The "status" is a serial signal consisting of 8 bits, and is, for example, a wait state where the temperature of the fixing device of the printer has not reached a printable temperature, a paper jam condition, or a paper cassette empty condition. This is information for informing the controller 200 from the printer 100 of various states of the printer.

SCLK signal: A synchronous pulse signal for the printer 100 to fetch a "command" or for the controller 200 to fetch a "status". CBSY signal: A signal for the controller 200 to occupy the SC signal and the SCLK signal before transmitting the command. SBSY signal: The SC signal and the SCLK signal before the printer 100 transmits the "status". Is a signal for occupying

The VDO signal is input to the printer 100 together with the VCLK signal, and then input to the VDO signal processing unit 101 provided in the engine for performing the signal processing of the present invention. The VDO signal processing unit 101 performs signal conversion on the input VDO signal by signal processing described below to generate a converted signal VD.
It is input as OM to the laser driver 50 shown in FIG. 2, and the semiconductor laser 51 is driven to blink.

Regarding the operation of such an interface,
A description will be added below. When the power switch of the printer is turned on and the power switch of the controller is turned on, the printer initializes the internal state of the printer and then
The PPRDY signal is made "true" to the controller.
On the other hand, the controller similarly initializes the internal state of the controller and then sets the CPRDY signal to "true" for the printer. This confirms that the printer and controller have been turned on.

After that, the printer energizes the fixing heater 24 housed inside the fixing rollers 8 and 8 ', and when the surface temperature of the fixing rollers 8 and 8'reaches a fixable temperature, RD
Set the Y signal to "true". After recognizing that the RDY signal is "true", the controller sets the PRNT signal to "true" for the printer when there is data to be printed. When the printer confirms that the PRNT signal is "true", the photosensitive drum 11 is rotated to uniformly initialize the potential on the surface of the photosensitive drum, and at the same time, in the cassette sheet feeding mode, the sheet feeding cam 3 is driven and the leading edge of the sheet is fed. Is conveyed to the position of the registration shutter 5. In the manual paper feed mode, the paper manually fed from the paper feed tray 16 by the manual paper feed roller 17 is conveyed to the position of the registration shutter 15. Then, when the printer becomes ready to accept the VDO signal, the VSREQ signal is set to "true". After confirming that the VSREQ signal is "true", the controller sets the VSYNC signal to "true" and simultaneously sends out the VDO signal in synchronization with the BD signal.

Upon confirming that the VSYNC signal has become "true", the printer drives the registration solenoid 6 in synchronization with this and releases the registration shutter 5. As a result, the sheet 1 is conveyed to the photosensitive drum 11. The printer forms a latent image on the photosensitive drum 11 by turning on the laser beam when the image should be printed black according to the VDO signal and turning off the laser beam when printing the image white. Next, the developing device 14 attaches toner to the latent image and develops the latent image to form a toner image. Next, the toner image on the drum is transferred onto the paper 1 by the transfer charger 15, fixed by the fixing rollers 8 and 8 ′, and then discharged onto the paper discharge tray 10.

Next, the halftone signal processing circuit in the embodiment will be described in detail below as an example in which it is applied to a laser beam printer of 300 dots / inch, 8 sheets / minute.
In the first embodiment, as shown in FIG. 5, 300 dot / inch pixels are divided into 128 areas in the main scanning direction, and each area is printed or not printed. To obtain a toned image.

FIG. 6 is a diagram for explaining the concept of halftone signal processing in the first embodiment. As shown in FIG. 6, 30
If the 0 dot / inch pixel is divided into 128 equal parts, the clock frequency becomes a high frequency of 230 MHz even if the digital count method in the conventional example is used.
A count circuit cannot be realized by a TL or CMOS circuit.

Therefore, in the embodiment, 1/4 of 230 MHz
Frequency: 57.6 MHz clock signal K0 is provided, and clock signals K1, K2, K3 having the same frequency and each phase delayed by 90 degrees are provided, and these four phase-shifted clock signals are appropriately selected and counted. By doing so, a digital counting method is enabled. As a result, the counting frequency is 57.6 MHz and TTL
And a frequency that can be counted by a CMOS circuit,
The pulse width can be controlled with an accuracy of ¼ of the cycle obtained from this frequency.

The method according to the embodiment generally uses TTL or C.
When applied to a clock frequency of 40 MHz or more, which exceeds the frequency which is said to be limited by the MOS circuit, the effect can be further enhanced. Here, FIG. 7 shows a circuit block of the VDO signal processing unit 101 described above. In the figure, 25 is a data latch circuit,
The input 6-bit image signal: VDO0 to VDO5 is latched in synchronization with the clock signal VCLK. In the 6-bit image latched by the latch circuit 25, RO
Address terminals of M26: connected to A0 to A5. On the other hand, the BD signal is input to the flip-flop circuit 35,
The frequency-divided signal is connected to the address terminal A6 of the ROM 26. This address data outputs the data D0 to D5 stored in the ROM 26. At this time, each time the BD signal is input, the addressed data is switched. The data D0 to D5 are input to the data latch 1 and the data latch 2. The flip-flop 27 receives the above-mentioned clock signal VCLK and inverts its output Q and / Q signals every time the clock is input.

When the Q output is in the "L" state, the data latch 1 is set to the write state and its output is set to the high impedance state (at this time, the data latch 2 is set to the read state and the data input is prohibited). Do). When the Q output is in the "H" state, the data latch 1 is set to the read state and the data input is prohibited (at this time, the data latch 2 is set to the write state and the data input is prohibited). Data latch 1 and data latch 2
Is output to the decoder 30 as data D0 'to D5'. In this way, the data latch 1 and the data latch 2 form a double buffer according to the clock signal VCLK.

Reference numeral 30 is a decoder for inputting D0 'to D
Data SD0 to SD5 and data RD0 corresponding to 5 '
~ RD5 is generated. These data are input to each set signal generation circuit 32 and reset signal generation circuit 33.
Reference numeral 31 is a clock phase control circuit, which receives a clock signal VCLKN as shown in FIG.
K1, K2 and K3 are generated.

A detailed circuit of the clock phase control circuit 31 is shown in FIG. In the figure, reference numeral 36 is a clock generation circuit, and a concrete circuit thereof is shown in FIG. That is, the clock signal VCLKN is input, and this signal is passed through the delay network formed by the gates so that the clock signal S0 whose phase is shifted.
Is a circuit for generating S32. Generally, the delay time generated by a gate circuit varies considerably among individual gates, but the gate circuit group used here is preferably a gate circuit formed on the same IC package. In this case, the mutual variation of the delay time of each gate can be made relatively small. The variation in delay time between packages is assumed to be 0.6 nanoseconds to 1.8 nanoseconds per gate. Such a delay time can be realized by a normal inexpensive CMOS gate array. According to this example, such variations in delay time can be automatically corrected to obtain clock signals whose phases differ from each other by approximately 90 degrees.

Reference numeral 37 shown in FIG. 8 is a phase detection circuit, and its concrete circuit is shown in FIG. Reference numeral 39 denotes a sampling circuit, which is a clock signal S0 (: frequency = 57.6 MHz, cycle = 17.4 ns) from the clock generation circuit 36 described above.
And clock signals with 8 different phases: S8, S1
1, S15, S18, S22, S25, S29, S32
Enter. Clock signal: S8, S11, S15, S
18, S22, S25, S29, and S32 are sampled by the sampling circuit 39 at the rising edge of the clock signal S0 (that is, when the time corresponding to the period is 17.4 ns) and sampling data: S8 'and S1.
1 ', S15', S18 ', S22', S25 ', S2
9 ', S32' are obtained. The eight sampling data are data-latched by the encoder circuit 40 at the leading edge of the above-mentioned VSYNC signal, and 3-bit code signals: H0 to H2 are generated according to the latched data (note that Here, an example of latching by the VSYNC signal is shown, but it may be latched at the leading edge of the BD signal). The code signals H0 to H2 are determined as shown in FIG. 11 corresponding to the sampling data. That is, the most optimal clock signal is selected in order to obtain a clock whose phase is shifted by approximately 90 degrees from the sampling result.

For example, as a first example, S8 = "L",
S15 = "H", S18 = "H", S22 = "L", S
When 25 = “L” and S32 = “H”, H0 =
Code signals of "H", H1 = "L", H2 = "L" are generated, and as a second example, S8 = "L", S11.
= “L”, S22 = “H”, S25 = “H”, S29 =
When "L" and S32 = "L", H0 = "H" and H
A code signal of 1 = “H” and H2 = “L” is generated.

Although only the above-mentioned two examples are shown in FIG. 11, the code signals in other cases are similarly determined. The above-mentioned first example occurs in the case of the clock relationship as shown in FIG. The code signal generated in this case: H0 to H2 causes the clock selection circuit 38 to output the clock signal S as the clock output K3.
16, the clock signal S11 is selected as the clock output K2, the clock signal S5 is selected as the clock output K1, and the clock signal S0 is selected as the clock output K0.

The second example occurs when there is a clock relationship as shown in FIG. In accordance with the code signals H0 to H2 generated in this case, the clock selection circuit 38 outputs the clock signal S21 as the clock output K3.
The clock signal S14 is selected as the clock output K2, the clock signal S7 is selected as the clock output K1, and the clock signal S0 is selected as the clock output K0.

By selecting in this way, as shown in FIG. 14, four types of clock signals K0, K having a phase shift for each phase difference obtained by dividing the cycle of the clock signal S0 into four equal parts.
1, K2, K3 can be obtained. The above control is VS
Since it is performed every time the YNC signal is input (or every time the BD signal is input), even if the variation in the gate delay time of the IC or the criminal delay time variation due to temperature is written, it is almost the same. It is possible to generate four types of clock signals having divided phase differences.

Although the embodiment shows an example in which four kinds of clock signals K0, K1, K2, K3 having different phases are obtained with the leading edge of the clock signal VCLKN as a reference, the clock signal VCLKN (: clock signal K0 The signal obtained by inverting (1) may be used as the clock signal K2. In this case, the duty of the clock signal needs to be 50%. Also,
In the embodiment, the case of using four types of clock signals obtained by dividing the phase into four has been described as an example, but it goes without saying that eight types of clock signals obtained by dividing the phase into eight and 16 types of clock signals obtained by dividing into 16 may be used. Yes.

Next, reference numeral 32 shown in FIG. 7 is a set signal generating circuit, which inputs the data SD0 to SD5 and clock signals K0, K1, K2 and K3 and generates a set signal S based on a logic described later. . A reset signal generating circuit 33 receives the data SD0 to SD5 and the clock signals K0, K1, K2 and K3 and generates a reset signal R based on a logic described later. A flip-flop circuit 34 generates an output signal VDOM which is set by the above-mentioned set signal S and reset by the reset signal R.

FIG. 16 is a timing chart showing the timing of each signal described above. Clock signal VCLK
Is a clock signal VCLKN by a controller (not shown).
32 countdown signal (: f _VCLKN = 32 ×
f _VCLK ). Image signal VDO (: VDO0
To VDO5) are input in synchronization with the clock signal VCLK and are latched by the data latch circuit 25. The data is input to the ROM addresses A0 to A5,
Each time the BD signal is input, the stored data D0 to D5 in the ROM addressed by the image signal VDO are alternately output from two different look-up tables. Although the output data is 6 bits (: D0 to D5) in the embodiment, it is not limited to this and 8 bits (: D0 to D7).
It is also possible to

The above-mentioned ROM functions as so-called gamma correction data conversion for correcting the linearity between the input image data and the printing characteristics of the printer. In addition, data D0
The data latch 1 and the data latch 2 functioning as a double buffer circuit for D5 are for enabling high-speed access to supplement the ROM access speed.
That is, the ROM generally has an access speed of 80 nanoseconds to 150 nanoseconds, but the double buffer circuit can perform a high-speed operation with a read access speed of 1 to 2 nanoseconds. Data D obtained from the double buffer circuit
0'-D5 'are input to the decoder 30 as data indicating the density code for the 300-line pixel shown in FIG.

As shown in FIG. 19, the decoder 30 is set corresponding to the area of one black print area in the 300-line pixel area in order to print with the density of the input density code D0'-D5 '. The signal S for designating the black print start point S and the signal R for designating the black print end point R are generated. here,
The black print start point S is assumed to be on the left side of the center of the 300 line pixel, and the black print end point R is assumed to be on the right side of the center of the 300 line pixel, that is, 300 as the density changes from low density to high density. It is selected so that the black print area extends from the center of the line pixel. Therefore, in the example described above, the black print area does not necessarily grow from the center portion, and the black print area may be grown from the left end or the right end of the 300-line pixel. Furthermore, here, 300
The description has been given with an example in which there is only one black print area within a line pixel, but the present invention is not limited to this, and there are two black print areas within 300 line pixels.
One, three, or four does not deviate from the intent of the present invention.

Further, the signal S generated from the decoder 30
D0 to SD5 are code signals for designating the position of the black print start point S in the black print area in FIG.
1 of clock signals K0 to K3 with 2 bits of D5
One clock signal is designated, and the count number N1 for counting the designated clock signal from the left end of the 300-line pixel is designated by 4 bits of SD0 to SD3. That is, the clock signal selected in SD4 to SD5 is 30
The position where N1 is counted from the left end of the 0-line pixel is the black print start point S. Examples of code correspondence at this time are shown in FIGS.
Shown in.

The set signal generation circuit 32 selects one of the clock signals K0 to K3 in accordance with the above-mentioned black print start point designation code signals SD0 to SD5, and when the clock is counted N1, the set signal S is set. Is generated and input to the set input terminal of the flip-flop circuit 34. The signals RD0 to RD5 generated from the decoder 30 are code signals for designating the position of the black print end point R in the black print area in FIG. 17, and are clock signals K0 to K3 with 2 bits of RD4 to RD5. One of the clock signals is designated, and the count number N2 for counting the designated clock signal from the center of the 300-line pixel is designated by 4 bits of RD0 to RD3. That is, the clock signal selected by RD4 to RD5 is input from the center of the 300-line pixel by N2.
The counted position is the black print end point R. 17 and 18 show examples of code correspondence at this time.

The reset signal generating circuit 33 selects one of the clock signals K0 to K3 according to the black print end point designating code signals RD0 to RD5 and sets the clock to 30.
The reset signal R is generated at the time when N2 is counted from the center of the 0-line pixel (when counting K0 16 or the falling edge point of the VCLK signal), and is input to the reset input terminal of the flip-flop circuit 34.

The flip-flop circuit 34 sets the output VDOM signal to "H" level at the rising edge of the input set signal S, and sets the output VDOM signal to "H" level at the rising edge of the reset signal R input here. Reset to L "level. In this way, a signal for printing the black area in the 300-line pixel is generated, and the signal VDOM is generated.
By turning on the laser at the "H" level and turning off the laser at the "L" level, it is possible to reproduce and print a halftone image in 300-line pixel units. Thus, according to the embodiment, it is possible to generate a pulse width modulated signal by a digital method and print a halftone image.

The above description will be specifically described by taking the pattern of FIG. 19 as an example. In this case, for the black print start point designation code signals SD5 to SD0, the clock signal K1 is selected,
Since the clock signal is obtained by counting 12 times, SD5 = 0, SD4 = 1 and SD3 = 1, S
D2 = 1, SD1 = 0 and SD0 = 0 are set. Further, since the black print end point designation code signals RD5 to RD0 are obtained by selecting the clock signal K2 and counting the clock signal 5 times, RD5 = 1, RD4 = 0 and RD3 = 0, RD2 = 1, RD1 = 0 and RD0 = 1 are set.

In this way, the black print start point and the black print end point can be arbitrarily designated. Therefore, as shown in FIG. 20, it is possible to create a pixel in which the density of the pixel grows from the left end portion to the right. On the contrary, as shown in FIG. 28, it is possible to create a pixel in which the density of the pixel grows from the right end to the left end. In the embodiment, the example in which the black print start point and the black print end point are designated by using the 6-bit code signal has been shown, but it goes without saying that the bit number of the code signal may be further increased to 8 bits or the like.

FIGS. 21A to 21C show 3 in the embodiment.
It is an example of a halftone pattern in which the density grows from the left end of the 00-line pixel to the right. In the figure, the density of the halftone increases as it goes from to. 22 to
FIG. 27 corresponds to from FIG. 29A to 29C show examples of patterns in which the black print region expands from the right end of the 300-line pixel to the left in the embodiment. In the figure, the density of the halftone increases as it goes from to. Similarly, FIG.
FIG. 35 corresponds to from FIG.

The ROM 26 stores a density pattern group which grows from the left end portion of the pixel of FIG. 21 to the right corresponding to the case where the address A6 is "L", and the address A6 is "H". Corresponding to the case, a density pattern group that grows from the right end portion of the pixel in FIG. 29 to the left is stored. Therefore, for example, even if the density levels of image signals are the same,
Each time the BD signal is input, for example, the pattern of FIG. 21 and the pattern of FIG. 29 are printed alternately.

An example of a halftone image printed in this way is shown in FIG. As can be seen from the figure, the vertical line streaks in the halftone image appear to disappear. In this way, it is possible to obtain a high quality printed image. The pattern group that is alternately selected for each BD signal input may be a combination of a pattern group in which the density grows from the central portion of the pixel.

[Second Embodiment] Next, a halftone signal processing circuit according to the second embodiment will be described with reference to 8 dots at 600 dots / inch.
The case of application to a laser beam printer of a sheet / minute machine will be described in detail below. In the second embodiment, as shown in FIG. 39, a small area is formed by dividing a 600 dot / inch pixel into 32 equal parts in the main scanning direction, and a 600 dot / inch pixel is divided into 2 pixels in the main scanning direction. In addition, the total of 4 pixels of 2 pixels in the sub-scanning direction is used as a unit of 1-pixel for halftone expression, and each small section is printed or non-printed to obtain 300 lines 1
A 28-step halftone image is obtained.

FIG. 37 is a block diagram showing the second embodiment, in which the same numbers or symbols as those in FIG. 7 are the same. In the figure, reference numeral 35 is a flip-flop circuit which, as shown in FIG. 38, inputs a BD signal, divides it by two, and inverts the output level every time the BD signal is input. The output is input as the address A6 of the ROM 26. Further, the output of the flip-flop 35 is further divided by 2 by the flip-flop 36, and RO
It is input as the address A7 of M26.

When the address data A6 is at "L" level, as shown in FIG. 40, 600 dot / inch pixel "A".
And the density code of the upper half of the 300-line pixel, which is a combination of "B" and "B", is output as output data of the ROM 26. A set signal SD obtained from the decoder 30 based on the density code
41. As shown in FIG. 41, 0 to SD5 designate the black print start point S1 for the upper half black area of the 300 line pixel, and the reset signals RD0 to RD5 indicate the end of black print for the upper half black area of the 300 line pixel. Specify the point R1. The set signal generation circuit 32 and the reset signal generation circuit 33 are based on the clock signal VCLKN which is 16 times the frequency of the clock signal VCLK with a cycle of 300 line pixels (twice the clock cycle corresponding to 600 dots / inch). The obtained clock signals K0 to K3 having different phases are appropriately selected, a predetermined number is counted, and the first pulse width modulation signal VDOM1 is obtained from the flip-flop 34. In this way, for the upper half of the 300-line pixel, as shown in FIG.
Is printed as black.

When the address data A6 is at the "H" level, the density code of the lower half of the 300-line pixel, which is a combination of 600 dot / inch pixels "C" and "D", is output as the output data of the ROM 26. Set signals SD0 to SD5 obtained from the decoder 30 based on the density code
41 designates the black printing start point S2 for the black area in the lower half of the 300-line pixel, and reset signal R
D0 to RD5 designate the black printing end point R2 for the black area of the lower half of 300 line pixels. Set signal generation circuit 32
And the reset signal generation circuit 33 uses the clock signals K0 to K
3 is appropriately selected, a predetermined number is counted, and the second pulse width modulation signal VDOM2 is obtained from the flip-flop 34.
In this way, for the lower half of the 300 line pixel, as shown in FIG.
As shown in, black is printed from S2 to R2.

Therefore, by outputting the same image data for two scans of 600 dots / inch, a halftone image of 300 dots / inch can be generated. Here, the above-mentioned processing will be described more specifically by taking the pattern of FIG. 41 as an example. In this case, the black print start point designation code signals SD5 to SD0 are obtained by selecting the clock signal K2 and counting the clock signal 6 for the first scan (upper half of the 300-line pixel). , SD5 = 1, SD4 = 0 and SD3 = 0,
SD2 = 1, SD1 = 1, SD0 = 0 are set. Further, since the black print end point designation code signals RD5 to RD0 are obtained by selecting the clock signal K3 and counting the clock signal 3 times, RD5 = 1, RD4 =
1 and RD3 = 0, RD2 = 0, RD1 = 1, RD0 =
Set to 1.

For the second scan (: lower half of 300 line pixels), the black print start point designation code signals SD5 to S
Since D0 is obtained by selecting the clock signal K3 and counting that clock signal by 6, SD5 =
1, SD5 = 1, SD4 = 1 and SD3 = 0, SD2 =
1, SD1 = 1 and SD0 = 0 are set. Further, since the black print end point designation code signals RD5 to RD0 are obtained by selecting the clock signal K2 and counting the clock signal 3 times, RD5 = 1, RD4 = 0 and RD3 = 0, RD2 = 0, RD1 = 1 and RD0 = 1 are set.

In this embodiment, an example of designating the black print start point and the black print end point by using the 6-bit code signal is shown, but it goes without saying that the number of bits of the code signal may be further increased. Further, the count for the black print end point has been described by taking the example of counting from the central portion of the pixel, but it goes without saying that counting may be performed from the left side.

In this manner, the upper half of the 300-line pixel is printed by the first scan, the lower half of the 300-line pixel is printed by the second scan, and the 300-line pixel is obtained by performing the main scan twice. Will be completed. In this case, for the image data having the same value, the address A6 is stored in the ROM 26 at the "L" level (: 3).
Black print pattern of "00 line pixels" and "H" (: 3)
The lower half of the 00 line pixel) is combined with the black print pattern to reproduce the halftone of the 300 line pixel, and it is determined in advance as a pattern in which S1, R1 and S2, R2 related to the black print region are printed as a pair. There is.

FIG. 58 is a diagram schematically showing the above situation. In FIG. 58, the area indicated by the dotted line is 600.
The size of dot / inch is shown, and the area shown in practice is 30.
A 0-line pixel is shown. In addition, as described with reference to FIG. 20 to FIG. 35 of the first embodiment, as shown in FIG. 42 and FIG. Further, as shown in FIGS. 50 and 51-, it is possible to specify a pattern in which the density grows from the right end portion of the pixel to the left. Here, the density of the halftone increases as it goes from to.

The ROM 26 stores a density pattern group that grows from the left end of the pixel in FIG. 43 to the right corresponding to the case where the address A7 is "L", and the address A7 is "H". Corresponding to the case, a density pattern group that grows from the right end portion of the pixel in FIG. 51 to the left is stored. Therefore, for example, even if the density levels of image signals are the same,
For example, the pattern of FIG. 43 and the pattern of FIG. 51 are alternately printed every time the BD signal is input.

FIG. 59 shows an example of a halftone image printed in this manner. As can be seen from the figure, the vertical line stripes of the halftone image appear to disappear. In this way, it is possible to obtain a high quality printed image. Note that the pattern group that is alternately selected according to the BD signal (every four BD signal inputs) may be combined with the pattern group in which the density grows from the central portion of the pixel.

In the above-described first embodiment, the case where the engine having a resolution of 300 dots / inch is 8 sheets / minute has been described, but the present invention is not limited to this, and 4 sheets / minute, 16 sheets / minute.
It may be applied to a laser beam printer of minute, ... Further, in the second embodiment, the case where the engine having a resolution of 600 dots / inch is 8 sheets / minute has been described, but it is applied to a laser beam printer of 4 sheets / minute, 16 sheets / minute, .... Is also good.

If the entire circuit shown in FIG. 7 including the delay gate circuit group or the entire circuit shown in FIG. 37 is integrated on the same chip and configured as a one-chip integrated circuit, signal skew is further reduced. It is possible to improve the accuracy of the pulse width, which is effective in improving the image quality.
As described above, according to the embodiment, as shown in FIG. 59, the deviation between the input image density and the output image density with respect to the ideal characteristic generated on the electric circuit returns to the point on the ideal characteristic for each cycle of the clock K0. Therefore, it can be made as small as possible.

Since the pulse width can be controlled by the digital count, the circuit can be easily integrated even when the circuit is formed, and the pulse width can be stably generated while the high-speed pulse signal is generated. It can be generated, and the step of the pulse width can be made finer than ever before. Furthermore, it is possible to perform high-quality printing by making the vertical lines invisible.

[Third Embodiment] The exposure distribution characteristic of laser light and the density distribution characteristic of an image to be formed will be described below with reference to FIGS. 66 and 67. FIG. 66 is a waveform diagram for explaining the exposure distribution characteristic by pulse width modulation. In the figure, (a) shows a laser drive pulse, and when "1", laser light is output. Further, (d) is the intensity I of the laser beam.
Of the laser beam, the horizontal axis represents the distance axis, and the laser light intensity I
The distribution of is usually approximated by a Gaussian distribution.

Therefore, the intensity I of the laser beam is given by the following equation (1) when normalized by the central intensity. However,
x represents the distance with the center as “0”, and σ is the standard deviation of the Gaussian distribution.

[0080]

[Equation 1]

To express the laser beam diameter, the central intensity of 1
There is a case where it is expressed by a strength width of / 2, that is, a half-value width and a strength which is 1 / σ ² of the center strength. Further, 4σ shown in (b) of FIG. 66 is the diameter of the laser beam. Further, the laser beam shown in (b) is scanned at a velocity V in the arrow direction. Therefore, the scanning distance L is expressed by the following equation (2).

[0082]

[Equation 2]

If the scanning speed V is constant, L and T are equivalent, and (a) and (b) of FIG. 66 can be compared coaxially.
66 (c) shows the intensity distribution (solid line / broken line) at points Q and S, and FIG. 66 (d) shows the laser ON times T ₁ and T _2.
The exposure amount distribution (waveforms (a) and (b)) corresponding to the above are shown. Next, the operation will be described.

When the laser light is turned on at the point P and turned off at the point Q, that is, when the laser light is turned on for the time T ₁ shown in (a) of FIG. 66, immediately after the laser light is turned on at the point P The distribution of the intensity I is as shown in (b) of FIG. 66, and the distribution of the intensity I when the laser light is turned off just before the point Q is as shown by the solid line in (c) of FIG. 66. Therefore, P
The intensity I (center P) shown in FIG. 66 (b) is considered to have shifted to the intensity I (center Q) shown in FIG. The quantity E _P is given by the following equation (3). However, P-
Q indicates the distance between P and Q.

[0085]

[Equation 3]

Similarly, the exposure amount E _Q at the Q point is given by the following equation (4) because the Q point is the P point with respect to the Gaussian distribution.

[0087]

[Equation 4]

The exposure amount E _{R at} the center R of the points P and Q is given by the following equation (5).

[0089]

[Equation 5]

In this way, the exposure amount distribution when the laser beam is turned on for the time T ₁ is as shown by the waveform (a) in (d) of FIG. 66. Further, when the ON time T ₁ of the laser light shown in FIG. 66 (a) is set to T _{2 which} is twice, the distribution of the intensity I immediately before the laser light is turned off is as shown by the broken line in FIG. 66 (c), The exposure amount at point P is the area of the horizontal line portion shown in (c), and the exposure amount distribution in that case is shown in FIG. 66 (d).
Waveform (b), the center of the exposure dose distribution also moves from the R point to the Q point.

FIG. 67 is a diagram showing the density characteristic with respect to the exposure amount distribution shown in FIG. 66 (d). The first quadrant represents the output density characteristic in the scanning direction, the vertical axis represents the density D, and the horizontal axis. Represents the distance L. The second quadrant shows the characteristics of the exposure amount and the density of a recording system, for example, an electrophotographic system, and the horizontal axis shows the exposure amount E. However, in the electrophotographic method, there are an image scan in which the density is high with a large exposure amount and a background scan method in which the density is low with a large exposure amount. In this example,
The former is shown. The third quadrant shows the exposure amount distribution shown in (d) of FIG. 66, and the horizontal axis shows the distance L.

The exposure amount distribution shown in the third quadrant has the ED characteristic shown in the second quadrant, and is output as the density distribution shown in the first quadrant to form a visible image. Waveform (a) shown in the first quadrant,
66 (b) corresponds to the waveforms (a) and (b) of FIG. 66 (d), and is the concentration distribution when the ON time of each laser beam is T ₁ · T ₂ . This average density is the volumetric integration of the three-dimensional distribution obtained from the distribution of the first quadrant and the distribution in the scanning direction, and is divided by the unit area. Become. Here, the two-dimensional distribution is omitted because it can be qualitatively understood only by the explanation of the one-dimensional direction, that is, the scanning direction.

Therefore, when the scanning direction is considered one-dimensionally, it is considered to be equivalent to the average density when the waveforms (a) and (b) shown in the first quadrant are integrated and divided by the unit distance. First
The area ratio of the quadrangle is not the ratio of the ON time of the laser light because the E-D characteristic is non-linear, but as the ON time of the laser light is longer, the density is higher and the dot diameter is also larger. It can be understood.

Further, since the latitude of electrophotography is narrow, if the laser ON time is increased to T ₂ or more, the dot density is saturated and only the dot diameter increases as indicated by the broken line (C) in the first quadrant. I understand. However, in general, an optical scanning method using a laser as a light emitting source and a rotary polygon mirror or a vibrating mirror has advantages such as a large scanning angle and a small color dispersion, and thus a facsimile apparatus, various display apparatuses, a printing apparatus. It is often used for etc. In particular, when a rotary polygon mirror is used, in a device using a high-speed scanning method, a phenomenon in which the scanning pitches of the respective scanning lines are unequal intervals caused by the surface tilt of the rotary polygon mirror, uneven rotation of the drum, or vibration ( Hereinafter, referred to as pitch unevenness) occurs.

Further, when trying to reproduce a halftone image by dithering, if the number of gradations is large, the mask size of dither becomes large and the resolution is lowered, making it difficult to read characters and the like. Further, as another binary processing, an error diffusion method or the like has been proposed, but the spatial frequency of the processing result is high,
When printing is performed with an electrophotographic printer having a large dot area ratio, the density tends to be high as a whole. Further, in the halftone dot method which is used for printing in each pixel and for which the area gradation is performed, particularly in the electrophotographic printer, the laser response is steep, and one pixel has a sufficient number of gradation levels. I can't get it.

As described above, when pitch unevenness occurs when a halftone image is output, the black and white portions in the halftone are conspicuous and the image becomes very difficult to see. Here, the cause of the conspicuous pitch unevenness will be described in detail below with reference to FIG. Now, assuming that there is no pitch unevenness and ideal recording is performed, Ga is displayed as shown by A in FIG.
When the light energy distribution on the cross section of the uss beam is developed at a certain development level (t in the figure), it becomes A '. On the other hand, FIG.
When dots come close to each other due to pitch unevenness as shown in (b) of FIG. 8, the light energy curve synthesized as shown by the dotted line B has a raised skirt. Therefore, the output becomes like B ″, and the blackened area is increased, as compared with the case where A ′ is close to B ′.

On the contrary, when the dots are further apart due to the dot pitch unevenness, the blank portion becomes wider, which is noticeable from the averaging with other portions. Since the occurrence of the pitch unevenness has a very bad influence on the print quality, various methods for correcting the unevenness have been reported. As one of them, it is generally stable when the number of lines of image processing is reduced due to the property peculiar to the electrophotographic system. However, if the number of lines processed is reduced, the resolution also decreases.

The laser beam printer according to the third embodiment, which has been made to solve the above-mentioned drawbacks, will be described in detail below. The engine part of the laser beam printer is the same as that of the first embodiment, and the signal processing part will be described in detail here. FIG. 69 is a block diagram showing the structure of the signal processing circuit according to the third embodiment. In the figure, reference numeral 100 denotes an input unit and image data developed into a raster image by a controller unit (not shown) in a host computer or printer is input as multi-valued information. Reference numerals 101 and 102 denote ROMs (read-only memories) in which two types of weighting factors that determine the toner growth direction are stored.

Reference numeral 103 is a sub-scanning counter, which is an input unit 100.
This is a counter for counting the number of lines in the sub-scanning direction of the image data input to. A comparing unit 104 determines the density of input multi-valued data. Reference numeral 105 is a random number generator, the details of which will be described later. A selector 106 is a ROM ₁ or 1 of 101.
02 ROM ₂ data is selected. 107,1
08 is a logic unit, 109 is a shift register unit, 110
Is an output unit, which controls the driving of the laser and performs a printing operation (not shown).

The operation of the third embodiment will be described below with reference to the drawings. FIG. 70 shows a horizontal synchronizing signal generating circuit, which generates a reference clock in synchronization with the horizontal synchronizing signal generated for each line. 301a, 30
Reference numeral 1b is a D-type flip-flop (hereinafter abbreviated as F / F), which constitutes a shift register. 301c-3
01g is a JK type F / F and constitutes a toggled binary counter. Gate circuits 301h to 301m are used to set input conditions.

First, when the power is turned on, a signal (/ PUC) for system reset (not shown) is generated.
The D type F / Fs of a and 301b are reset. Also, 3
J of 301c to 301g through the gate circuit of 01i
The K type F / F is also reset. D of 301a and 301b
CLK is input to the clock terminals of the JK F / Fs of the F / Fs 301c to 301g.

The / Q terminal of the JKF / F of 301c is fed back and input to the JK terminal to perform a toggle operation. This situation is shown in the time chart of FIG.
Shown in _CLK . The 301d JKF / F is connected to the 301k JKF / F Q output and 301d via the 301j gate circuit.
The AND output of the JKF / F output of / Q is input to the JK terminal and toggled. This is 4V _CLK in the time chart of FIG. Hereinafter, similarly, 301e-301g
JKF / F is toggled, and has 2V _CLK · V _CLK · 1 / 2V _CLK in the time chart of FIG. 85, respectively.

On the other hand, when the / BD signal is generated as a horizontal synchronizing signal from the inside of the engine of the laser beam printer, it is input to the D terminal of the DF / F of 301a and latched by the first rising edge of CLK. And
The Q output of the DF / F of 301a is input to the D terminal of the DF / F of 301b and is latched by the next rising edge of CLK. This situation is shown in the time chart of FIG. DF / F / Q output of 301a and DF of 301b
The Q output of / F is input to the gate circuit of 301h, and
As shown in the time chart of 5, when the / BD signal is input, the / BD 'signal is generated. This / BD 'signal is 30
301c as the / RST signal via the gate circuit of 1i
Input to the R terminal of JKF / F of ~ 301g and reset all. Therefore, after reset, the counting operation is started again and the clock V _CLK synchronized with the horizontal synchronizing signal is generated.

FIG. 71 shows the ROM ₁ and ROM shown in FIG.
₂ (101, 102) and a detailed circuit diagram of the selector 106 section. Reference numerals 101 and 102 denote read-only memories (ROMs) in which two types of weighting factors that determine the growth direction of toner are stored as even-line and odd-line data, respectively. 106 to 106h are gate circuits for selectors, which are set to 1 by the output signal of the signal line 203a.
The signals through the gate circuit of 06i 101, 10
Select one of the two ROM outputs.

FIG. 72 is a detailed circuit diagram of the sub-scanning counter section 103 shown in FIG. 103a and 103b are J
KF / F, which constitutes a binary counter that is toggled. With the start of the printing operation, a / TOP signal is generated from the controller unit in the laser beam printer, and both JKF / F of 103a and 103b are reset. When the horizontal sync signal / BD 'is input, 1
It is input to the gate circuit of 03c, and JK of 103a
The F / F / Q output is also fed back, and the toggle operation is performed at the same time as the rising of CLK. Therefore, the output signal line 2
03a and 203b respectively output "1" and "0",
The address signals are input to the ROMs 101 and 102 in FIG. Also, the input multi-valued data 200a output from the controller unit in the laser beam printer
200h is input as an address of each ROM of 101 and 102, and data indicating a toner growth direction corresponding to the input multi-valued data is output.
It is input to the gate of the selector part of h. Here, since the output line 203a outputs "1", the selector unit validates the data of the odd lines, that is, the reference data of the first stage shown in FIGS. 79 to 82.

Therefore, the data from the ROM 101 is validated and output from the output lines 206a to 206h. Further, since scanning for one line is completed and scanning is restarted, the horizontal synchronizing signal / BD 'is input and the JKF / F of 103a is toggled and inverted to "0". Further, the JKF / F of 103b is also fed by the gate circuit of 103d from the / Q output of the JKF / F of 103b.
The toggle operation is set to "1" by the back and the / Q output / BD 'output of the JKF / F of 103a. Therefore, the output signal lines 203a and 203b output "1" and "0", respectively, and are input as address signals to the ROMs 101 and 102 in FIG. The same signal is output again for the input multi-valued data from the controller unit, and the data from the ROM 101, that is, the reference data of the second stage shown in FIGS. 79 to 82 are validated and output from the selectors 206a to 206h.

In the scanning of the next line, the horizontal synchronizing signal / B
The JKF / Fs of 103a and 103b are set to "1" and "1" by D'and are output to the output lines 203a and 203, respectively. At this time, the laser beam
The input multi-valued data of the next line is output from the controller section in the printer, and the ROM data of 102, that is, the reference data of the third stage shown in FIGS. , Output line 206a-
It is output from 206h. Further, in the scanning of the next line, the JKF / Fs of 103a and 103b are the horizontal synchronization signal /
It becomes "0" and "0" depending on BD '. Also,
The input multi-valued data from the controller in the laser beam printer is the same as the previous one. This time as well, data from the ROM 102, that is, FIGS. 79 to 82.
The reference data in the fourth row shown in FIG.
It is output from a to 206h. Where 101 and 102
The reference data from the ROM is the input multi-valued data 200a.
It is output as black data that is simply filled in according to the value of 200h.

FIG. 73 is a random number generator 105 shown in FIG.
3 is a detailed circuit diagram of FIG. 105a to 105h are DF / F
And 105a ~ depending on the / PUC signal after power is turned on.
105h is preset to a predetermined value. That is, 105a and 105b are "0", "0", 105
c and 105d are "1" and "0", 105e and 105f are "0" and "1", and 105g and 105h are "1" and "1".
Becomes Then, by the next 1 / 2V _CLK signal, 105
The Q output of the DF / F of g and the Q output of the DF / F of 105a are input to the gate circuit of 105i for exclusive OR, and the output is input to the D terminal of the DF / F of 105a. Be latched. At the same time, 105h DF / F
Q output of 105b and DF / F Q output of 105b are also input to the gate circuit of 105j, and the same operation is performed to obtain D of 105b.
It is input to the D terminal of the F / F and latched. Similarly, every time 1 / 2V _CLK is sequentially input, 105a, 1
The Q output of 05b is shifted to the right, and the same operation as described above is performed. Therefore, 2-bit random number data is output as the output lines 205a and 205b. FIG. 89 is a diagram showing this state.

FIG. 74 shows a comparison section 104 shown in FIG.
It is a detailed circuit diagram of the logic unit ₁ 107. A comparison unit 104a constitutes a magnitude comparator. 1
Gate circuits 04b and 104c are provided. And 107
Reference numeral a is a decoder, and 107b to 107e are gate circuits. Multi-valued data 200a-2 from within the controller
00h is input to the comparator 104a and the gate circuit 104b. The gate circuit 104b detects whether all the input multi-valued data 200a to 200h are "0". That is, if all of 200a to 200h are "0", "1" is output from the gate circuit 104b. Furthermore, the comparator 104a detects whether the input multi-valued data is "11001111", that is, "207" or more data from the MSB. That is,
If the input multi-valued data is completely white or almost black, it does not make sense to change the toner growth direction by using random numbers, so the input multi-valued data is detected and the random number data is corrected. It is a thing.

The input multi-valued data is "0" or "20".
If it is 7 "or more, 104a gate circuit, 1
"1" is output from the comparator of 04b, 104c
"0" is output through the gate circuit of. On the other hand, 10
The 2-bit output lines 205a and 205b from the random number generator 105 shown in FIG.
Each input is from MSB "00", "01", "10",
Decode “11”. That is, in the case of "00", the "0" output from the decoder of 107a is input to the gate of 107b. In the case of "01", the "0" output from the decoder of 107a is input to the gate of 107c. Thereafter, the signals are sequentially input to the gates 107d and 107e. Here, the "0" output from the gate circuit 104c is input to the gate of 107b and "1" is output. Further, 107c to 107e all output "0". Then, since the gate circuits 107c to 107e are activated by "1" from the gate circuit 104c,
The decoder output result of 107a is output as it is. That is, if the random number output is "0", the gate circuit 104b outputs "1", and the random number output is "1",
If "2" and "3", 107c and 107 respectively
Only the output of the gate circuit of d, 107e becomes "1".

In this way, the density of the input multi-valued data is detected and a random number is generated in the toner growth direction. FIG. 75 shows
FIG. 70 is a detailed circuit diagram of the logic unit ₂ 108 shown in FIG. 69. Reference numerals 108a to 108k denote gate circuits, which determine data by the output from the selector 106 in FIG. 69 and the output from the logic unit 107.

Here, the output lines 207a-207 of FIG.
d has a random number according to the output from the random number generator 105. In the embodiment, random numbers are generated by delaying the toner growth direction. That is, the output value "0, 1, 2, 3" from the random number generator also represents the delay amount. Therefore, the 8-bit result from the selector 106 shown in FIG. 69 is shifted by 0 bit, 1 bit, 2 bits, and 3 bits. Now, when only the output line 207a outputs “1”, that is, when the delay amount is “0”, the outputs of the output lines 206a to 206h are 108a to 10h, respectively.
It is output as output lines 208a to 208h through the gate circuit of 8h. Next, when only the output line 207b outputs "1", the output lines 206a to 206h output the output line 2 via the gate circuits 108b to 108i, respectively.
It is output as 08b to 208i. Hereinafter, the same applies to the case of the output lines 207c and 207d.

76 and 77 are detailed circuit diagrams of the shift register unit 109 shown in FIG. 69. Reference numerals 109a to 109k shown in FIG. 76 are DF / Fs, which form a shift register. Reference numerals 1091 to 109v are gate circuits. Reference numeral 109w shown in FIG. 77 is a gate circuit.
The / Load signal for presetting to the DF / F of 109a to 109k shown in is generated.

As shown in the time chart of FIG. 88, 4V
_CLK · 2V _CLK · V _CLK signal is input to the gate circuit 109w, / Load signal is output. The DF / FKR terminals 109a to 109k shown in FIG.
Since the signal is connected, it is reset to each pulse of / TOP signal of power start or printing start,
The Q outputs of the DF / Fs 109a to 109k are all "0". Output line 2 from the logic unit 108 shown in FIG.
08a to 208k are input to one input of the gate circuits 109l to 109v in FIG. Hereinafter, description will be given based on the time chart of FIG. 88.

The "0" level of the / Load signal by the gate circuit 109w shown in FIG. 77 is 109 shown in FIG.
1 to 109v is input to the other input of the gate circuit, and FIG.
The output lines 208a to 208 of the logic unit 108 shown in FIG.
Each k signal is valid. Therefore, the output line 208a is input to the D terminal of the DF / F of 109a via the gate of 109l. The output line 208b is connected to the D of 109b through an AND / OR circuit which is a 109m gate circuit.
It is input to the D terminal of the F / F. Similarly, the output line 208c
~ 208h is the DF / F of 109c to 109h, respectively
Input to the D terminal of.

Further, the D terminal of the DF / F of 109i is
Either "1" of the output line 208i or the Q output of the DF / F of 109h which is the Q output of the shift register of the preceding stage is preferentially input. Below, 109j / 10
The same applies to the 9k DF / F D terminal. It overlaps the last three to compensate for the amount delayed. The data input to the D terminal of each DF / F is latched by the rising edge of 8V _CLK shown in FIG. Therefore, the last DF /
The value of the output line 208k is output as the output line 209 to the Q output of F109k. After that, the / Load signal becomes "1", all inputs from one of the gate circuits of 109m to 109v are prohibited, and the DF of 109a to 109j is disabled.
The output of the preceding stage of the shift register composed of / F becomes valid. That is, the D terminal of the DF / F of 109b is
The signal from the Q output of 109a is input,
The signal from the Q output of the DF / F of 109j is input to the D terminal of the DF / F of k.

The first stage of the shift register, 10
"0" is input to the D terminal of 9a. The data input to these D terminals is latched by the rising edge of 8V _CLK . Therefore, the next Load signal is "0".
The data in the shift register is sequentially shifted to the right until. As shown in FIG. 88, the output line 209
To the output lines 208j, 208i, ... When the signal of the output line 208d is output,
The / Load signal "0" is output again. At this time, 10
The 9k DF / F D terminal is connected to the 109j DF / F of the previous stage.
Q output of F, that is, the output of the previous output line 209c,
The output of the output line 208k newly generated this time is input with priority of "1". The DF / Fs 109j and 109i also perform the same operation, and the previous data or the new data of the new output lines 208j and 208i is latched. 10
The data of the new output lines 208a to 208h of this time are latched in the DF / Fs of 9a to 109k as in the previous case.

Here, the black coating that determines the toner growth is shifted to the right by 3, 2, 1 or 0 bits by the output from the random number generator 105 shown in FIG. 69, and this is performed randomly. FIG. 78 shows the output unit 11 shown in FIG.
It is a detailed circuit diagram of a laser drive unit of 0. 110a is a laser diode, 110b is a transistor, 110c is an operational amplifier, and 110d is a resistor. 69 shown in FIG.
The output line 209 from the shift register unit 9 is input to the (+) side input terminal of the operator amplifier 110c. If the output line 209 is "1", the transistor 110b is driven, and the laser diode 110a emits light to form an electrostatic latent image on the photosensitive drum. In addition, 110
A current is detected by the resistance of d and is input to the (-) side input terminal of the operator amplifier of 110c to create a constant current drive circuit system.

The above operation is repeated. 79 to 8
2 is a diagram showing weighting factors that determine the growth direction of the toner, and the growth direction changes line by line as shown. 83 and 84 show the dot state of the image when the gray scale is printed by the weighting factors shown in FIGS. 79 to 82, and the gradation is printed in 32 gradations as the input image data increases. In 16a, 16b, 16c, and 16d, the density levels of the input multivalued data 200a to 200h are "1.
This is the case of 11.21.31 ".

As described above, according to the embodiment, since the toner growth direction is changed line by line and the number of halftone processed lines is artificially reduced, the toner adhesion stability is excellent. Therefore, pitch unevenness in the sub-scanning direction can be improved. Further, since the random number is generated to eliminate the regularity of the toner growth direction in the main scanning direction, it is possible to prevent the resolution from decreasing. This is a laser beam printer with a resolution of 6
It is effective because it is as high as 00dpi, and 1000dpi
It goes without saying that the above-mentioned resolution makes the effect extremely remarkable.

In the third embodiment, although the resolution of the laser beam printer is 600 dpi and the digital pulse width modulation is divided into eight, the transmission frequency is increased and
With 16 divisions and 32 divisions, not only the number of gradations increases, but also the effect of reducing pitch unevenness becomes large, and higher quality images can be reproduced. Further, in the embodiment, mono color is explained, but it is needless to say that the same effect can be applied to color printing using four color toners of yellow, magenta, cyan and black, which is effective in reducing pitch unevenness. ..

[Fourth Embodiment] Next, the signal processing section in the fourth embodiment will be described in detail below. Figure 90
FIG. 9 is a block diagram showing a configuration of a signal processing circuit according to a fourth embodiment. Those having the same functions as those in the third embodiment described above are designated by the same reference numerals, and the description thereof will be omitted.

In the figure, reference numeral 120 is a comparison unit, which is an input unit 1.
00 image data and the output from the selector 106 are compared to determine whether or not to turn on the laser. The operation of the fourth embodiment will be described below. FIG. 91 corresponds to FIG.
3 is a detailed circuit diagram around the ROM ₁ , ROM ₂ , sub-scanning counter, and selector shown in FIG. 101a, 102a
Is a counter for counting the number of pixels in the main scanning direction and the number of lines in the sub scanning direction, respectively. That is, the counter 101a
Is a 4-bit counter 4 times the frequency 4V _CLK of the image clock V _CLK to the clock input terminal is input.
Thereby, the corresponding table is designated while the number of pixels in the main scanning direction is calculated. And the counter 102a
The horizontal sync signal / BD is input to the clock terminal 2
It is a bit counter. If the content of the counter 102a is "00", the output "0" of the first bit is input to the C terminal of the selector 106, and the content of the ROM ₁ of 101 is selected and output. Next, when all the contents of the counter 101a are output as "0", the outputs of the counters 101a and 102a are input and designated as addresses to the ROM ₁ and ROM ₂ . That is, every time the counter 101a is counted up, "5, 1, 2, 8, 5, 5
1, 2, 8 "are repeatedly output.

Next, when the scanning of the first line is finished and the scanning of the second line is started, the counter 102a is counted up by the input of the / BD signal, and the output is "0".
When it becomes 1 ″, the selector 106 similarly selects the ROM _1. Every time the counter 101a is counted up,
"7,4,3,6,7,4,3,6" is repeatedly output in order. Further, when the scanning progresses to reach the third and fourth lines, the content of the counter 102a is "10",
It changes to "11". The selector 106 selects the contents of the ROM ₂ by the output "1" of the first bit of the counter 102a. Therefore, depending on the contents of the counter 101a, “2, 8, 5, 1, 2, 8, 5, 5 are sequentially provided.
1 ”is repeated, and in the next line, the counter 10
Depending on the contents of 1a, “3, 6, 7, 4, 3, 6,
7, 4 "is repeated. In this way, the selector 106
Is output as a 4-bit signal to the signal line 206 and input to the comparison unit 120.

FIG. 92 is a detailed circuit diagram of the comparison unit 120 and the output unit 110 shown in FIG. A magnitude comparator 120 performs 4-bit signal comparison. 11
0a is a laser diode, 110b is a transistor, 1
10c is an operational amplifier, and 110d is a resistor.
The comparator 120 includes image data 200 from the input unit 100 and reference data 2 from the selector 106 described above.
06 is input, and the magnitude of the input digital value is determined.
If the image data 200 is larger than or equal to the reference data 206, a "1" level signal is output, the operational amplifier 110c is activated, the transistor 106b is driven, the laser diode 110d is turned on, and printing is performed. Sometimes printed. After that, this is repeated and the printing is completed.

FIG. 93 is a diagram showing the arrangement of weighting factors for determining the toner growth direction in the fourth embodiment. 94 and 95 are diagrams showing the dot state of an image when a gray scale is printed by the arrangement of the weighting coefficients shown in FIG. 93. Printed in gradation.

[Fifth Embodiment] In this embodiment, data interpolation for each line is performed according to the count value of the sub-scanning counter, and multi-valued data is created so as to form a square lattice, and the toner is recorded in accordance with the data. The growth direction is changed line by line. FIG. 96 is a block diagram showing the structure of the signal processing circuit according to the fifth embodiment. 121 is a delay device (DL)
Then, the image data input from the input unit 100 is delayed by 2 clocks and then output. 122 is an arithmetic unit, and the input unit 1
The interpolation calculation of the image data input from 00 is performed. A ROM 123 stores a weighting factor that determines the toner growth direction. A selector 125 selects whether to delay the input data and output the data or to output the data via the arithmetic unit 122, depending on the value of the sub-scanning counter 103. A comparison unit 126 compares the selected image data with the data whose contents from the ROM are output via the selector, and determines whether to turn on the laser.
An output unit 127 controls the driving of the laser to perform printing (not shown).

The operation of the fifth embodiment will be described below. FIG. 97 shows the arithmetic unit 122 shown in FIG.
3 is a block diagram showing the details of FIG. In the embodiment, a linear interpolation, that is, an interpolation calculation by Bi-linear method (hereinafter abbreviated as BI method) will be described. In the figure, 122a and 122c are 8
DF / F for latching bit data, 122b is an adder for adding 8-bit data. The image data 200 from the input unit 100 is input to the DF / F 122a and is latched and stored at the rising edge of the image clock V _CLK . On the other hand, it is input to one side of the adder 122b. The DF / F 122a is connected to the other input of the adder 122b.
The output of is input. Therefore, the adder 122b adds the current data and the previous data and outputs the result. The output line 200c is input to the DF / F 122c and is latched and stored at the rising edge of the image clock V _CLK . The inputs of the adders 122b are 8 bits, respectively, and the addition result 200c is a 9-bit output. Output 20
8 bits from the MSB of 0c is DF as the output line 200c
/ F122c is input. Therefore, the adder 122b halves the two data, that is, averages them.

Thereafter, the same operation is repeated, the two data are averaged by the arithmetic unit 122 shown in FIG. 96, and the interpolation is performed at the intermediate position. On the other hand, in the delay device 121, the image data 200 from the input unit 100 is transferred to the image clock V _CLK.
Are delayed by 2 clocks and output. Next, the output line 300 from the delay device 121 and the output line 301 from the arithmetic unit 122 are input to the selector 125. The sub-scanning counter 103 is the same as the counter 102a shown in FIG. 91 and is a 2-bit counter. The clock terminal has
The horizontal sync signal / BD is input. If the content of the counter 103 is “00”, the output “0” of the first bit is input to the selector 125 and the output line 30 from the delay device 121 is input.
0 is valid and is output. In addition, progressive scanning progresses, 2
At the third and third lines, the sub-scanning counter 103
Becomes "10", the output "1" of the first bit is input to the selector 125, and the output from the calculation unit 122 becomes valid this time.

[0130] Furthermore, the counter for counting the main scanning direction of the pixel is also the same as 101a shown in FIG. 91, the 4-bit counter 4 times the frequency 4V _CLK of the image clock V _CLK to the clock input terminal is input ROM123 Set the address of. If the 0th bit output of the sub-scanning counter 103 is "0", "5, 1, 2, 8" data is sequentially repeated from the ROM 123 by the address designation by the 4-bit counter as shown in FIG. Is output. Next, if the 0th bit output of the sub-scanning counter 103 is "1", the data of "7, 4, 3, 6" is sequentially repeated from the ROM 123 by the address designation by the 4-bit counter as shown in FIG. Is output.

The above operation is repeated, and by the output of the sub-scanning counter, interpolation is performed for each line to create data at an intermediate position, and the toner growth direction can also be changed for each line. As described above, according to the fourth and fifth embodiments, the following effects can be obtained by changing the toner growth direction for each line. (1) The resolution is improved in both the main scanning direction and the sub scanning direction. (2) Since the number of processed lines is agenda, the stability is excellent and the toner adhesion unevenness is reduced.

Thus, in reproducing a halftone image,
Since this can be done without lowering the resolution, it is possible to reduce the difference in shade due to pitch unevenness. Further, in the fifth embodiment, the table capacity can be reduced by adding a simple interpolation circuit. The present invention may be applied to a system including a plurality of devices or an apparatus including a single device. It goes without saying that the present invention can also be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0133]

As described above, according to the present invention, high-quality images can be output by counting predetermined reference information and switching the density growth direction of the density pattern.

[Brief description of drawings]

FIG. 1 is a diagram showing an engine portion of a laser beam printer in an embodiment.

FIG. 2 is a diagram showing an engine portion of the laser beam printer in the embodiment.

FIG. 3 is a diagram showing interface signals between a printer and a controller.

FIG. 4 is a timing chart of interface signals shown in FIG.

FIG. 5 is a diagram showing a pixel unit in the first embodiment.

FIG. 6 is a diagram illustrating a concept in the first embodiment.

FIG. 7 is a block diagram showing a configuration of a VDO signal processing unit in the first embodiment.

8 is a block diagram showing details of the clock phase control circuit shown in FIG. 7. FIG.

9 is a specific circuit diagram of the clock generation circuit shown in FIG.

10 is a specific circuit diagram of the phase detection circuit shown in FIG.

FIG. 11 is a diagram showing generated codes and selected clock signals.

12 is a time chart showing the clock relationship shown in FIG.

FIG. 13 is a time chart showing the clock relationship shown in FIG. 11.

FIG. 14 is a diagram showing four types of clocks having a phase shift for each phase difference.

15 is a time chart of the clock phase control circuit shown in FIG.

16 is a time chart of the set signal, the reset signal and the like shown in FIG.

FIG. 17 is a diagram showing code correspondence.

FIG. 18 is a diagram showing code correspondence.

FIG. 19 is a diagram showing a pattern in the first embodiment.

FIG. 20 is a diagram illustrating a case where the density of a pixel grows from the left end to the right.

FIG. 21 is a diagram showing a density pattern in which the density of a pixel grows from the left end to the right.

FIG. 22 is a diagram showing density patterns corresponding to the items shown in FIG.

FIG. 23 is a diagram showing density patterns corresponding to the items shown in FIGS.

FIG. 24 is a diagram showing density patterns corresponding to (1) to (3) shown in FIG.

FIG. 25 is a diagram showing density patterns corresponding to the items shown in FIGS.

FIG. 26 is a diagram showing a density pattern corresponding to-shown in FIG.

FIG. 27 is a diagram showing density patterns corresponding to the items shown in FIGS.

FIG. 28 is a diagram illustrating a case where the density of a pixel grows from the right end to the left.

FIG. 29 is a diagram showing a density pattern in which the density of a pixel grows from the right end to the left.

FIG. 30 is a diagram showing density patterns corresponding to the items shown in FIGS.

FIG. 31 is a diagram showing density patterns corresponding to (1) to (3) shown in FIG.

FIG. 32 is a diagram showing density patterns corresponding to (1) to (3) shown in FIG.

FIG. 33 is a diagram showing density patterns corresponding to (1) to (3) shown in FIG.

FIG. 34 is a diagram showing a density pattern corresponding to-shown in FIG.

FIG. 35 is a diagram showing a density pattern corresponding to-shown in FIG.

FIG. 36 is a diagram showing a print result of a halftone image in the first embodiment.

FIG. 37 is a block diagram showing a configuration of a VDO signal processing unit in the second embodiment.

38 is a timing chart of the signals shown in FIG. 37. FIG.

FIG. 39 is a diagram showing pixel units in the second embodiment.

FIG. 40 is a diagram showing an outline of processing in the second embodiment.

FIG. 41 is a diagram illustrating a case where the density of a pixel grows from the central portion to the left and right.

FIG. 42 is a diagram showing a case of growing from the left end portion to the right in the second embodiment.

FIG. 43 is a diagram showing a density pattern that grows from the left end to the right in the second embodiment.

FIG. 44 is a diagram showing a density pattern corresponding to-shown in FIG. 43.

FIG. 45 is a diagram showing density patterns corresponding to-shown in FIG.

FIG. 46 is a diagram showing density patterns corresponding to the items shown in FIGS.

FIG. 47 is a diagram showing density patterns corresponding to (1) to (3) shown in FIG. 43.

FIG. 48 is a diagram showing density patterns corresponding to the items shown in FIG.

FIG. 49 is a diagram showing density patterns corresponding to (1) to (3) shown in FIG. 43.

FIG. 50 is a diagram showing a case of growing from the right end portion to the left in the second embodiment.

FIG. 51 is a diagram showing a concentration pattern that grows from the right end to the left in the second embodiment.

FIG. 52 is a diagram showing density patterns corresponding to-shown in FIG.

FIG. 53 is a diagram showing density patterns corresponding to-shown in FIG.

FIG. 54 is a diagram showing density patterns corresponding to-shown in FIG.

FIG. 55 is a diagram showing density patterns corresponding to-shown in FIG. 51.

FIG. 56 is a diagram showing a density pattern corresponding to-shown in FIG. 51.

FIG. 57 is a diagram showing density patterns corresponding to-shown in FIG.

FIG. 58 is a schematic view of the recording method in the second embodiment.

FIG. 59 is a diagram showing a print result of a halftone image in the second embodiment.

FIG. 60 is a diagram illustrating pulse width modulation using a triangular wave.

FIG. 61 is a diagram illustrating pulse width modulation using a sawtooth wave.

FIG. 62 is a diagram showing a result of printing a halftone image by the method shown in FIG. 60.

FIG. 63 is a diagram showing a result of printing a halftone image by the method shown in FIG. 61.

FIG. 64 is a diagram showing a result of printing a halftone image with a 600 dpi printer.

FIG. 65 is a schematic diagram showing distortion of output image density with respect to input.

FIG. 66 is a diagram for explaining exposure distribution characteristics by pulse width modulation.

67 is a diagram for explaining density characteristics with respect to the exposure distribution shown in FIG. 66.

FIG. 68 is a diagram illustrating pitch unevenness of a halftone image.

FIG. 69 is a block diagram showing a configuration of a signal processing circuit according to the third embodiment.

FIG. 70 is a detailed circuit diagram of a horizontal synchronizing signal generating circuit.

71] FIG. 71 shows ROM ₁ , ROM ₂ (101,
102) and a detailed circuit diagram of a selector 106 section.

72 is a detailed circuit diagram of the sub-scanning counter section 103 shown in FIG. 69.

73 is a detailed circuit diagram of the random number generator 105 shown in FIG. 69. FIG.

74 is a comparison unit 104 and a logic unit ₁ shown in FIG. 69.
7 is a detailed circuit diagram of 107. FIG.

75 is a detailed circuit diagram of the logic unit ₂ 108 shown in FIG. 69. FIG.

76 is a detailed circuit diagram of the shift register section 109 shown in FIG. 69. FIG.

77 is a detailed circuit diagram of the shift register unit 109 shown in FIG. 69. FIG.

78 is a detailed circuit diagram of the output unit 110 shown in FIG. 69. FIG.

FIG. 79 is a diagram showing the toner growth direction in the third embodiment.

FIG. 80 is a diagram showing a toner growth direction in the third embodiment.

FIG. 81 is a diagram showing a toner growth direction in the third embodiment.

FIG. 82 is a diagram showing a toner growth direction in the third embodiment.

83 is a diagram showing a dot state of an image when a gray scale is printed by the arrangement of the weighting factors shown in FIGS. 79 to 82. FIG.

84 is a diagram showing a dot state of an image when a gray scale is printed by the arrangement of the weighting factors shown in FIGS. 79 to 82. FIG.

85 shows a time chart of the horizontal synchronizing signal generating circuit shown in FIG. 70.

86 is a time chart showing the operation of the sub-scanning counter shown in FIG. 72. FIG.

87 is a diagram showing timing of multi-valued data output from the controller unit in response to the horizontal synchronizing signal BD 'shown in FIGS. 71 and 72. FIG.

88 is a diagram showing a time chart of the shift register unit shown in FIGS. 76 and 77. FIG.

89 is a diagram showing an output from the random number generator shown in FIG. 73. FIG.

FIG. 90 is a block diagram showing a configuration of a signal processing circuit according to a fourth embodiment.

91 is a detailed circuit diagram around the ROM and selector shown in FIG. 90. FIG.

92 is a detailed circuit diagram of a comparison unit and an output unit shown in FIG. 90.

FIG. 93 is a diagram showing a toner growth direction in the fourth embodiment.

FIG. 94 is a diagram showing a dot state of an image when a gray scale is printed by the array of weighting factors shown in FIG. 93.

95 is a diagram showing a dot state of an image when a gray scale is printed by the array of weighting factors shown in FIG. 93.

FIG. 96 is a block diagram showing the structure of a signal processing circuit according to the fifth embodiment.

97 is a detailed block diagram showing a configuration of a calculation unit shown in FIG. 96.

FIG. 98 is a diagram showing a toner growth direction in the fifth embodiment.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Takashi Kawana 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Toshihiko Sato 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Within the corporation

Claims (6)

[Claims] 1. An image processing apparatus for performing halftone processing based on multi-valued image information and outputting a multi-gradation image, a reference information counting means for counting reference information in a predetermined direction, and density growth for image formation. An image processing, comprising: a density pattern generating means for generating at least two kinds of density patterns having different directions, and switching the density growth direction of the density pattern according to the count value of the reference information counting means. apparatus. 2. An image processing apparatus which performs halftone processing based on multi-valued image information and outputs a multi-gradation image, a reference signal counting means for counting a reference signal in the main scanning direction, and an image forming density. An image characterized in that it has at least two types of density patterns with different growth directions, and switches the density growth direction of the density pattern according to the count value of the reference signal counting means. Processing equipment. 3. An image processing apparatus which performs halftone processing based on multi-valued image information and outputs a multi-tone image, a line number counting means for counting the number of lines in the sub-scanning direction, and an image forming density. An image characterized by having a density pattern generating means for generating at least two kinds of density patterns having different growth directions, and switching the density growth direction of the density pattern according to the count value of the line number counting means. Processing equipment. 4. An image processing apparatus which performs halftone processing based on multi-valued image information and outputs a multi-tone image, line number counting means for counting the number of lines in the sub-scanning direction, and random number generation. A random number generating means and a density pattern generating means for generating at least two kinds of density patterns having different density growth directions of image formation are provided, and the random number generating means is responsive to the count value in the line number counting means and the random number in the random number generating means And an image processing apparatus for switching the density growth direction of the density pattern. 5. An image processing apparatus which performs halftone processing based on multi-valued image information and outputs a multi-gradation image, a line number counting means for counting the number of lines in the sub-scanning direction, and the line number counting. The interpolating means for interpolating pixels in the main scanning direction according to the number of lines counted by the means, and the density growing means for growing the pixels interpolated by the interpolating means in a predetermined density growing direction. Image processing device. 6. An image processing method for performing halftone processing based on multivalued image information to output a multi-tone image, a reference information counting step of counting reference information in a predetermined direction, and a density growth for image formation. A density pattern generating step of generating at least two kinds of density patterns having different directions, and switching the density growth direction of the density pattern according to the count value in the reference information counting step. Method.