JPH05258471A - Data conversion circuit - Google Patents

Abstract

PURPOSE:To convert digital information signals containing sample data into digital information signals corresponding to the n-bit digital video signal format. CONSTITUTION:On an n-bit digital information signal B, a data comparison circuit 26 compares whether each sample data is within the prescribed ranges N3-N4 decided by the abovementioned format, generating comparison result D. Thus, a data value conversion circuit 23 converts the sample data of the digital information signal B to be within the range. An identification code generation circuit 27 changes the comparison result D to identification code data K. A data comparison circuit 29 compares whether it is within the prescribed range N5-N6 decided by the above-mentioned format, and the comparison result D' is outputted. Thus, a data value conversion circuit 28 converts the identification code data K to be n-bit identification code data FLG within the range, being added to a digital information signal C from a data value conversion circuit 23 in a switch circuit 24.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data conversion circuit for converting an arbitrary digital information signal into a digital video signal format or converting a digital information signal in the digital video signal format into an original digital information signal, and more particularly, The present invention relates to a data conversion circuit suitable for use in a digital signal magnetic recording / reproducing apparatus such as a digital VTR.

[0002]

2. Description of the Related Art In an analog signal magnetic recording / reproducing apparatus such as an analog VTR, a data conversion circuit used for recording / reproducing a digital information signal such as a digital audio signal in place of an analog video signal has been conventionally known, for example. Consumer Electronics P described in Stereo Technical Committee / Video Technical Committee file (STC-007) of Japan Electronic Machinery Manufacturers Association
CM encoder / decoders are known. Such a data conversion circuit converts a digital audio signal into a signal conforming to an analog video signal format,
The digital audio signal is processed so that all the sample data thereof exceeds the pedestal level value of the digital video signal, thereby enabling recording / reproduction of the digital audio signal in the analog VTR.

By the way, in recent years, in addition to an analog VTR as a VTR, a digital VTR which is a digital signal magnetic recording / reproducing apparatus has been developed. For example, a digital V such as a D2 standard composite digital VTR
In TR, in order to increase the recording capacity, only the video signal portion of the digital video signal is extracted by digital processing, and only that portion is recorded / reproduced on the magnetic tape.

[0004]

By the way, in the prior art,
As described above, a data conversion circuit has already been proposed for making it possible to record / reproduce a digital information signal in the analog VTR instead of the analog video signal. No data conversion circuit has been proposed so far as it can record / reproduce a signal like a digital video signal.

Therefore, consider conversion of a digital information signal into a signal of digital video signal format in a digital VTR so that an arbitrary digital information signal can be recorded / reproduced similarly to the digital video signal. ..

In order to convert the digital information signal into a signal in the digital video signal format, a sync signal equivalent to the sync signal of the digital video signal may be added to the digital information signal. However, simply adding a sync signal equivalent to the sync signal of the digital video signal to the digital information signal causes the following problems.

That is, in general, in a digital VTR, if sample data having a value smaller than a predetermined value N ₁ continues in a digital video signal to be recorded and reproduced, that portion is treated as a synchronizing signal portion and processed. I will end up. The sample data having a value larger than the predetermined value N ₂ in the digital video signal is defined as a code for internal processing of the digital VTR.

Therefore, if the digital information signal before adding the synchronizing signal includes sample data having a value smaller than the predetermined value N ₁ or sample data having a value larger than the predetermined value N ₂ , the digital information signal When the above synchronizing signal is added to the signal and converted into a digital information signal in the digital video signal format, the digital information signal in this digital video signal format includes the portion other than the synchronizing signal, that is, the digital information before adding the synchronizing signal. In the portion where the signal exists (hereinafter referred to as the information signal portion), the sample data having a value smaller than the predetermined value N ₁ or the sample data having a value larger than the predetermined value N ₂ exists. Therefore, when such a digital information signal is recorded and reproduced by the digital VTR, the sample data having a value smaller than the predetermined value N _{1 of} the reproduced information signal portion of the digital information signal is erroneously determined as the synchronization signal portion, and the digital VTR is erroneously determined. Malfunction, and sample data with a value larger than the predetermined value N _{2 is applied} to the digital VTR.
There is a possibility that the original digital information signal may not be obtained because the internal circuit determines that it is coded data.

An object of the present invention is to solve the above problems and provide a data conversion circuit capable of converting an arbitrary digital information signal into a signal of an appropriate digital video signal format.

Another object of the present invention is to provide a data conversion circuit capable of surely converting any digital information signal converted into a digital video signal format signal back to the original digital information signal. To provide.

[0011]

To achieve the above object, the present invention determines whether the value of each sample data of an input digital information signal is within a first range determined by a digital video signal format. Then, the first means for outputting a bit representing the determination result, and the sample data whose value is not within the first range are converted based on the determination result of the first means, and the value is converted into the first value. And (n-1) bit identification code data by dividing the (n-1) number of decision bits of each sample data from the first means by the second means to be within the range of 1 A third means for generating, a fourth means for judging whether or not the value of the identification code data is within a predetermined second range, and a value based on the judgment result of the fourth means. The identification code data that is not within the second range is converted so that its value is Of the digital information signal from the second means and the second means for making the identification code data of the quantization bit number n by adding a conversion flag indicating the presence or absence of conversion. -1) Sixth means for adding the identification code data from the fifth means to each sample data, and equivalent to the synchronizing signal in the digital video signal format for the digital information signal from the sixth means And a seventh means for adding the synchronization signal of.

As described above, a digital information signal converted into a digital video signal format signal having a quantization bit number n is used as an input signal, and the identification code having a quantization bit number n added to the input digital information signal. Eighth means for extracting data and generating data representing the presence or absence of conversion for each sample data of the input digital information signal, and the converted sample data of the input digital information signal based on the data. And a ninth means for converting the original value into sample data.

[0013]

The first range is at least a range included in the range of the value of the video signal portion in the digital video signal format. First, by the first means, for each sample data of the input digital information signal. It is determined whether the value is in this first range. And this first
When there is sample data having a value outside the range of, the sample data is converted so that the value falls within the first range. This causes all sample data values of the digital information signal to fall within the values of the video signal portion in the digital video signal format. Along with this, the bits representing the result of the above judgment for each sample data are combined to make identification code data. When this identification code data is outside the range of the value of the video signal part in the digital video signal format, it is set to that range. In addition to the conversion, the conversion flag indicating the conversion is added and added to the digital information signal subjected to the above conversion processing. As a result, the converted sample data in the digital information signal can be easily discriminated, and the data added for this discrimination is within the range of the value of the video signal portion in the digital video signal format. Even if a synchronizing signal in the digital video signal format is added to this and recording / reproducing is performed by the digital signal magnetic recording / reproducing apparatus, an erroneous synchronizing signal or code is not generated.

Further, the identification code data extracted from the input digital information signal processed as described above determines the sample data of which the value has been converted as described above in the input digital information signal. The value of the sample data whose value has been converted as described above can be converted to the original value, and thus the original digital information signal can be obtained.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a digital signal magnetic recording / reproducing apparatus equipped with a data conversion circuit according to the present invention will be described with reference to FIG. 1 to 3 are input terminals, 4 is an A / D (analog / digital) converter, 5 is a recording data conversion circuit which is a data conversion circuit according to the present invention, 6 is a switch circuit, 7 is a recording system digital processing circuit, Reference numeral 8 is a modulator, 9 is a recording amplifier, 10 is a recording magnetic head, 11 is a magnetic tape, 12 is a reproducing magnetic head, 13 is a reproducing equalizer, and 1 is a reproducing magnetic head.
Reference numeral 4 is a demodulator, 15 is a reproduction system digital processing circuit, 16 is a reproduction data conversion circuit, 17 is a D / A (digital / analog) converter, and 18 to 20 are output terminals.

In FIG. 3, input terminals 1, 2, and 3 are input terminals for a digital information signal, a digital video signal, and an analog video signal, respectively. When an analog video signal is input from the input terminal 3, the analog video signals are input. The signal has a quantization bit number n by the A / D converter 4.
Is converted into a digital video signal of and is supplied to the terminal B of the switch circuit 6 which is closed on the terminal B side. Input terminal 2
When a digital video signal whose number of quantization bits is n is input from the switch circuit 6 which is closed to the terminal A side
Is supplied to the terminal A of. The digital video signal selected and output by the switch circuit 6 is supplied to the recording system digital processing circuit 7, where it is subjected to digital signal processing and converted into a recording digital signal. This recorded digital signal is
After being modulated by a modulator 8 and amplified by a recording amplifier 9, the magnetic tape 1 is supplied to a predetermined number of recording magnetic heads 10.
Recorded on 1.

When an arbitrary digital information signal having the same number of quantization bits n as the digital video signal is input from the input terminal 1, this digital information signal is processed by the recording data conversion circuit 5 as described later. , Is converted into a digital information signal in a digital video signal format and supplied to the terminal A side of the switch circuit 6. At this time, the switch circuit 6 is closed on the terminal A side, and the same processing as that of the digital video signal is performed and the magnetic tape 11 is processed.
Recorded in.

On the other hand, the reproduced digital signal reproduced from the magnetic tape 11 by a predetermined number of reproducing magnetic heads 12 is processed by the reproducing equalizer 13 and further demodulated by the demodulator 14. The demodulated reproduced digital signal is subjected to digital signal processing by the reproducing system digital processing circuit 15,
It is converted into a digital video signal or a digital information signal in a digital video signal format. The digital video signal is output from the output terminal 19, and at the same time, converted into an analog video signal by the D / A converter 17 and output from the output terminal 20.

When the digital information signal converted into the digital video signal format is output from the reproduction system digital processing circuit 15, the reproduction data conversion circuit 16 converts the digital information signal into the original format digital information signal and outputs it. It is output from 18.

By the above operation, it is possible to record / reproduce the digital information signal on the magnetic tape 11 in the digital VTR, similarly to the digital video signal.

Next, an embodiment of the present invention used as the recording data conversion circuit 5 and the reproduction data conversion circuit 16 in FIG. 3 will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a data conversion circuit according to the present invention used as the recording data conversion circuit 5 of FIG.
1 is an input terminal, 22 is a recording memory, 23 is a data value conversion circuit, 24 is a switch circuit, 25 is a predetermined value generation circuit, 2
6 is a data comparison circuit, 27 is an identification code generation circuit, 28 is a data value conversion circuit, 29 is a data comparison circuit, 30 is an identification code addition circuit, 31 is a switch circuit, 32 is a synchronization signal generation circuit, and 33 is a synchronization signal addition circuit. The circuit, 34 is an output terminal.

Next, the operation of this embodiment will be described with reference to FIG. However, in FIG. 4, signals corresponding to those in FIG. 1 are denoted by the same reference numerals.

The digital information signal A input from the input terminal 21 is a series of sample data D having a quantization bit number n.
₁ , D ₂ , D ₃ ,. ． ． And is temporarily stored in the recording memory 22. From the recording memory 22, by the control signal G from the identification code addition circuit 30 and the control signal H from the synchronization signal addition circuit 33, identification code conversion data FLG described later is added for every (n-1) sample data. In order to be able to do so, the digital information signal is time-axis processed and read out, and is supplied to the data comparison circuit 26 and the data value conversion circuit 23 as the digital information signal B.

The data comparison circuit 26 is also supplied with the predetermined values N ₃ and N ₄ from the predetermined value generation circuit 25, and the respective sample data D ₁ , D ₂ , D ₃ ,. ． ． The magnitude comparison with the predetermined values N ₃ and N ₄ is performed for each time, and each sample data D ₁ , D ₂ , D ₃ ,. ． ． When N ₃ ≤Ns ≤N ₄ , 1-bit comparison result data D is generated which is "0" when N ₃ ≤Ns ≤N ₄ and "1" when Ns <N ₃ or N ₄ <Ns. The comparison result data D is the data value conversion circuit 23.
And the identification code generation circuit 27.

Here, the predetermined value N ₃ may be larger than the digital value N ₁ of the synchronizing signal in the digital video signal format, and the predetermined value N ₄ may be smaller than the digital value N ₂ similarly defined in the code. ..

In the data value conversion circuit 23, based on this comparison result data D, each sample data D ₁ , D ₂ , D ₃ ,. ． ． Among them, the sample data having a value smaller than the predetermined value N ₃ (for example, the sample data D ₂ ) becomes the sample data having a value larger than the predetermined value N ₁ (for example, the sample data D ₂ '), and the sample data having a value smaller than the predetermined value N ₄ . Even larger sample data (eg, sample data D ₃ ) is converted into sample data smaller than a predetermined value N ₂ (eg, sample data D ₃ ″), and is output as a digital information signal C to one terminal of the switch circuit 24. As the conversion method of the sample data, for example, a method of inverting a predetermined bit of the sample data having a value smaller than a predetermined value N ₃ or a sample data having a value larger than the predetermined value N ₄ is used. Can be considered.

In the identification code generation circuit 27, the recording memory 2
Based on (n-1) comparison result data D from the data comparison circuit 26 corresponding to (n-1) sample data as a unit from 2, the (n-1) -bit parallel identification code The data K is generated and supplied to the data comparison circuit 29 and the data value conversion circuit 28. The identification code data K is obtained by, for example, parallelizing the (n-1) comparison result data D described above. The data comparing circuit 29 is supplied with the predetermined values N ₅ and N ₆ from the predetermined value generating circuit 25, compares these with the identification code data K, and if the value of the identification code data K is Ks, then N when _{5 ≦ Ks ≦ N 6 "0} ", Ks < when N ₅ or N ₆ <Ks "1" become the comparison result data D'is generated.
The comparison result data D ′ is supplied to the data value conversion circuit 28.

In the data value conversion circuit 28, when the comparison result data D'from the data comparison circuit 29 is "1", the identification code data K becomes "10" if the upper 2 bits are "00", " If it is 11 ", it is converted to" 01 ", respectively, and indicates whether or not such conversion is performed (" 1 "when converted," 0 "when not converted). Upper bit (MS
B) is added and becomes identification code conversion data FLG having the number of quantization bits n, and the other terminal II of the switch circuit 24
Is supplied to. In the identification code data K, the first one of the (n-1) unit comparison result data D output from the data comparison circuit 26 is the least significant bit (L).
SB), and the last (n-1) th one is designated as MSB. In the data value conversion circuit 28, the above N ₅ ≦
When Ks ≦ N ₆ , (n−1) -bit identification code data K
Even if "0" bit is added as MSB to n-bit data, the value is less than the predetermined value N ₁ or the predetermined value N ₂
Make sure that Ks <N ₅ or N ₆ <
At the time of Ks, even if the data value conversion circuit 28 performs the above conversion and the addition of the MSB of "1" bit, the above value is set so as not to become the predetermined value N ₁ or less or the predetermined value N ₂ or more. The predetermined values N ₅ and N ₆ are determined.

In the above, the data comparison circuits 26, 2
Although the comparison result data D and D ′ output from 9 are 1-bit data, these are the data value conversion circuits 23 and 28.
Since it suffices to indicate whether or not the data value should be converted with, data with an arbitrary number of bits of 2 bits or more may be used.

The identification code adding circuit 30 outputs a control signal G for controlling the read timing of each sample data from the recording memory 22 and the switch circuit 24. The switch circuit 24 is closed by the control signal G to the terminal I side during the period when (n-1) sample data is read from the data value conversion circuit 23, and the identification code conversion data FLG is output from the data value conversion circuit 28. Closed to the terminal II side for a certain period. As a result, (n-1) of the digital information signal C
The digital information signal E to which the identification code conversion data FLG is added for each sample data is output from the switch circuit 24 and supplied to one terminal III of the switch circuit 31.

The control signal H output from the sync signal adding circuit 33 is, for example, "H" (high level) during the sync signal adding period of the digital information signal E supplied to the terminal III of the switch circuit 31, and other than that. The control signal H controls the read-out of the recording memory 22 so that it becomes "L" (low level) during the period and the timing is matched in this way. The synchronization signal generation circuit 32 is controlled by the control signal H, and the synchronization signal S is generated at the timing of the "H" period.
YN is generated and output. The synchronization signal SYN is supplied to the terminal IV of the switch circuit 31. The switch circuit 31 is controlled by the control signal H from the synchronizing signal adding circuit 33, and is switched to the terminal IV side when the control signal H is "H" and to the terminal III side when it is "L". As a result, the synchronizing signal is added to the digital information signal E, and the digital information signal F is output from the output terminal 34. This digital information signal F is a digital information signal of the above digital video signal format, and the switch circuit 6 of FIG.
Is supplied to the terminal A side of the.

The digital value of the information signal portion of the digital information signal F obtained as described above exists within the range of the value determined for the video information in the digital video signal format.

FIG. 2 is a block diagram showing another embodiment of the data conversion circuit according to the present invention used as the reproduction data conversion circuit 16 in FIG. 3, wherein 35 is an input terminal, 36 is a synchronizing signal discriminating circuit, and 37. Is a switch circuit, 38 is an identification code discrimination circuit, 39 is a switch circuit, 40 is a data value conversion circuit, 41 is a reproduction memory, and 42 is an output terminal. This embodiment performs an operation which is completely opposite to the operation of the embodiment shown in FIG. 1. Therefore, the signal timing of each part in FIG. 2 becomes the same as that in FIG.

2 and 4, the reproduction equalizer 1 reproduced from the magnetic tape 11 as described with reference to FIG.
3 to Digital information signal F of digital video signal format processed by reproduction system digital processing circuit 15
Is connected to the data conversion circuit 4 via the switch circuits 37 and 39.
In addition to being supplied to 0, it is also supplied to the synchronizing signal discriminating circuit 36, and the portion of the synchronizing signal SYN of this digital information signal F is discriminated. Then, according to the result of the determination, the control signal I is generated and output which is in the “H” period for the synchronization signal SYN of the digital information signal F and is in the “L” period during the other periods. The switch circuit 37 is controlled by the control signal I, and is turned on for the "H" period and turned off for the "L" period to remove the synchronizing signal SYN from the digital information signal F.

In this way, the digital information signal E output from the switch circuit 37 is supplied to the identification code detection circuit 38. First, the identification code conversion data FLG is detected, and the identification code conversion data FLG of FIG. The conversion flag added as MSB is detected by the data value conversion circuit 28, and the conversion flag is removed from the identification code conversion data FLG. In this case, for example, in the digital information signal F, the insertion position of the identification code conversion data FLG is set to have a fixed relationship with the synchronization signal, so that the identification is performed according to the determination result of the synchronization signal determination circuit 36. The code conversion data FLG can be detected. When it is determined that the detected conversion flag is "1" and the identification code conversion data FLG from which the conversion flag is removed is the identification code data converted by the data value conversion circuit 28 of FIG. , The upper 2 bits of the identification code conversion data FLG from which the conversion flag is removed are converted to "00" if it is "10" and to "11" if it is "01" to generate the identification code of FIG. The same identification code data K as the quantization bit number (n-1) generated by the circuit 27 is obtained. Then, the same comparison result data D as that obtained by the data comparison circuit 26 of FIG. 1 is obtained from this identification code data K. The comparison result data D is data indicating whether or not the sample data of the reproduced digital information signal is converted by the data value conversion circuit 23 of FIG.

In the identification code detection circuit 38, the identification code conversion data FLG is converted from the digital information signal E.
A control signal J that is "H" during the period of time and "L" during the other periods is formed. Switch circuit 3
9 turns on when the control signal J is "L", and turns off when the control signal J is "H". As a result, the identification code data FLG is removed from the digital information signal E, and the digital information signal C is supplied to the data value conversion circuit 40.

The comparison result data D is the digital information signal C.
2 shows the sample data converted by the data value conversion circuit 23 in FIG. 1, and the data value conversion circuit 40 reversely converts the sample data indicated by the comparison result data D into the original sample data. The output digital information signal B of the data value conversion circuit 40 thus inversely converted is supplied to the reproduction memory 41, and by the control signal J indicating the identification code data position and the control signal I indicating the synchronization signal position. Only the information signal portion is sequentially written, read as the original digital information signal A, and output from the output terminal 42.

As described above, it is possible to surely reverse the original digital information signal into an arbitrary digital information signal which has been digital video signal formatted so that an erroneous synchronizing signal or code data will not be lost.

In FIG. 3, both the recording data conversion circuit 5 and the reproduction data conversion circuit 16 of the above embodiment are mounted inside the digital signal magnetic recording / reproducing apparatus, but they should be provided outside. You can

Further, in FIG. 1, the data comparison circuit 29
In the above, the identification code data K is compared with the predetermined values N ₅ and N ₆ in magnitude, but it may be compared with the predetermined values N ₃ and N ₄ .

Further, in FIG. 1, the data comparison circuit 2
Although the comparison result data D and D ′ of 6 and 29 are 1-bit data, they may be data of an arbitrary number of bits.

In the above embodiment, the number of quantization bits of the input digital information signal is equal to the number of quantization bits n of the digital video signal format. Next, the number of quantization bits of the input digital information signal is m (m
≠ n) and the number of quantization bits n in the digital video signal format are different from each other, an embodiment of the present invention will be described.

FIG. 5 is a block diagram showing a specific example of a bit number conversion circuit which is a main part of such an embodiment of the data conversion circuit according to the present invention, in which 43 is an input terminal, 44 is a parallel / serial conversion circuit, and 44 is a parallel / serial conversion circuit. Reference numeral 45 is a serial / parallel conversion circuit, 46 is a bit number conversion circuit, and 47 is an output terminal.

This embodiment also has the same structure as that of the embodiment shown in FIG. 1, but further, the bit number conversion circuit 46 shown in FIG. 5 is provided between the input terminal 21 and the recording memory 22 shown in FIG. Is provided. The bit number conversion circuit 46 is composed of a parallel / serial conversion circuit 44 and a serial / parallel conversion circuit 45, as shown in the figure.

Next, the operation of the bit number converting circuit 46 will be described with reference to FIG. However, FIG. 6 shows the signals of the respective parts in FIG. 5, and the signals corresponding to FIG.

First, in the case where the number of quantization bits m of the input digital information signal U from the input terminal 43 is m> n (where n is the number of quantization bits in the above digital video signal format), FIG. ), The number of quantization bits m
A series of parallel sample data S ₁ , S ₂ ,
S ₃ ,. ． ． This input digital information signal U consisting of is supplied to a parallel / serial conversion circuit 44 and converted into a serial digital information signal V. This digital information signal V is then sent to the serial / parallel conversion circuit 45.
, A series of bits are combined n by n to form n-bit parallel sample data,
As a result, the digital information signal W having the quantization bit number n is obtained.
Is obtained. This digital information signal W is supplied to the recording memory 22 as the digital information signal A in FIG.

The same applies when the quantization bit number m of the input digital information signal U from the input terminal 43 is m <n,
In FIG. 6B, the input digital information signal U is supplied to the parallel / serial conversion circuit 44 and converted into a serial digital information signal V. This digital information signal V is then supplied to the serial / parallel conversion circuit 45, and a series of bits thereof are combined n by n to form parallel sample data of n bits, respectively. A digital information signal W is obtained. This digital information signal W is supplied to the recording memory 22 as the digital information signal A in FIG.

Thus, in this embodiment, even if the number of quantization bits of the input digital information signal is different from the number of quantization bits n in the digital video signal format,
It is possible to record as a digital information signal in a digital video signal format with a digital VTR.

FIG. 7 is a block diagram showing a specific example of a bit number conversion circuit which is a main part of still another embodiment of the data conversion circuit according to the present invention, in which 48 is an input terminal and 49 is a parallel / serial conversion. A circuit, 50 is a serial / parallel conversion circuit, 51 is a bit number conversion circuit, and 52 is an output terminal.

This embodiment also has the same structure as that of the embodiment shown in FIG. 2, except that the bit number conversion circuit 51 shown in FIG. 7 is provided between the reproduction memory 41 and the output terminal 42 shown in FIG. Is provided. The bit number conversion circuit 51 is composed of a parallel / serial conversion circuit 49 and a serial / parallel conversion circuit 50 as shown in the figure. Next, the operation of the bit number conversion circuit 51 will be described with reference to FIG.
Will be explained. However, FIG. 8 shows the signals of the respective parts in FIG. 7, and the signals corresponding to FIG. 8 are assigned the same reference numerals.

Here, when the number of quantized bits of the finally required digital information signal is m and the number of quantized bits in the digital video signal format is n as described above, there are cases where m> n. sometimes m <n,
The operation in the former case of this concrete example is shown in FIG. 8A, and the operation in the latter case is shown in FIG. 8B. In either case, the operation is input from the input terminal 48 in FIG. The number of quantization bits of the reproduced digital information signal U'is equal to the number of quantization bits in the digital video signal format and is n.

Therefore, the reproduced digital information signal U'from the input terminal 48 is converted into the serial digital information signal V'in the parallel / serial conversion circuit 49 in the bit number conversion circuit 51. In either of the above cases. Similarly, the serial digital information signal V'is supplied to the serial / parallel conversion circuit 50 and converted into a parallel digital information signal having a quantization bit number m. In this case, the serial / parallel conversion circuit is used. 5
As shown in FIG. 8A, 0 is divided into m serial bit strings each of which is larger than n, and the number of quantized bits is m.
Parallel sample data S ₁ , S ₂ , S ₃ ,. ． ． The digital information signal W ′ having a quantization bit number m larger than the quantization bit number n in the digital video signal format can be obtained by operating as described above.
As shown in FIG. 8B, the serial / parallel conversion circuit 50 is divided into m serial bit strings each of which is smaller than n, and the parallel sample data S ₁ , S ₂ , S each having the quantization bit number m are respectively divided. ₃ ,. ． ． The digital information signal W ′ having a quantization bit number m smaller than the above-mentioned quantization bit number n is obtained by the operation.

Thus, in this embodiment, the digital V
Any digital information signal in the digital video signal format reproduced from TR can be used as the digital information signal having the desired number of quantization bits.

Therefore, in the digital signal magnetic recording / reproducing apparatus shown in FIG. 3, the data converting circuit explained in FIG. 5 is used as the recording data converting circuit 5, and the data converting circuit explained in FIG. 7 is used as the reproducing data converting circuit 16. By using, it is possible to record and reproduce a digital information signal having an arbitrary quantization bit number.

FIG. 9 is a block diagram showing a main part of still another embodiment of the data conversion circuit according to the present invention, which is 46 '.
Is a bit number conversion circuit, 53 is an input terminal, 54 is a subtraction circuit, 55 is a ROM, 56 is a delay circuit, 57 is an addition circuit,
Reference numeral 58 is a ROM, 59 is a sign bit conversion circuit, and 60 is an output terminal.

In this embodiment, the input terminal 2 is shown in FIG.
A code bit conversion circuit 59 and a bit number conversion circuit 46 'shown in FIG. 9 are provided between the memory 1 and the recording memory 22. The input digital information signal is compressed in the data amount and digital in a digital video signal format. It is to be converted into an information signal.

In FIG. 9, a sign bit conversion circuit 59.
Is composed of a subtraction circuit 54, ROMs 55 and 58, an addition circuit 57, and a delay circuit 56. From the input terminal 53, a digital information signal having a quantization bit number n with the x-th sample data as D (x) is input and supplied to the sign bit conversion circuit 59. In the sign bit conversion circuit 59, the sample data D of the digital information signal is now taken.
If (x) is supplied, the sample data D (x) in the subtraction circuit 54 and the (x-1) th sample data D (x-1) immediately before the sample data D (x) supplied from the delay circuit 56.
The difference data Da (x) from the sample data D ′ (x−1) corresponding to is calculated and output, and is supplied to the ROM 55. In the ROM 55, the difference data Da (x) of the quantization bit number n is the data d of the quantization bit number k (k <n).
It is converted into (x), encoded, and supplied to the ROM 58.

In the ROM 58, the data d (x) is converted,
Data Da '(x) similar to the input data Da (x) of the ROM 55 is generated by decoding and is supplied to the adder circuit 57 to be sampled data D' (x-1) from the delay circuit 56.
And sampled data D ′ with quantization bit number n
(X) is generated. This sample data D ′ (x) is delayed by one sample cycle of the input digital information signal in the delay circuit 56, and is used as sample data for the next sample data D (x + 1) input from the input terminal 53, and the subtractor circuit 54 and the adder circuit. And 57.

In this way, the subtraction circuit 54 obtains the difference data between the input sample data and the sample data immediately before it, and the quantization bit number in the ROM 55 is m.
The data d (x) is obtained by reducing the data amount.

The data d (x) having the quantization bit number m output from the ROM 55 is also supplied to the bit number conversion circuit 46 'similar to that shown in FIG. 5, for example, and is quantized as described above. It is converted into a digital information signal having the number of bits n and supplied from the output terminal 60 to the recording memory 22 in FIG. 1 as the digital information signal A.

FIG. 10 is a block diagram showing the main part of still another embodiment of the data conversion circuit according to the present invention.
′ Is a bit number conversion circuit, 61 is an input terminal, 62 is a decoded bit conversion circuit, 63 is a ROM, 64 is an addition circuit, 65 is a delay circuit, and 66 is an output terminal.

In this embodiment, the decoding bit converting circuit 62 and the bit number converting circuit 51 'shown in FIG. 10 are provided between the reproducing memory 41 and the output terminal 42 in FIG. The digital information signal having the original data amount can be obtained from the digital information signal in which the format data amount is compressed.

In FIG. 10, the decoded bit conversion circuit 62
Is composed of a ROM 63, an adder circuit 64 and a delay circuit 65. Here, the ROM 63 is the ROM 58 in FIG.
The delay circuit 65 has the same function as, and the delay circuit 65 has the same delay amount as the delay circuit 56 in FIG.

The digital information signal of the quantized bit number n from the reproduction memory 41 of FIG. 2 is input from the input terminal 61 and supplied to, for example, a bit number conversion circuit 51 'similar to the bit number conversion circuit 51 shown in FIG. Then, a digital information signal having the same number of quantization bits m (m <n) as the digital information signal formed by the code bit conversion circuit 59 of FIG. 9 is supplied to the decoding bit conversion circuit 62.

Now, the x-th sample data d'of the digital information signal from the bit number conversion circuit 51 '.
If (x) is output, the decoded bit conversion circuit 62
, The sample data d '(x) is
Similar to the difference data D′ a (x) output from the ROM 58 in FIG. 9, the data is converted into the difference data Da ′ (x) and decoded by 63, and is supplied to the addition circuit 64. In the adder circuit 64, the difference data Da ′ (x) and 1 output from the adder circuit 64 and delayed by the delay circuit 65.
Sample data D '(x
-1) and are added, and the data D ′ having the quantization bit number n
(X) is generated. The sample data D ′ (x) is the sample data of the digital information signal having the original data amount, and is output from the output terminal 66 and is also supplied to the adding circuit 64 via the delay circuit 65.

As described above, by using the embodiment shown in FIGS. 9 and 10, an arbitrary digital information signal is compressed in the data amount and recorded and reproduced in the digital VTR in the digital video signal format. You can

In the embodiment shown in FIG. 9, the number of quantization bits of the digital information signal input from the input terminal 53 may be different from the number of quantization bits n in the digital video signal format, or Also in the embodiment shown in FIG. 10, it goes without saying that the number of quantization bits of the digital information signal output from the output terminal 66 can be different from the number of quantization bits n in the digital video signal format. Absent.

In the embodiment shown in FIGS. 9 and 10,
Although the difference from the prediction value by the previous value prediction is encoded by the number of quantization bits smaller than n, the present invention is not limited to this, and other difference encoding method or transform encoding method may be used. it is obvious.

[0069]

As described above, according to the present invention,
Even if the input digital video information signal has sample data with a value outside the range determined by the digital video signal format, the value of the sample data can be converted into the range, and the sample converted into the value within this range Allows you to determine the data. Further, the sample data whose values are thus converted can be converted into the sample data of the original value. Therefore, even if the digital information signal converted so as to be compatible with the digital video signal format as described above is recorded and reproduced by the digital VTR, an erroneous sync signal or code is not obtained, and the digital VTR malfunctions. Does not cause

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a data conversion circuit according to the present invention.

FIG. 2 is a block diagram showing another embodiment of the data conversion circuit according to the present invention.

FIG. 3 is a block diagram showing a specific example of a digital signal magnetic recording / reproducing apparatus using a data conversion circuit according to the present invention.

FIG. 4 is a timing chart showing the operation of the specific example shown in FIGS. 1 and 2.

FIG. 5 is a block diagram showing a specific example of a bit number conversion circuit which is a main part of still another embodiment of the data conversion circuit according to the present invention.

FIG. 6 is a diagram for explaining the operation of the bit number conversion circuit shown in FIG.

FIG. 7 is a block diagram showing a specific example of a bit number conversion circuit which is a main part of still another embodiment of the data conversion circuit according to the present invention.

FIG. 8 is a diagram for explaining the operation of the bit number conversion circuit shown in FIG.

FIG. 9 is a block diagram showing a specific example of a code bit conversion circuit which is a main part of still another embodiment of the data conversion circuit according to the present invention.

FIG. 10 is a block diagram showing a specific example of a code bit conversion circuit forming the essential part of still another embodiment of the data conversion circuit according to the present invention.

[Explanation of symbols]

 1 recording data conversion circuit 16 reproduction data conversion circuit 21 input terminal 22 recording memory 23 data value conversion circuit 24 switch circuit 25 predetermined value generation circuit 26 data comparison circuit 27 identification code generation circuit 28 data value conversion circuit 29 data comparison circuit 30 identification code Additional circuit 31 Switch circuit 32 Synchronous signal generation circuit 33 Synchronous signal addition circuit 34 Output terminal 35 Input terminal 36 Synchronous signal determination circuit 37 Switch circuit 38 Identification code detection circuit 39 Switch circuit 40 Data value conversion circuit 41 Reproduction memory 42 Output terminal 43 input Terminal 44 Parallel / serial conversion circuit 45 Serial / parallel conversion circuit 46, 46 'Bit conversion circuit 47 Output terminal 48 Input terminal 49 Parallel / serial conversion circuit 50 Serial / parallel conversion circuit 51, 51' bit conversion circuit 52 output terminal 53 input terminal 54 subtraction circuit 55 ROM 56 delay circuit 57 addition circuit 58 ROM 59 sign bit conversion circuit 60 output terminal 61 input terminal 62 sign bit conversion circuit 63 ROM 64 addition circuit 65 delay circuit 66 output terminal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Tomiji Okamura, inventor Tomoji Okamura, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa, Ltd. Inside the Hitachi Media Visual Media Research Institute (72) Yuzumi Wataya, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa 292 Hitachi, Ltd. Visual Media Research Laboratories

Claims (6)

[Claims] 1. A data conversion circuit for converting an arbitrary input digital information signal into a digital information signal of a digital video signal format having a quantization bit number n (where n is an integer of 2 or more). A first means for determining whether or not the value of each sample data is within a first range determined by the digital video signal format, and outputting a bit representing the determination result, and a determination result of the first means. Second means for transforming the sample data whose value is not within the first range so that the value is within the first range, and each sample data from the first means And a third means for generating (n-1) bit identification code data by dividing the determination bits of (n-1) each, and whether the value of the identification code data is within a predetermined second range. Judge whether or not Based on the determination result of the fourth means, the identification code data whose value is not within the second range is converted so that the value is within the second range. , And a fifth means for adding a conversion flag indicating the presence or absence of conversion into identification code data having a quantization bit number n, and (n-1) sample data of the digital information signal from the second means. Sixth means for adding the identification code data from the fifth means, and a sixth means for adding a synchronization signal equivalent to the synchronization signal in the digital video signal format to the digital information signal from the sixth means Data conversion, characterized in that the second range is set so that the value of the identification code data output from the fifth means is always within the first range. circuit. 2. The digital video signal according to claim 1, wherein the number of quantization bits of the input digital information signal is different from that of the digital video signal format, and the number of quantization bits of the input digital information signal is converted. A data conversion circuit, characterized in that a bit number conversion means for making the number of quantization bits n of a format is provided, and an output digital information signal of the bit number conversion means is used as an input signal of the first and second means. 3. The eighth method according to claim 1, wherein the data amount of the input digital information signal is compressed.
Means and a ninth means for converting the output digital information signal of the eighth means into a digital information signal of the number of quantized bits n, and the output digital information signal of the ninth means is provided for the first digital signal. A data conversion circuit, which is an input of the means. 4. A digital information signal converted into a signal of the digital video signal format of the quantization bit number n by the data conversion circuit according to claim 1, as an input signal,
A data conversion circuit for converting an original arbitrary digital information signal, wherein the identification code data of the quantization bit number n added to the input digital information signal is extracted, and each sample data of the input digital information signal is extracted. Tenth means for generating data representing the presence or absence of conversion for each, and eleventh means for converting the converted sample data of the input digital information signal into sample data of the original value based on the data. A data conversion circuit comprising: 5. The digital information signal according to claim 4, wherein the digital information signal obtained by the conversion of the second means is a digital information signal having a quantization bit number different from the quantization bit number n in the digital video signal format. A data conversion circuit characterized by outputting. 6. A data conversion circuit according to claim 3, wherein a digital information signal converted into a signal of the digital video signal format having the number of quantization bits n and having a compressed data amount is used as an input signal, and an original data amount is obtained. A data conversion circuit for converting the identification code data of the number of quantized bits n added to the input digital information signal to extract each sample data of the input digital information signal. , 12th means for generating data indicating the presence or absence of conversion, 13th means for converting the value of the converted sample data of the input digital information signal based on the data, and 13th means And a fourteenth means for expanding the data amount of the sample data output from the data conversion circuit.