JPH05258051A - Batch execution device for tile base image rotation, scaling, and digital half-tone screening - Google Patents

Abstract

PURPOSE: To adjust contone through image rotation, anamorphic scaling, and digital half-tone screening which are used when a page description language is executed. CONSTITUTION: A two-dimensional sampling increment is defined in a slow-speed scanning direction so as to rotate the contone image and make the anamorphic scaling effective, and a movement quantity between successive pixels is related to a corresponding pixel-topixel movement quantity in the contone image. A sampling increment is also defined in high and slow scanning directions for a movement quantity between half-tone scaling cells according to a screen angle and screen ruling. To generate output data at each successive pixel position, increment sampling is performed in the contone image to generate a sampled contone value. This value defines a sampling position together with an increment half-tone sampling address. Each title is successively processed in two nested loops and the output data are written at a proper pixel position of a corresponding block.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to electronic images generated during execution of a page description language having the ability to manipulate continuous tone images through image rotation, scaling and digital halftone screening. Regarding processing.

[0002]

BACKGROUND OF THE INVENTION The content of this application is JF Hamilton, Jr.
US patent application of the same date from others, application number 741,877
It is also described in an application entitled "Tile-based processing method for collectively performing image rotation, scaling, and digital halftone screening" (the Japanese application is also filed on the same date).

As an efficient way to convey information to the reader,
Images have always been incorporated into documents. The need for computer manipulation of diversified arrays of image-related applications and the explosive use of personal computers has increased the need for manipulating images in digital form. In particular, the operations often include scaling, rotation, and halftone processing (halftoning).

Document images are often processed by computers called page description languages, which have been in use ever since they began to be used several years ago. The language allows the user to define the objects that appear on the printed page, such as images, and to process the objects in a desired way to position them accurately relative to each other.
The entire page can be properly formed. To provide the user with maximum flexibility in digital image processing, the page description language uses a scaling of arbitrary uniform and anamorphic images within a finite range, arbitrary image rotation, and arbitrary screen angles and screens. It is necessary to support halftone processing in ruling with floating point precision. Ensures that document images are properly "aligned" with other objects on the page
Therefore, the image processing function must be performed very precisely. Otherwise, artifacts or other errors will appear on the page when printing.

There are currently several different page description languages in use, among which traditionally they have been implemented when performing image scaling and image rotation.
There are significant limitations to the two basic approaches.

In particular, one basic approach that is widely used in the art depends on storing the entire image in a random access frame memory and operating on individual bits of the image located in that memory. To be done. This approach (hereinafter referred to as the "full-frame memory" approach) uses bitwise sequential reading of the image using the appropriate incremental memory address to produce properly rotated image data that should produce a rotated image. Processing can be included. As is known in the art, scaling can include, for example, adding data to or removing data from selected pixel locations in memory to change the scale of the image as desired. .. This holistic approach requires a frame memory of sufficient size to also provide relatively fast read / write random access. Unfortunately, for currently available output writers, ie, 8 x 10 inch (20 x 25 cm) continuous tone images printed at 300 dot / inch resolution available on laser printers, the frame memory will not , About 7 megabytes will be required. Memories of that size tend to be very expensive, especially when manufactured with currently available high speed random access memory (RAM) circuits.
Due to the exorbitant price of the frame memory,
Not available for low cost printers. Moreover, even with this large amount of fast memory, image scaling and image rotation are often performed in software-based processes running on microprocessors, which tend to be relatively slow for whole images. There is.

In terms of practical memory limits, the technique is "tile based" in scaling and rotation.
It has also been taught that the alternative approach can be pre-formed alternately. Here, the image is first divided into small uniform areas called "tiles". Then, each partitioned tile is processed separately and appropriately. Usually, one tile is significantly smaller than the whole image. Once the tiles have been processed to produce an output tile, the output tile
Then, it is written to a spatially corresponding area such as an output buffer. All tiles are processed until the entire image is formed of output tiles.

Given the two approaches given, tiling offers several significant advantages. First, by significantly reducing the size of one tile from the size of the entire image, the memory requirements for fast frame memory are reduced. For example, it takes 7 megabytes to store an entire image, but about 10 bytes are currently needed to store one single tile being processed.
It seems to be reduced to kilobytes. Then, there is no need for a large-scale full-size high-speed frame memory, the system memory can be simplified, and the price of the system memory is considerably reduced. An image size output buffer would still be needed, but
It would no longer be necessary to act as a fast random access memory. As a result, the buffer can be manufactured with a relatively slow and inexpensive memory circuit. Furthermore, by processing one single tile at a time, the data transfer involving frame memory is reduced to the data required only for a particular tile rather than the tile of the whole image in the "full frame memory" approach. . As a result, the operations required to perform that memory transfer are greatly simplified and become insignificant in the overall tile-based processing. Moreover, by processing only a relatively small amount of data at once, certain hardware circuits can be easily manufactured to process the entire tile at high speed.
This allows the whole image to be rotated and / or scaled faster than the speed of the "full frame memory" approach. Finally, tile-based implementation is suitable for pipeline and parallel processing. Appropriate tile processing hardware is copied and operated on this parallel and time alternating basis by this process to batch process several tiles at once. This further accelerates the overall processing of image scaling and / or rotation. Conveniently, the means cost:
Consistent with performance trade-offs, it can be easily scaled to larger sizes to achieve desired throughput levels.

[0009]

Unfortunately, despite the advantages exhibited by tile-based scaling and rotation, the tile-based approach results in each output tile, especially when used for halftone processing. Must be very accurately placed in the output buffer. Otherwise, there will be visible scratches on the image. In particular,
It has been observed experimentally that in a halftoned image with a 50% tint factor, a one-pixel offset in the halftoned pattern between adjacent tiles causes visible artifacts to appear in the image. The artifact has a "zig-zag" shape along the border tiles of the entire image. As a result, if the image is then halftoned, a screener operating on that tile is required to retrieve each tile from the output buffer, screen the tile and return it to the output buffer with 1-bit precision. .. Achieving and maintaining this high accuracy throughout the image halftoning process has proven to be very difficult in practice.

At first glance, one might think that the precision can be relaxed and that the "zig-zag" pattern can be eliminated by properly leveling the boundaries of the halftoned tiles. In particular, the leveling, which can be implemented with low-pass spatial filtering, probably reduces the visible impact of rounding errors and reduces the resulting tile misalignment. The misalignment occurs when the floating point address value is divided into real integer addresses and is not leveled. The real integer address is then used to address the output buffer where the halftoned tile is being reassembled. Proper experimental observations have shown that the filtering reduces visible tile misregistration, but, unfortunately, the filtering decomposes and destroys the halftone dot structure of existing images. Therefore, tile boundary filtering cannot be a viable solution, and it is absolutely necessary to maintain 1-bit precision in order to perform tile-based image processing.

Also, apart from tiling, commercially available screeners are expensive, require large amounts of memory, and often do not have the ability to perform image scaling and / or rotation.

In addition, image scaling and rotation are often performed in image processing devices currently available as "font end" operations, ie, circuits located near the image scanner in a series of image processing circuits. On the other hand, screening is performed as a "back-end" operation, i.e. in the circuitry associated with the output writer. Both manipulations generally have little knowledge of the other manipulations, and as a result artificial impurities and other adverse consequences often appear in the image. Since the page description language performs post-processing, that is, the language processes "while looking at an image",
The language does not provide the opportunity to optimize the image for operations most recently performed on it, such as "font end" scaling or rotation. Therefore, the specific implementation of the language, as it is currently used, does not eliminate the adverse effects of moire patterns, aliases, etc. The adverse effects result from the interaction of similar comparable properties associated with the halftone processing process and the output writer with properties of "font end" operations such as sampling of frequency and pixel placement, for example.

In addition, commercially available screeners also tend to be extremely slow. Therefore, when the screener is used to implement a page description language, the resulting processing power is significantly slower than the output writer speeds currently in use, such as 70 pages per minute (ppm) and above, which is significant. It will be an obstacle. Extreme slowness can be frustrating for users. The user would then be willing to give up and not incorporate the image into the document, rather than waiting for the time required for the image to be processed and printed.

In spite of the above basic problems, the inherent advantages of the tile-based approach, especially those resulting from the reduced size of the frame buffer and the reduced price, strongly support its use.

Therefore, very accurately and at low cost,
There is a need in the art for tile-based techniques that can perform image rotation, scaling and halftone processing. In addition, there is a particular need to approach the processing power of currently available output writers by considerably speeding up the processing power of page description languages to perform tile-based scaling, rotation and halftone processing.
Advantageously, incorporating the technique into an output writer
The person in charge will expedite the use of the document image.

Accordingly, it is an object of the present invention to provide an apparatus and method for performing image scaling, rotation and halftone processing of a continuous tone (contone) image in a post-processing environment at a low cost but very accurately. To provide.

A particular purpose uses tiling in the apparatus and method to advantageously reduce high speed memory requirements.

Another particular object is to provide a device that will contain tile placement errors in the output buffer within one bit of precision throughout the halftone processing operation.

Yet another particular purpose is to sufficiently accelerate the processing power of page description languages, image scaling, rotation and halftoning at speeds roughly comparable to the processing power provided by many currently available output writers. It is to provide the apparatus and method for performing the processing.

[0020]

Generally speaking, these objectives, in accordance with the teachings of the present invention, are based on a contone image for a corresponding movement between two adjacent pixel locations within an output image block. Is accomplished by first defining a pixel sampling increment that specifies the incremental movement of successive contone tiles between successive sampling positions.

Next, in response to the increment, (a) an address indicating the incremental movement amount of the block is generated, and (b) a contone image that produces a series of output pixel positions is sampled and addressed. Create one sampled contone value at each output pixel location to produce a plurality of sampled contone values, and
(C) In response to the sampled contone value and the predefined pattern, one corresponding halftone output value is sequentially created for the addressed output pixel position, and a plurality of halftone output values are generated. Create. next,
If each halftone output value is for a pixel location within the contone tile, it is written to the corresponding addressed output pixel location within the block.

In particular, based on the detailed teachings, the method of the present invention effectively partitions the contone image into a series of non-overlapping tiles and the output image into a series of blocks. Based on processing. The latter usually overlaps based on the angle φ (rotation angle) at which the contone image rotates. As illustrated, the block size is fixed at a position of 32 × 32 in the case of enlargement scaling, and is variable to some extent in the case of reduction scaling. The tiles are determined based on the anamorphic scale factors α and β and the rotation angle such that the tiles have a maximum size that fits within the block when rotated within the corresponding block.
Incremental pixel sampling coordinates include, among others, rotation angle, anamorphic scale factor, screen angle θ,
Determined based on tile and block size. As a result, for continuous pixel movement within a block with respect to pixel X pixels, the halftone output data contains, for each pixel in the block, the minimum size in the contone image that completely contains the corresponding contone tile. It is calculated from the contone data contained in the box. Incremental sampling coordinates for the amount of movement of the corresponding increment pixel in the halftone screening pattern are also defined to produce consecutively sampled halftone values for each pixel in the block, specifically based on screen ruling and screen angle θ. It Increments are defined not only between successive tiles of a halftone screen pattern and between successive blocks of an output image, but also for the amount of movement between successive tiles of a contone image. Once all of the increments have been selected, each tile of the contone image is processed serially to fill each successive corresponding block with halftone output data. The process increments the current output block on a pixel by pixel basis to create a series of output pixel locations. It also incrementally samples from the contone image to produce one sampled contone value at each output pixel location and a plurality of sampled contone values. In addition, incremental sampling is performed from the halftone pattern, and one halftone output value corresponding to each output pixel position is sequentially created according to the sampled contone value to create a plurality of halftone output values. The increment process, the incremental contone process, and the halftone sampling process occur in lockstep, and after the address is generated for each successive pixel of the current block, the corresponding sampled contone value and the corresponding halftone output value are generated. . This process is continuously performed along each row of the current block in the fast scan direction. Also, the process continues in the slow scan direction row by row within the block until the current block is completely filled with output halftone values. Halftone data is only written to the buffer at that location in the current block with the corresponding sampled contone value in the current tile being processed. Zero values are written in all other locations. When the current contone tile is completely processed, the buffer contents are transferred to the output block of the page buffer. The output block is located at a position corresponding to the spatial position of the current image in the output image. Once the current contone tile is processed, the next contiguous contone tile formed by the tile increments is processed to produce output halftone processed data for the next block in the output image. Similar processing is performed for each successive contone tile. To ensure correct positioning of all contone tiles, the starting position of each consecutive contone tile is modified by the position offset value that exists between the block edge position and the corresponding rotated contone tile corner. . Contone tiles are processed sequentially along the row, ie, in the fast scan direction, and row to row, ie, in the slow scan direction, throughout the contone image.

Halftone data can be generated by sampling in either the halftone reference cell or the threshold matrix. In the former approach, the halftone reference stack contains multiple halftone reference cells, each cell typically containing a different depiction of halftone dots from 0% dots to 100% dots. Each sampled contone value selects the particular halftone reference plane to be sampled by the appropriate pixel address to produce the corresponding sampled halftone value. In the latter approach, the threshold matrix is also sequentially sampled with the appropriate pixel address to produce the sampled current threshold value. The threshold value is compared to the corresponding sampled current contone value to produce a halftone output bit having a value determined by the result of the comparison. Halftone sampling occurs independently of the halftone plane or threshold matrix, and generally in a different direction than sampling through the contone image. However, both sampling processes are mutually performed in lockstep.

The invention is a two-chip architecture,
In particular, it is conveniently implemented using a microcomputer combined with dedicated hardware circuitry. Dedicated hardware circuits are referred to below as tile / pixel processor (TP
P). The microcomputer is able to handle tile and block sizes, pixel sampling and tile increments, etc.
After setting various parameter values that are fixed throughout the contone image, the starting position of each successive contone tile and output block is calculated. The microcomputer loads the pixel sampling increment into the TPP. Then, the start position is determined for each contone tile and sent to the TPP, and the processing instruction for the contone tile is sent to the TPP. The TPP, through an internal tile processor, generates contone and halftone pixel sampling addresses for each successive output pixel of the output image. The address is used sequentially to access the associated contone and hardware reference memory to produce each sampled contone value and corresponding halftoned output value. As the TPP processes each contone tile, the microcomputer transfers all halftone data produced by the TPP to the corresponding block in the page buffer. Then it updates the parameter value stored in the TPP to change the starting position of the next consecutive tile. After that, the processing start command is issued to the TPP to process all contone tiles. In essence, the combination of the microcomputer and TPP implements the nested processing loops together, and the TPP implements two nested loops in hardware.

The present invention advantageously incorporates parallelism, no matter how the architecture of the present invention is implemented, so that processing power is scaled higher to the desired level. It has the feature. To that end, the two-chip architecture of the present invention is easily extended, using multiple TPPs connected and controlled by a common microcomputer,
Parallel processing is performed. Each TPP will be the structure by which the microcomputer independently processes certain corresponding non-overlapping portions of the input contone image, eg, horizontal strips. The microcomputer issues instructions to all TPPs to process each image portion in alternating time, essentially in parallel to each other. While each TPP is performing processing,
The microcomputer decides a part of the output buffer,
The data generated by the TPP and temporarily stored in an appropriate first-in first-out manner will be transferred to the output buffer at the end of the process. Active TP
As the number of P's increases and the parallelism increases, so does the throughput.

After reading the following description, those skilled in the art will appreciate that the inventive technique can be used in a wide variety of image processing applications for performing image scaling, rotation, and halftoning in bulk at relatively high speeds. You will soon recognize what you can do. One of the outstanding applications of the present invention is a page description language in a post-processing environment of a digital image processing system that is embedded within the output writer used by the system rather than within the preceding image processing equipment forming the system. For the sake of brevity, the invention will be considered in the context of the above.

In order that the inventive technique and apparatus may be better understood, the following discussion is conducted at various stages. First, an outline of an image processing system that implements a page description language according to the present invention will be briefly described. The inventive process for collectively performing image scaling, rotation, and halftone processing using various graphical depictions will now be described. Thereafter, embodiments of image processing systems incorporating the inventive techniques of interest will be described in detail. Then, two chips of the technique (eg, microcomputer
/ ASIC) Conduct a detailed study of implementation. In the latter examination,
First, a high-level pseudocode is used to provide a functional description of operation by both chips, and then, for example, an ASIC (application specific integrated circuit app) that implements a salient part of the technique.
lication specific integrated circuit) Describes a dedicated hardware circuit that is supposed to be used by specifying a chip.

[0028]

EXAMPLES A. Page Description Language Implementation System FIG. 1 illustrates image scaling,
1 is a very high level simplified block diagram of an image processing system 5 for implementing a page description language (PDL) that provides rotation and halftone processing capabilities. As shown in the figure,
Input data goes to system 5 via lead 7.
The data is formed by a series of PDL commands that are each followed by the associated first image data or contone image data. Each command specifies how to process the data that immediately follows and how to print to the output page. The consecutively generated PDL commands form a data stream with the accompanying data, which data stream travels via lead 7 to processor 10. The processor 10, which has the PDL processing circuit 13 and the output buffer 17 by itself, executes each command by performing the corresponding image processing operation on the attached data through the PDL processing circuit, and then executes the command. , Write the obtained processed image data in the output buffer. Then, the contents of the buffer are read in a raster manner and applied to the digital marking (writing) engine 25 via the lead wire 21. The engine is
In the simplest form, a single write spot (output bit)
Is written to the output page for each corresponding bit applied to the input. Normally, the engine 25 has 300 dots / inch (about 11
It is a laser printer with a vertical and horizontal output writing pitch of 8 dots / cm or more. Printed page 30, which is typically a hardcopy output of paper, has the contents of output buffer 17 produced by engine 25.

The PDL allows the user to define the objects that appear on the printed page 30, such as images, and to process the objects in the desired manner and position them accurately relative to each other to ensure that the entire page is It can be formed appropriately. To provide the user with maximum flexibility in digital image processing, PDL is capable of scaling any uniform and anamorphic image within a finite range, rotating the image at any angle, and at any screen angle and screen ruling. It is necessary to support the halftone processing of with the precision of floating point.
To ensure that the document image is properly "aligned" with other objects on the page, the image processing function must be performed very precisely. Otherwise, artificial impurities or other errors will appear on the page when printing.

For example, a series of PDL commands is used to position the input contone image 8 in the middle of the output page after scaling 0.5 inches in each direction, rotating about 45 degrees, and halftoning. The output image 33 can be specified by creating it on 30. The command can also specify that the letters "A" and "b" of the text be placed on either side of the output image 33, with "A" scaled by 2 both vertically and horizontally. In processing the PDL command and associated data, the PDL processor 13
It operates on the contone image data to produce the desired scaled, rotated and halftoned output image and writes the result to the output buffer 17. Processor 13
Works with the first data defined by the PDL command. The output buffer 17 is large enough to store halftone processed image data for 25 pages of engine.

The present invention is not in the specific commands used for the PDL and the manner in which each PDL command and its associated data is generated, but rather for incorporating image scaling, rotation, and halftoning functions into the PDL. It is in the way these functions are implemented. The following discussion focuses only on image scaling, rotation and halftoning.

B. Process of the Invention For the tile-based process of the invention, first consider the overall quality with respect to FIGS. 3-6, 7, 8 and 9. The various tile-based operations that collectively form the inventive process for performing image scaling, rotation, and halftone processing of system 5 are shown in FIGS. FIG. 2 shows that it is composed of FIGS. The spatially corresponding and illustrated contone box and writing of output data to the various contone boxes and output blocks is shown in FIG. Detailed views of a single contone box and corresponding output block are shown in FIGS. 8 and 9, respectively. Please refer to all of the above drawings simultaneously throughout the discussion below.

The inventive process is first based on the process of smoothly partitioning the entire input contone image into adjacent tiles of the same size. Contone image of Figure 7
301 is a contone tile 310 ₁ , 310 ₂ , 310 ₃ ...
・ It is divided into · and spreads horizontally and vertically over the entire contone image. As an enlarged view, the representation 210 of FIG.
215 ₁ , 215 ₂ , arranged in a matrix ...
Shows an image portion 215 which is formed by 215 ₉ 9 contone tiles. Once the image is segmented, each contone tile is serially processed to produce an output, eg, a halftoned output bit value. This output bit value is written as a tile for each tile in the corresponding square block of the output buffer. At this point, the blocks 371 ₁ , 371 ₂ , 371 _3, ... Of the output buffer 17 of FIG.
・ The output images 33 are collectively formed, and the corresponding output tiles 375 ₁ , 375 ₂ , 375 ₃ that are adjacent to each other smoothly are ...
Has an output bit value of. Each output tile has output data for a corresponding single contone tile. Through the following examination, note that a contone tile refers to a tile that collectively forms a contone image, and an output tile refers to a tile that collectively forms an output image formed by the output buffer 17. There must be.

Each block of the output buffer has a fixed size, and has 32 × 32 positions as shown in the figure. There is another block for each contone tile. Since the contone image is rotated on the output page by the desired angle φ, the tile rotates through φ degrees in the output block. This is seen in the representation 210 of FIG. 2 of the output block overlaid on spatially corresponding tiles, and in the skewed output image 33 of FIG.

As will be discussed in detail below, during initialization:
The size of each tile is set to the maximum value that fits within the output block. The size of each tile is determined by the following three factors. That is, the scale factors (α and β) in the low-speed and high-speed scan directions, the rotation angle (φ) of the contone image, and 32 as shown in the figure.
× 32 The output block size is fixed at the output position. Since each output tile rotates within the corresponding block, blocks 217 ₁ and 217 ₂ shown in FIG. 3 having the output data of adjacent contone tiles 215 ₁ and 215 ₂ .
Proximity blocks, such as, will overlap in the output buffer. The overlap angle between adjacent blocks is governed by the size of the angle φ at which the contone image rotates. As the angle increases, so does the amount of overlap. Overlap region of the block 217 ₁ is generated in the hatched area 219. Similar areas occur in each of the other blocks. The overlap ensures that all adjacent tiles are adjacent and in correct alignment with each other.

Depiction 220 shows one contone tile shown, for example tile 215 ₇ overlaid on the corresponding output block, block 217 ₇ . As can be seen from the figure, the direction of the tile is fixed in the rotation angle of the block.

With this method, contone tiles are defined,
When tilted with respect to the block, the contone image is sampled in two dimensions, effectively providing the contone data required for each block from the associated contone tile. Sampling is a contone surface,
That is, since it is done in plane 301 of FIG. 7, the increment of the two-dimensional sample in the fast and slow scan directions (v and u) is set. Also, as will be described in more detail below, during initialization another continuous contone sample is generated for each output position of each output block containing the output data for the tile of the contone image. The contone value area of the contone image is hereinafter referred to as a contone box (distinguished from the output block). The region of contone values is fully sampled in defined increments in a raster fashion, producing a large number of consecutive contone samples.
The large number of consecutive contone samples are processed, such as halftoning, to produce a sufficient number of consecutive output values to completely fill the spatially corresponding output blocks of the output image. Each sampled contone value is generated and processed, and the resulting halftoned output value is
It is written to the corresponding output position of the output block. In this regard, contone tiles 310 ₁ , 310 ₂ , 310, respectively.
Contone boxes 320 ₁ , 320 ₂ , 32 including ₃ ...
0 ₃ ... Are continuously sampled in a raster manner to produce a series of contone samples in each box. The sample is processed box by box in halftone screening to produce corresponding halftone bits (writing spots). This continuous halftone bit is then the appropriate continuous position of the corresponding output block, ie,
Written to the output blocks 371 ₁ , 371 ₂ , 371 ₃ ... FIG. 7 shows the spatial correspondence between the contone box and the associated output box. Specifically, the contone values of the sampled contone boxes 320 ₁ , 320 ₂ , 320 ₃ are added to the halftone screener 340 by lines numbered 331, 332, 333, respectively.
The line allows the contone samples made in each of the three contone boxes to be visually distinguished. The halftone screener 340 operates on the contone samples generated for each box of interest and provides another halftone bit pattern in the manner discussed below. Line 331
, 332, and 333, the halftone bit pattern obtained from the contone sample is the halftone screener.
340 advances through each line 341, 342, 343 to clipping logic 350. The output bit 4 provided by the logic is written to the output buffer 17, as discussed below. In particular, the corresponding output blocks 37 are indicated by the lines numbered 361, 362 and 363 respectively.
Written in 1 ₁ , 371 ₂ , 371 ₃ . Thus, the resulting contone sample from contone box 320 _1, 320 _2, 320 _3, creating a series of corresponding screen training output value, that value, the corresponding output block 371 _1, 371 ₂ , written in 371 _3. Each contone box of contone image 301 is processed sequentially to write the output data to the corresponding output block. The writing is continued until the entire output block is filled.

Output data is only needed for each block of the output buffer to fill the area of the corresponding contone tile. Since contone tiles based on rotation angle cannot completely occupy the contone box, use clipping to define these contone samples within the contone tile that is about to be processed, as defined below. And from the remaining contone samples of the contone box that are effectively ignored, produce output values that are stored in the output tiles in the output block. These latter values produce output data in the overlap areas of adjacent output blocks, so a zero value is written to the output buffer at the corresponding output location. In its simplest form, clipping can be thought of as a simple switch that adds either a halftone bit value or a zero value to the write to each output position of the output block.
Switches 351, 352 and 353 are used for the halftone bit value appearing on line 341, 342 or 343 or line 345.
It provides the clipping function to the output blocks 371 ₁ , 372 ₂ , 371 ₃ by sending the zero value applied to each line 361, 362, 363. The choice of halftone bit or zero value (switch setting) for the output block is based on the coincident values of the Cartesian clipping coordinates (K and L). The coordinates are defined and scaled so that the "unit" distances of the variables K and L are equal to the distances of the edges of the contone tiles, given the current tile size. Specifically, K and L are both 1 in the contone tile,
It is 0 or 2 outside the tile. The clipping variable effectively defines the boundaries of each contone tile. Further, the clipping variable causes a zero value to be written in all the remaining areas of each block while embedding the area of each output block occupied by the corresponding output tile with output data. The processed contone sample data, that is, the bits after the halftone processing, are written to spatially corresponding output positions within one block. The values of K and L are both 1 for the block, in other words 1 only in the output tiles contained in the output block.
And not 1 in the overlap region. K and
The value of L is appropriately raster-incremented so that the address of the current output location written to the current output block is raster-incremented.

As shown by the sample line 223 in the representation 220 of FIG. 3, the contone sampling direction is determined by the horizontal and vertical directions of the output buffer, but the rotation of the contone image causes an angle for each contone tile. Is attached. Since this value is the input contone value that is actually sampled, sample line 22
3 _1, 223 _2, 223 ₃ inclined sampling by · · · · 223 _n is carried out in a suitable sampling increments throughout the input contone image, the data from each image tile, such as tiles 215 ₇ each contone box Ask. In the raster scheme, sufficient contone sampling occurs to generate data at all output positions of each output block, so that the sampling extends beyond the perimeter of each tile to fill the entire contone box. At this point, the sampling lines 223 ₁ , 223 ₂ , 223 ₃ ... 223 _n (
Which together form line 223) produces the contone sample. An "X" is attached to each of the samples throughout the contone box 320 ₂ including the contone tile 310 ₂ shown in FIG. Sampled values, block 371 ₃ including a region 377 of the peripheral shown in FIG. 9
Provide enough output data to fill the entire output block such as. Output block, such as block 371 ₃ is filled in the direction indicated by the axes p and q in a raster fashion. At this time, the data is written to each of 32 × 32 fixed output positions (each position is indicated by a solid dot) starting from the upper left corner of the block and continuing to the lower right corner. Due to clipping, zero values are written to output positions in the surrounding area 377 (cross-hatched for clarity) within the block. At this time, halftoned bit value is written to remaining positions entering the output tile 375 _3. Similarly, the representation 210 of FIG.
The contone sampling of the contone tile 215 ₇ and the spatial correspondence between the tile and the output block 217 ₇ are shown.

In the case of a contone image, sampling begins at the upper left corner (ULC) of the contone box corresponding to the top output block of the output image and is done vertically, downwards through that box. The block itself is located in the ULC of the output image. After one contone box is sampled, sampling starts at the ULC of the next contone box, and so on. Appropriate variables are used to maintain the ULC address of the current contone box and are incremented appropriately by the fast and slow scan increments,
Start sampling from ULC of each continuous contone box. In this way, output data is generated that fills successive output blocks such as 217 ₁ , 217 ₂ , 217 ₃ forming the output image portion 217 of FIG. As a result, the output image is constructed on a block by block basis, with the output data providing the output tile data for each block.

The representation 230 of FIG. 4 details two-dimensional contone sampling. The two sampling lines 223 ₁ and 223 _{1 + 1} in the example shown are shown in detail. Variable, pi
xel_v and pixel_u store the address of the current sampling position of the contone image with respect to coordinates u, v. The variable is the pixel sampling increment Δ
pixel _u _fast, △ pixel _v_fast, △ pixel _u
_Slow and △ pixel _v _slow (in this document, △ u
_Fast, Δv _fast, Δ_slow and Δv _fast) are appropriately incremented in the fast and slow scan directions. The increments are actually all "△" values, but are set during initialization to create the correct number of contone samples and fill each contone box. As shown in description 230, the contone sampling is
Beginning from the left start point of the sampling line, such as line 223 _1, a fast scan v and u pixels sampling increment, △ pixel _v _fast and △ pixel
Continuously increment the sampling address by _u _fast,
Advances to the next position from the position with the line, the sampling points 231 _1, 231 _2, 231 _3, 231 ₄ and 23
1 ₅ creates an evenly distributed sequence. When the last sampling position has reached the sampling line, such as position 231 ₅ of FIG example, it is the sampling addresses,
Slow scan pixel sampling increment value Δv_slow
And Δu_slow are incremented to start sampling from the leftmost position of the next consecutive sampling line, ie, line 2231 _{+ 1} , and so on. The resulting contone sample points are indicated by an "X" on each sample line.

As shown in the representation 240 of FIG. 4, each sampled contone value simply serves as the address of the front memory, ie, the halftone reference stack for selecting a particular halftone reference cell. Stack242
Is stored in one memory (not shown),
It stores a predefined number, namely 256 different cells. Each cell has a bitmap of the particular halftone dots formed by the 64 × 64 pixels in the illustrated example.
In the stack 242, the dot size, as shown by the dot profile 245, cell 242 ₀ 100% dot from zero dot of cells 242 ₂₅₅ (i.e., the dots fill the cell completely) gradually changes into. Figure cell
242 ₄₇ and 242 ₁₈₁ are each a medium-sized dot 24
Stores 5 ₄₇ and 245 ₁₈₁ . Although the dot pattern is shown smoothly, it is actually quantized. Once the desired cell is selected, the cell is oriented in the direction dictated by screen angle θ using two-dimensional fast and slow scan increments determined by the screen angle, screen ruling and output writing (laser) frequency. It is sampled so that the output block contains the proper number of halftone dots.

The contone / halftone dot sampling proceeds to the lock step in a state where each sampled contone value produces a sampled halftone dot value. However, the direction and increment at which halftone sampling occurs is completely independent of the direction and increment at which contone sampling occurs.

[0044] Here, for convenience of explanation, it is assumed that the current contone sample values to select a halftone reference cell 245 _47. Further, the screen angle θ is assumed to be about 10 degrees. Partial screen 24, as shown in drawing 250 of FIG.
Halftone dot screens such as 8 have a seamless 2D halftone dot pattern (seamless doubly per
iodic two-dimensional halftone dot pattern). The depiction is the output block, in particular, a block 217 ₇ superimposed on the halftone screen 248. Halftone dot sampling is performed by a two-dimensional raster method in the fast and slow scan directions of the screen. The direction is parallel to the output buffer. But,
Since the sampling is actually performed in the selected halftone dot cell, the tilt sampling is performed in the cell in the minus direction of the screen angle. Due to the periodicity of the screen pattern, once the sampling line hits the edge of a halftone cell such as 251, 252, 253 or 254 shown in drawing 260, the line is simply
Move to the opposite edge and restart the next sampling from there.

At this point, the sampling line 257 in the illustrated example
_m and 257 _{m + 1,} the process proceeds halftone reference cell 242 _47, creating a series of halftone sampling points along each line. In a manner similar to contone sampling, halftone reference cell sampling is done along axes x and y in an incremental manner along each halftone sampling line. Two variables, pixel_x and pixel_y, store the address of the x and y coordinates of the current sampling position of the halftone reference cell. The variables are Δpixel _x _fast and Δpixel _y _fas, which are pixel sampling increments.
t, △ pixel_x_slow and △ pixel_y_slow (in this document, △ x_fast, △ y_fast, △ x_slow and △ y
(Also referred to as _fast), appropriately incremented in the fast and slow scan directions. The increment is set during initialization to create the correct number of halftone dot sample points to fill each output block. As shown in drawing 260, contone sampling starts from the left start point of the sampling line, such as line 257 _m, and samples by Δy _fast and Δx _fast, which are sampling increments of fast scan y and x pixel l. The address is continuously incremented to advance from one position of the line to the next position, and the sampling point 261
_1, 261 _2, 261 _3, 261 including _4, produce equally distributed sequence. When the last sampling position is reached, the sampling address is incremented by slow scan pixel sampling increments Δy _slow and Δx _slow to the next consecutive sampling line, ie, line 257 _{m + 1} . Sampling is started from the leftmost position, and so on. The resulting halftone sample points are indicated by an "X" on each sampling line. If any of the sample points are on or in the halftone dot of the reference cell, is the corresponding halftoned output value 1?
Is. The resulting output values of 1 or 0 are the halftone processed bits that have been screened and are stored in the output buffer as clipping spot values in the output image via clipping logic.

The process of halftone sampling is well known and is described in US Pat.
918,622 (issued April 19, 1990 to EMGranger and others ---- hereafter referred to as the '622 Granger et al., Which is assigned to the assignee of the present application). Disclosed in. Reference is therefore made to the '622 Granger et al. Patent for a deeper insight into the process.
If desired, a wide range of other known halftone processing processes may be used, as it is not critical to use the particular halftone processing process of the present invention.

Finally, the halftone bits produced by the halftone screener are applied via clipping logic as shown in the representation 270 of FIG. As mentioned above, clipping is a “valid” halftone bit, that is, the halftone bits that are located on or in the output tiles of the output block and are written to the output buffer and the rest of the block in the block that is set to zero in the output buffer. It is used to distinguish from the halftone bits of. As symbolized by representation 270, the screened halftone bit is applied to one input of switch 275 via lead 274. The zero value is applied to another input of the switch via lead 278. From the AND combination of clipping variables K and Y,
Based on the value produced by AND gate 273 on lead 276 and applied to the control input of switch 275, the switch directs the halftone screening bit or zero value to output lead 277. Lead wire 277
The bits appearing at are stored at sequential addresses in the current output block of the output buffer. Lead wire 27
The values of the clipping variables K and L appearing at 1 are both 1 and the screened halftone bits produced by the halftone screener are valid. Therefore, AND
The output of gate 273 is high for that bit, but zero otherwise.

As discussed above, the contone sampling and screening operations occur in lockstep, or unison, with each operation simultaneously creating a corresponding sample point. Contone image
In order to clearly visualize the pixel increments that simultaneously increase in the halftone reference plane and the output image plane (output buffer), and the resulting correspondence between pixel locations, these vertically aligned pixels are shown in FIG. Aspects need to be considered. Incremental sampling distance is contone image plane 630
And, with proper selection in the halftone reference plane 620, given the contone image rotation angle φ, halftone screen angle θ, and scale factors (α and β), the current output position of the output image plane and Together, the corresponding current sampling positions of the contone and halftone reference planes always remain on a common line. Specifically, it remains on line 685, which runs vertically across all three sides. As sampling progresses to another point on each of these three planes, line 685 shifts its position so that it crosses another set of these three vertically positioned points, once on each plane. .

Output image 6 such as blocks 651 and 654, which will contain the output data for tiles 661 and 664.
For any of the 40 blocks, the process of the invention operates and the corresponding boxes of data, namely the contone image plane and the halftone reference plane boxes 633 and 623, as shown by the line 670. To sample via. The sampled contone value is
Used to select the particular halftone reference plane to sample, as indicated by dashed line 683. The sampled halftone bits are used to fill the output locations within the corresponding output tiles 661 and 664 of the output image plane 610, as shown by dashed line 687. The process of the present invention fills a contiguous block of the output image plane starting from the block in the upper left corner of the output image 640 and processes it through the corresponding data boxes in the contone and halftone reference planes to produce the right image of the output image 640. Go to the bottom corner. This process continues until the writing of the image is complete.

C. Image processing using inventive techniques
System A qualitative description of the process of the invention has been given above. Figure 1
2 and 13 show a high level block diagram of an image processing system 700 implementing the process as part of the image processing function. FIG. 11 is composed of FIGS. 12 and 13.

As shown, the system 700 comprises a command control processor 701, an image data decompressor 720, an image processing pipeline 730 and an output buffer memory management unit 760, all interconnected by a bus 750. There is. System 700
Receives input image data in the form of a packet with an appropriate header 750 on input bus 705. Each of the packets includes one or more specific image processing instructions with associated image data, the associated image data typically being compressed. The command control processor 701 controls the system 700 as a whole. At this point, the processor 701 reads the header of each incoming packet and sends the packet to the appropriate destination for further processing. In the case of image rotation, scaling, or halftone processing, the processing is performed by the processor 701 itself, the decompressor 720, or the image processing pipeline 73.
You can start elsewhere, such as 0. The output buffer / memory management unit 760 is provided for temporary storage and / or local use of processed image data.
Alternatively, multiple pages of random accelerator memory (RAM) are provided as a frame memory for holding the output image data of the marking engine.

Command Control Processor 710
The register 711, microcomputer 713, ROM
715 and RAM717, all of which are local buses
716 connected to each other. The bus is an appropriate circuit, not shown, that has an input bus 705 and an interconnect bus.
Interfaced to 719 and 750.
Register 711 can be loaded and read by an external command applied to lead 705, but it stores various parameters and is used by the system.
Takes overall control of 700. Also register 71
1 provides upstream image handling and / or state information used to interface to the processing system. The microcomputer 713 is one of various single-chip microcomputers that are generally commercially available. ROM 715 stores programs and constant data. RAM 717 is a multi-level halftone reference (font) data,
Stores 16 different 256-level halftone reference cell stacks and pre-defined noise data, as discussed below. The RAM is loaded with front data and noise data appearing on bus 705 during system initialization.

The decompressor 720 receives the packet of input image data and decompresses the compressed data which is temporarily stored in the system 700 and processed by known methods.

The image processing pipeline 730 performs specific image processing on the decompressed image data. The pipeline is composed of a trilinear interpolator 733, RAM memories 731 and 735, a tile pixel processor (TPP) 740 and a tiling RAM 742. The input 24-bit image data (24D) is applied to the trilinear interpolator 733 and TPP740. In particular, the interpolator 733 uses a table index and interpolation operation on a three-dimensional basis to perform various well-known color transforms and input red, green, blue (R, G, B) values. To cyan, yellow, and magenta (C, Y, M, B) values. The RAM 731 stores various index tables used by the interpolator 733.
The index table is rather complicated,
Created with a "reference" output writer. The tri-linear interpolator provides a 12-bit output data (12D) value that is sent to the look-up table stored in RAM735. The latter look-up table is relatively simple, 12-bit. Converts the output data into 8-bit form, such as dot gain effect
Compensates for C, Y, M, K values, especially the currently used output writers. If a different output writer (marking engine) is used, the table stored in RAM 735 changes appropriately to show the output characteristics of that writer. If the index table of RAM735 is changed, there is no need to change the rather complicated three-dimensional interpolation table stored in RAM731. If 8 bits (contones) are applied to the interpolator 733 rather than 24-bit color input data, the contone data is unchanged and is simply sent to the TPP 740 via the interpolator and RAM 735.

The 8-bit data provided by RAM735 is TPP
The contone value applied to the 740. The TPP is combined with a microcomputer 713, as discussed in detail below, to implement the inventive techniques to provide tile-based image rotation, scaling and halftone screening. TPP 740 is a microcomputer 713
Properly configured to process one contone data tile at a time, producing, for example, halftoned output bits. TPP by receiving tile start coordinates
Is configured, the TPP processes complete contone tiles independently of the microcomputer 713. The microcomputer tiles the entire contone image, and the coordinates of the start point of each tile, that is,
It calculates the ULC coordinate, the incremental sampling distance of the contone and halftone reference sampling, provides this information to the TPP, and then issues a command to the TPP to start processing the first contone tile. When the TPP completes the processing of the tile, the microcomputer updates the starting tile coordinates of the TPP of the next contone tile, and starts processing the tile from the TPP. Thus, the process for each successive contone image tile continues until the entire contone image has been processed. Tiling RAM 742, which is typically 128 Kbytes x 8 bits, is a "strip" of "N" complete lines of the contone image used by the TPP 740.
To store effectively. The RAM 742 is formed of high-speed RAM, but its relatively small size has the advantage that it is cheaper and less complex to implement than a full-size frame buffer of considerable speed. Based on the actual number "N" of the contone image lines stored in RAM742, the TPP 740 can perform image scaling within N to 1 / N in each of the fast and slow scan directions. ..

Output buffer / memory management unit 760
Address generator 762, memory controller
Includes 769 and output buffer 766. Output information is applied to unit 760 from pipeline 730, via buses 747 and 750. In the unit, the address portion of the information is sent to the address generator 762 via the bus 761, which converts the address into a block address and the block address to the memory controller via the lead wire 763. send.
The memory controller translates the block address into an appropriate memory address and sends the latter address to the address input of output buffer 766 via lead 767. The data portion of the output information is sent to the data input of buffer 766 via bus 761. These buffers contain multiple pages of RAM 768. The RAM consists of two groups of page buffers of the same size 768 _A and 768 _B.
These are RAMs that are manipulated as a whole in a well-known "ping-pong" fashion, where the output data can be written to another group, 768 _A , while reading data from another group, 768 _B. is there.
The output data read from buffer 768 is provided to a binary (“bilevel”) marking (writing) engine via output data lead 772.

Next, a two-chip implementation of the inventive technique used in the system 700 shown in FIGS. 12 and 13 (microcomputer 713 and TPP processor 74).
Reference is made to FIG. 14 which shows a block diagram of (0). The means is
Overall, tile transform / halftone (TTH) circuit 80
Called 0.

The TTH circuit 800 is a microcomputer 71
3, formed by TPP 740 and output buffer memory management unit 760. As discussed above, the microcomputer 713 calculates the starting point for each tile of the contone image and incremental sampling distance. The microcomputer also calculates the sine and cosine of the rotation angle φ and the screen angle θ. Because the calculation is easier to perform in software than it is in TPP. The TPP 740 is a dedicated hardware circuit, specifically a gate array, application specific integrated circuit (ASIC) that processes each tile by sampling through regions formed in the contone and halftone reference planes.
Alternatively, it is formed from another easily customizable large scale integrated circuit.

Together with the TPP, the microcomputer and its control program execute two nested loops in total. The outer loop, of the two loops, runs primarily in the microcomputer to process each contone tile of the image. on the other hand,
The inner loop runs independently in the TPP to process each pixel in each tile. As discussed in detail below, the microcomputer will place the TPP properly so that it can process each contone tile and then instruct the TPP to fully process the tile. Further, the microcomputer sets various parameter values necessary for the entire image, such as scaling parameters, rotation parameters, and halftone processing parameters, as will be discussed below. Once these parameters are set, they remain constant throughout the image.

As shown in FIG. 14, the input (contone) data is applied to the microcomputer 713 via the lead wire 803 together with the job control data (command information) from the lead wire 805. Various supervisory control signals are also applied to the microcomputer via leads 807 to coordinate and control image processing. The microcomputer provides status information, such as ready / busy, on lead 811 and an input flow control signal on lead 809. The status information is connected to an upstream circuit (not shown) to inform the current status of the TTH circuit 800. The flow control signal is used to adjust the amount of input contone data that the microcomputer receives at one time. The microcomputer 713 uses the lead wire 813 for the configuration information and the lead wire 815 for the tile information.
Various control signals are provided to the TPP 740 via a lead wire 817. The composition information and tile information are parameter values that the TPP needs to process each successive contone tile of the image. The constituent image is applied once to one image. On the other hand, the tile information is updated for each continuous contone tile. TPP 740
Provides the microcomputer with status information such as a ready / busy signal. By monitoring the status information provided on lead 819, the microcomputer calculates the parameter value of the continuous contone tile in addition to performing another task. On the other hand, TPP performs the pixel sampling operation of the current tile. Furthermore, as soon as the processing of the TPP is finished and the state is changed, the microcomputer loads the TPP with the parameter value of the next consecutive contone tile with a simple handshake protocol and then starts the tile processing to start the TPP. Minimize latency and increase system throughput. As discussed in detail below, the TPP will access the appropriate halftone front data and noise data from RAM717 for use during halftone screening. for that purpose,
The TPP applies the appropriate address information (address of the current xy sampling location) to RAM 717 via lead 841. Also, the obtained halftone data and noise data are received via the lead wire 843. Tiling RAM7
42 is address lead 831 and data lead 833
Connects to the TPP 740 via and stores the contone data for the "N" line strip of the contone tile currently being processed. The first strip of contone data is loaded into RAM 742 by microcomputer 713 prior to tiling. At this time, each successive strip is ready to be loaded after each preceding strip has been completely processed. The data stored in RAM742 is TP
Sampled by P.

When the TPP produces each output bit of the current block of the output image, the bit is stored in the FIFO (First In First Out) file 857. The FIFO file accumulates the data of the current output block created.
This FIFO is shown in dashed lines as it is typically implemented in a buffer read by an asynchronous controller.

When the TPP generates each block of the output data and notifies the event to the microcomputer 713 based on the handshake protocol and the change in the status information appearing on the lead wire 819, the microcomputer 713 The coordinates of the block of the output image are supplied to the address generator 762 via the lead wire 823. The address generator uses block transfer (“BL
Ting ”) processor, which translates the real block address into the image block coordinates of the output buffer 766 and applies the address to the memory controller 769. Then, the address generator applies the block address to the controller, and the microcomputer transfers the block of the current block of the output data to the FI.
Start from FO file 815 to output buffer 766. The contents of output buffer 766 appearing on lead 722 are applied to the marking engine and printed into a hard copy of the output image.

D. Microcomputer 713 and TP
Pseudocode description of operations performed on P 740 Microcomputer 713 shown in TTH circuit 800 of FIG.
The flow chart of the main loop 900 executed in FIG. 16 is shown in FIGS. FIG. 15 shows that it is configured by FIGS. 16 to 17. The loop processes the entire image and also configures and coordinates the TPP 740 operation to process each tile of the contone image.

More specifically, when input to the main loop 900, the block 905 is first processed. When executed, the block 905 performs the known power-up initialization sequence. Thereafter, execution proceeds to block 910. Once executed, block 910 is described below, in the contone image processing “setup” TPP circuit 800.
Calculate initial values for various parameter values used in.
Once this is done, execution proceeds to decision block 915. The block determines if the TPP circuit 800 has been commanded to begin contone image processing. If the TTH circuit 800 has not yet received the image processing instruction, execution proceeds to block 920 via NO path 917 exiting from the decision block. When executed, block 920 reads the job control data with the latest image processing command entered. The execution process then returns to decision block 915 to block the command. On the other hand, if the TTH circuit 800 has received the processing instruction of the input contone image, the execution processing is YES YES from the decision block 915.
Continue through to block 925. When block 925 is executed, it computes initial values for various parameters that are constant for the entire image currently being processed, as described below.

When block 925 is completely executed, execution proceeds to block 930. When executed, it computes initial values for various parameters that identify the contone tile of the image currently being processed, as shown below. Block 930 then loads the TPP 740 with the parameter value. Thereafter, block 935 issues a TPP 740 instruction to process the tile of the contone image. Execution then proceeds to block 940 while TPP 740 is processing the tile. The block is the address of the current block in the output image for the data of the contone tile that the TPP 740 is currently creating when executed (x, y).
Generate coordinates. The execution process then proceeds to decision block 945, as shown in FIGS. The decision block causes the microcomputer to wait with an execution closed circuit by NO path 946 until the TPP 740 completes the current contone tile processing. When the TPP 740 has completed the current tile processing, execution processing proceeds to YES block 947 exiting decision block 945 to block 950. When block 950 is executed, block 950 provides the address generator 762 (see FIG. 14) with the (x, y) block coordinate values and as soon as it receives a handshake from the address generator to acknowledge receipt of that address. TPP 74 to transfer the block output data held in the block from FIFO 857 to the output buffer 766.
Command 0. Once block 950 has been completely executed, execution proceeds to decision block 955, as shown in FIGS. The decision block determines whether the contone image has been completely processed, that is, there are still contone images that have to be processed. If the image has not been completely processed, decision block 955 returns execution processing to block 930 via NO path 958 to calculate the parameter values, etc. for the next consecutive contone tile of the image. On the other hand, if the contone image has been completely processed, decision block 955 returns execution to YES block 959 to decision block 915, waits for the next image processing instruction, and so on.

Before going into the detailed description of the pseudo code, the following terms, coordinates and variables are defined here for the sake of future understanding and for easy reference.

Term Definition Delta-means incremental amount.

Fast / Slow-usually means the fast scan direction across a page, tile, or halftone reference cell. The slow scan direction is orthogonal to the fast scan direction and is usually oriented below the page, tile or halftone reference cells.

K, l − Clipping coordinates u, v − Contone sampling address coordinates x, y − Halftone reference cell sampling coordinates p, q − Output image (page) address variable definition Δtile_u_slow, Δtile_v_slow-Contone Low and high image plane △ tile_u _fast, △ tile_v _fast speed Increment of movement between tiles in scan direction tile_u, tile_v-current contone tile position △ tile_x _slow, △ tile_y _slow-low speed through halftone reference cell and △ tile_x _Fast, △ tile_y _fast Increase in movement between tiles in fast scan direction (screening) tile_x, tile_y-Current halftone reference cell tile position △ tile_p_slow, △ tile_q _slow-Slow and high through output buffer △ tile_p_fast, △ tile_q _Fast Increment of movement between tiles in fast scan direction tile_p, tile_q-Output The current tile position of the buffer p_tile_start (= 0) -the tile offset of the output buffer q_tile_start (= 0) (normally zero in the case of tiling) △ p φ, △ q φ-the edge corresponding to the output block Offset of position between corners of tone tile △ pixel _x _slow, △ pixel _y _slow-slow through the halftone reference cell △ pixel _x _fast, △ pixel _y _fast and fast scan direction moving increment pixel sampling pixel _x , △ pixel_y-current pixel sampling position within the block of halftone reference cells △ pixel_u_slow, △ pixel_v_slow-low through the contone image △ pixel_u_fast, △ pixel_v_fast for fast and fast scan directions Incremental pixel sampling of movement pixel_u, pixel_v-current pixel sampling position of contone box of contone image △ pixel_k_slow, △ pixel_l_slow-low through the contone image △ pixel_k_fast, △ pixel_l_fast fast and incremental pixel movement of clipping variable in fast scan direction pixel_k, pixel_l-processed in contone image Current clipping position image for the pixel of the current contone box image_u (= 0) -Initial coordinate of the contone image (image image_v = 0) Can be other than 0 when clipping image Image_x , Image_y-halftone screen offset (which can be used for screen offset) block_size, tile_size-output block size and tile size (control and output) △ k_block, △ l_block-inter-block movement on various planes Increment △ u _block, △ v _block (between boxes on the contone surface) △ x _block, △ y _block △ p _Block, Δq _block block _k, block _l-for clipping variables, and con block _u, block _v tone images (specifically, control block _x, block _y inboxes), halftone reference cells, and block * p, block_q and the current block position in the output (page) buffer 2 _16- Constant used to shift the number into the upper 16 bits of the register (2 ¹⁶ ) Store these since the definition was made. Then, a detailed description of the pseudo code will be given.

FIG. 18 is a flow chart of the tile processing routine 1000 formed in steps 925-945 occurring in the main loop 900 of FIGS. Using inventive techniques, routine 1000 sequentially processes tiles that together form a contone image to produce a rotated, scaled and / or halftoned output image. The routine sets various image parameters and then sets various parameters for the "first" tile of the contone image to process the first tile. Then, each successive tile is processed until the entire contone image is processed by appropriately incrementing the parameter value specific to each successive contone tile.

Specifically, as soon as the routine 1000 is entered, execution proceeds to step 925, which sets "image" parameters, where various values, called image parameters, are constant for the entire contone image. Set the parameter value of. The parameter value is calculated based on, for example, the contone rotation angle φ, the anamorphic scale factors α and β, the screen angle θ, and the screen ruling. In particular, once entered in step 925, block 1010 is executed to set the block and tile sizes. The block size is set based on the angle at which the tile rotates, that is, the contone image rotation angle φ. In this case, the maximum tile size is 32. When the block size is set, the tile size is set next. Thereafter, execution processing proceeds to block 1020. This block 1020
With respect to the number of tiles in each row and the number of columns in the tile,
Determines the number of tiles processed in the contone image. Once determined, block 1030 is executed and
Compute incremental coordinate values (unique “Δ” values) for contone sampling and sampling through halftone reference cells, and for pixel movement of clipping variables. Thereafter, block 1040 is executed to increment the incremental coordinate values for movement between consecutive tiles in the contone image plane, in the halftone reference cell, and through the output buffer (a unique "△").
Value) is calculated. Once calculated, the step 925 of setting the "image" parameters is complete.

At this point, the execution process proceeds to step 930 which sets the "tile" parameter. Once entered in that step, the execution process first proceeds to block 1050.
When executed on that block, it is caused by the rotation of the contone tile associated with the corresponding block,
Offset value of the position of the output block △ p _phi, calculates the △ q _phi. Once the offset value has been calculated, execution proceeds to block 1060. The first portion of the block, located at step 930, is initialized so that the coordinates indicate the start point (ULC) of the first tile of the contone image. Each successive contone tile is then processed sequentially, beginning with the first tile, producing output bits that are written to successive pixel locations in the output buffer. In this way, each output block is filled with tiles of consecutive output pixels until the entire output image is formed. As each successive tile of the contone image is processed, the appropriate tile coordinates are incremented to prepare for the next contone tiling, and so on. Once all contone tiles have been processed, execution processing exits step 1060 and routine 1000.

FIG. 19 shows the tile processing routine 10 of FIG.
11 is a flowchart of step 1010 of setting a block and tile size executed at 00. This step determines the appropriate block and tile sizes, as already mentioned.

As soon as the input to step 1010 is completed,
Execution processing proceeds to decision block 1110. The block is executed to determine if a reduced scaling occurs in either direction of the contone image, ie if the scale factor α or β is less than one. If both factors are greater than one, execution proceeds to block 1140 via NO path 1115 exiting decision block 1110. When executed, block 1140 reduces the block size to 32 along each dimension, i.e. 32 x 32.
Setting to create a block having the output pixel position of. On the other hand, if reduced scaling occurs in either direction, then execution is out of decision block 1110.
YES Proceed to block 1130 via path 1120. Block 11
When executed, 30 determines the block size based on the scale factor and the contone rotation angle φ.
The subscript "f" used for the absolute value function in blocks 1130 and 1150 indicates that the absolute value function is calculated with the appropriate floating point precision. Once the block size is determined in either block 1130 or 1140, execution proceeds to block 1150, which calculates the tile size.
The tile size is based on the block size and the sine and cosine of the contone image rotation angle φ, and is at most one pixel smaller than the block size. Block 1150
After execution is performed, execution processing exits step 1010.

FIG. 20 shows the tile processing routine 10 of FIG.
11 is a flowchart of step 1020 of calculating the number of tiles executed at 00. As already discussed, step 1020
With respect to the number of tiles in each row and the number of columns in the tile,
Determines the number of tiles processed in the contone image.

Once entered in step 1020, execution proceeds to decision block 1210. When the block is executed, the height of the contone image H (in inches)
The number of rows of image tiles that form the contone image MAX_ROW as a function of, the anamorphic scale factor in the fast scan direction (α), the laser writing and the contone frequency (respectively to the writing spot per inch or the contone sample per inch). ) And the tile size. Once the calculation is complete, execution proceeds to block 1220, where the number of columns of image tiles forming the contone image MAX_COL as a function of the width W (in inches) of the contone image,
Calculate the anamorphic scale factor, laser writing and tile size in the slow scan direction (β). When execution of block 1220 is complete, execution processing exits step 1020.

FIG. 21 shows a step 10 for changing the set pixel coordinates executed in the tile processing routine 1000 shown in FIG.
30 is a flowchart of 30. As discussed above, step 1030 is an incremental coordinate value (a unique "△" value) for contone sampling and sampling through the halftone reference cell, and for pixel movement of the clipping variable.
To calculate. The value is constant throughout the contone image currently being processed.

As shown in the figure, as soon as an input is made to step 1030, the execution process proceeds to 1310. The block, when executed, is based on the sine and cosine of the contone image rotation angle φ, and the size of the tile and block, the clipping variable, the parameter value of the incremental pixel movement of k and l, ie Δpixel _k _fast, △ pixe
l _l _fast, ∆pixel _k _slow, and ∆pixel _
Calculate l_slow. When all the increment values have been calculated, execution proceeds to block 1320, which is executed to calculate the parameter values for the contone surface pixel sampling increments. Parameter value, △ pixel _u _fast, △ pixel
_V _fast, △ pixel _u _slow, and △ pixel _v
_Slow is determined based on the anamorphic scale factor, the contone and laser frequency, the sine and cosine of the contone image rotation angle φ, and the block size. When all the parameter values have been determined, execution proceeds to block 1330. The block is
When executed, the parameter value of the pixel sampling increment of the halftone reference plane, ie, Δpixel _x _fast, Δpixel
_Y _fast, △ pixel _x _slow, and △ pixel _y
Calculate _slow. The increments are screen ruling, laser frequency, sine and cosine of screen angle θ,
And calculated based on the block size. When the calculation of the parameter value is completed, the execution process exits from step 1030.

FIG. 22 shows a step 10 of changing the set pixel coordinates executed by the tile processing routine 1000 shown in FIG.
It is a flow chart of 40. As discussed above, step 1040 computes incremental coordinate values (unique “Δ” values) for movement between consecutive tiles within the halftone reference cell, within the output buffer, and within the contone image plane. The value is constant throughout the contone image currently being processed.

As shown, once entered in step 1040, execution proceeds to block 1410. When executed, based on the sine and cosine of the contone image rotation angle φ and the tile size, the parameter value of the movement between consecutive tiles of the output buffer, ie, Δtile_p_fast, Δtile_
Calculate q_fast, Δtile_p_slow, Δtile_q_slow. When all of the parameter values have been calculated, execution proceeds to block 1420, which, when executed, calculates the parameter values for the continuous inter-tile movement of the contone surface. Initial values of the parameter values Δtile_u_fast and Δtile_v_slow are set to 0. Remaining parameter value, △ tile
_V_fast and Δtile_u_slow are determined based on the anamorphic scale factor, contone and laser frequency, and tile size. When all the parameter values have been determined, the execution process is block 1430.
When executed, the parameter value of movement between consecutive tiles of the halftone reference plane, that is, Δtile_x_fast, Δti
le_y_fast, △ tile_x_slow, and △ tile_y_s
Calculate low. The increment is based on the sine and cosine of the screen angle θ, the tile size and the halftone reference plane pixel sampling increment. Once the parameter values have been calculated, execution processing exits step 1040.

As noted above, there is an offset between consecutive output block edges and the corresponding contone tile due to truncation associated with tile rotation and integer block addressing. To ensure that the sampling of the contone image corresponds to the correct integer position in the output buffer, the offset between the tile's "real" contone sampling position and the corresponding integer pixel address in the output block must be in the contone tile. You have to make a decision. The offset value is determined only once, and thereafter, it is used to compensate the sampling initial position of each contone tile. To this end, the upper left corner (ULC) of each block is easily determined with floating point precision. But,
The integer sampling address may change by about 1 bit due to rounding down. Therefore, one bit is shifted up and to the left at the position of each tile.
If the offset is determined and the initial sampling position of each contone tile is corrected by the offset value, no sampling error occurs and each contone tile is sampled and all contone tiles are correctly positioned.

FIG. 23 diagrammatically shows the offset position between the edge of the output block 217 ₇ and the corner of the corresponding contone tile 215 ₇ caused by the rotation of the tiles within the block. Block 217 ₇ sides 1515,1530,1540
And a square with 1550. Tile 215 ₇ is sized to fit in the maximum in the block. Also,
Given a contone rotation angle φ, the ULC 1545 with sampling coordinates (0,0) is oriented to align with the left side 1550 of the block. The location of the other three corners of the tile, 1520, 1525 and 1535, is the ULC of the tile, ie
Coordinates (-temps, t with reference to the coordinates (0,0) of the (p, q) axis
empc), (tempc-temps, tempc + temps) and (te
mpc, temps). 25 and 26
As shown in, the position sampling offsets, Δp _φ and Δq _φ are min (0, temps, tempc-temps,
-temps) and min (0, tempc, tempc + temps, temps)
It is defined by The distances tempc and temps are
It is defined with respect to the sine and cosine of the tile size and the contone rotation angle φ, respectively.

Now that the description of offset has been completed, attention is directed to FIGS. 25 and 26. 25 and 26 show the whole flow chart of the block position offset calculation step 1050 for calculating the offset values Δp _φ and Δq _φ . Further, this step 1050 is executed by the tile processing routine 1000 shown in FIG. FIG. 24 shows FIG.
4 is configured by FIGS. 25 and 26. Step 1050 is formed by step 1610 of calculating Δp φ and step 1650 of calculating Δq _φ . In step 1610, the value of Δp _φ takes the maximum value of −,
That is, (0, temps, tempc-temps, -temps) is calculated so that it becomes the maximum of-. On the other hand, in step 1650,
The value of _φ takes the maximum value of −, that is, (0, temp
c, tempc + temps, temps) is calculated to be the maximum of −.

Step 10 as described in detail below.
As soon as the input to 50 is done, the execution process is △ p
Proceed to step 1610 to calculate _φ . Here, first, block 1615 is executed. The block sets the initial value of the Δp _φ value to 0. Thereafter, execution processing proceeds to decision block 1618. For the block, the value tempc is negative,
That is, it is tested whether the initial value of Δp _φ is smaller than 0. If the value tempc is negative, execution proceeds to block 1625 via YES path 1619. The block is executed, the current value of Δp _φ is set to the same value as tempc, and the execution process proceeds to decision block 1628. On the other hand, the value t
If empc is not negative, decision block 1618 returns NO.
Execution processing is sent to decision block 1628 via path 1620.
In the latter decision block, the tempc-temps value is the current Δp _φ.
Determine if less than the value. If the value of tempc-temps is less than the current Δp _φ value, then decision block 1628.
Sends execution processing to block 1635 via YES path 1629 where the current Δp _φ value is set to the same value as tempc-temps. Execution processing then proceeds to decision block 1638. Execution processing also proceeds to block 1638 if decision block 1628 also determines that the value of tempc-temps is greater than or equal to the current Δp _φ value. Decision block 1638 is -t
Determine if the value of emps is less than the current Δp _φ value. If the value of -temps is less than the current value of Δp _φ , decision block 1638 advances execution via YES path 1639 to block 1645 to make the current value of Δp _φ equal to the value of -temps. Set. Execution processing then exits from step 1610. On the other hand, if the value of -temps is greater than or equal to the value of Δp _φ , then execution proceeds from step 1610 via NO path 1640 exiting decision block 1638.

Once step 1610 has been fully executed to determine the current value of Δp _{φ for} the tile currently being processed, step 1650 performs a calculation of the value of Δq _φ for that tile. As will be described in detail below, as soon as an input is made to step 1650, execution proceeds to block 1655,
When executed, it sets the initial value of _Δqφ to 0. afterwards,
Execution processing proceeds to decision block 1658. The block is
Test whether the value tempc is negative, that is, less than the initial value 0 of Δq _φ . If the value tempc is negative, execution proceeds to block 1665 via YES path 1659. The block is executed and the current value of Δq _φ is t
Set the same value as empc and judge execution processing Block 1668
Proceed to. On the other hand, if the value tempc is not negative, decision block 1658 sends the execution process to decision block 1668 via NO path 1660. The latter decision block is tempc +
Determine whether the value of temps is less than the current Δq _φ value. If the value of tempc + temps is less than the current Δq _φ value, decision block 1668 directs execution processing, via YES path 1669, to block 1675, where the current Δq _φ value is determined.
Set to the same value as tempc + temps. Execution processing then proceeds to decision block 1678. Execution processing also proceeds to block 1678 if decision block 1668 determines that the value of tempc + temps is greater than or equal to the current Δq _φ value.
Decision block 1678 determines if the value of temps is less than the current Δq _φ value. If the value of temps is less than the current Δq _φ value, decision block 1678 returns YES pass 1679.
Execution proceeds to block 1685 where the current value of Δq _φ is set to the same value as temps. Execution processing then exits from step 1650. On the other hand, the value of temps is △
If it is greater than or equal to the value of _qφ , execution proceeds from step 1650 via NO path 1680 exiting decision block 1678.

The high level flowchart of step 1060 for processing tiles performed by the tile processing routine 1000 of FIG. 18 is shown in FIG. As discussed, step 10
The 60 processes the first tile through a loop after initializing the coordinates to indicate the starting point (ULC) of the first tile of the contone image. Then, each successive contone tile is processed sequentially to completely fill each corresponding output block of the output image with output bits. In addition, after processing each successive tile of the contone image, the step
The 1060 increments the appropriate tile coordinates to prepare for the next continuous contone tiling.

Specifically, as shown in FIG. 27, step 10
As soon as the input to 60 is made, the execution process first proceeds to block 1710. The block is executed to initialize various respective tile-based parameter values for the first tile of the image. The execution process then sequentially processes all tiles of the contone image through two nested loops, outer loop 1720 and inner loop 1730. In particular, the outer loop 1720 processes the entire row of tiles at once. Inner loop 1730, on the other hand, processes each tile in each row. Loop 17
As soon as the inputs to 20 and 1730 are made, execution proceeds first to block 1740 in the inner loop. The block is executed and the current position of the output block in the output (page) buffer (block_p, block_q)
To calculate. The execution process then proceeds to block 1750,
Each increment value specific to the current contone tile being executed and being processed, ie Δp_block, Δq_block, Δk_block,
Calculate Δl_block, Δu_block, Δv_block, Δx_block and Δy_block. Once all the calculations have been made, execution proceeds to block 1760, where the increments are used to execute each parameter value that is also specific to the current tile being processed: block_k, block_l, b.
Initialize lock_u, block_, block_x and block_y. Thereafter, execution processing proceeds to block 1770. The block fully processes the current contone tile, as described below. The current contone tile is step 1770
Processing proceeds to step 1780, where it increments various fast scan base parameters of the next consecutive contone tile of the current row being processed. Once the increment has been made, step 1770 processes this contone tile and the process continues until all rows of the contone tile have been processed. When the tile processing is completed, the execution processing is performed from the inner loop to the outer loop 17
Continue to block 1790 within 20. The block increments various slow scan parameters to indicate the first contone tile of the next successive row of contone images. When the increment is done, the execution process returns to the inner loop 1730 to process all tiles in the row, and so on. When all tiles of the contone tile have been processed, execution processing exits from outer loop 1720 and step 1060 processing tiles.

Step 10 of processing the tile shown in FIG.
A detailed flowchart of 60 is shown throughout FIGS. 29 and 30. FIG. 28 shows that FIG. 28 is composed of FIGS. 29 and 30. The steps forming block 1710-1790 of FIG. 27 are illustrated in FIGS.

As shown, when an input is made to step 1060, execution proceeds to block 1710. Here, the parameter values image_u, image_v, image_x, i
mage_y, p_tile_start and q_tile_start
Parameter values for the first contone tile in the image, tile_u, tile_v, tile_x, tile_y, til
Set the same as e_p and tile_q. Here, the outer loop 1720 and the inner loop 1730 are input. Next, block 1740 is executed, in which the output coordinates of the current block, block_p and block_q, are tiled.
Offset value corresponding to the current value of _p and tile_q △ p _φ and △ q set _phi to a value obtained by adding a. As a result 16
Bit-shifted to the right to make an integer block address.
Thereafter, block 1750 depicts an increment value, Δp_, specific to the first contone tile being processed with the contone image.
block, q_block, △ k _block, △ l _block, △ u _bloc
Calculate k, Δv_block, Δx_block and Δy_block. In this way, Δp_block and Δq_block
Is formed by the fractional part of the block address. Of the remaining tile-based increments, △ k _block, △ l _block,
Δu _block and Δv _block are sine and cosine of the contone image rotation angle φ, Δp _block and Δq _
Calculated based on block value, tile size, and contone and laser frequency. The remaining two tile-based increments, Δx _block and Δy _block
Is calculated based on the sine and cosine of the screen angle θ, Δp_block and Δq_block, screen ruling and laser frequency. The increment value is a block
Once determined at 1750, block 1760 determines the tile base parameters block_k, block_l, block_u, block_v,
The initial values of block_x and block_y are calculated based on the increment value. The parameter value is also specific to the current contone tile being processed. Then block 1770
Performs the processing of the entire current contone tile as defined by the parameter values determined through the previous block. If the contone tile is fully processed and there are other contone tiles that must be processed in the current row, the tile-based parameter tile
_U, tile _v, tile _x, tile _y, tile _p and
tile_q is block 1780, where each tile-based increment is appropriate for the fast scan direction, ie, Δtile_u_fast,
△ tile_v_fast, △ tile_x_fast, △ tile_y_fa
Incremented by st, Δtile_p_fast and Δtile_q_fast to define the next contone tile of the current row.
The column counter, col, is also incremented by 1. At this point, there is at least one contone tile to process in the current row, execution processing returns to block 1740 to process that tile, and so on. However, once all tiles in the current row have been processed, execution exits inner loop 1730 and proceeds to block 1790. The tile base parameter, tile_u, tile_v, tile, if there is at least one other line that must be processed by the contone tile.
_X, tile_y, tile_p and tile_q are block 17
At 90, each tile-based increment amount appropriate for the slow scan direction, ie, △ tile_u_slow, △ tile_v_slow, △
tile_x_slow, △ tile_y_slow, △ tile_p_slow
And Δtile_q_slow are incremented to define the first contone tile of the next consecutive row. The row column counter, row, is also incremented by 1. At this point, there is at least one row of contone tiles to process, execution processing returns to block 1740 to continue processing each contone tile in that row, and so on. When all the rows of the contone image have been processed, the execution process is the outer loop.
Exiting from 1720 to block 1820, which produces the proper signal that the contone image has been fully processed. The execution process then exits from step 1060.

A high level flowchart of the process tile routine 1770, which is performed as part of the step 1060 of processing tiles shown in FIGS. 29 and 30, is shown in FIG.
Shown in 1. As we have already considered, the routine is
Process the entire tile as desired by scaling and / or halftoning.

As shown in detail in the figure, as soon as an input is made to the routine 1770, the execution process begins with the block
Continue to 1910. The block, when executed, initializes various pixel-based parameter values for the first pixel of the current output block being generated. When initialization is complete, execution proceeds to decision block 1920. Here, it is decided whether to process a tile (ie tile mode) or a single raster of pixels based on the last user input. If the contone image is not rotated, then a single raster of pixels is typically processed. If the tile is processed, decision block 1920 causes the execution process to be YES.
Sends via path to block 1930, which when executed initializes the tile's p counter. On the other hand, if a single raster of pixels is used, decision block 1920 directs the run process to the 1940 via the NO path, which, when executed, initializes the raster's p counter. When either block 1930 or 1940 is executed, execution processing enters two nested loops, an outer loop 1950 and an inner loop 1960. The outer loop processes all pixels in a row at once. On the other hand, the inner loop processes each pixel in each row. More specifically, as soon as inputs to loops 1950 and 1960 are made, execution proceeds first to block 1970 within the inner loop. When the block is executed, it obtains the data of the pixel currently addressed in the output block through clipped sampling on the contone reference plane and the halftone reference plane, and outputs the result at the pixel position to the output block. Store. Then the execution process is blocked
Proceeding to 1980, when executed, each parameter value (that is, q, pixel_k, pixel_l, pixel
_U, pixel_v, pixel_x and pixel_y) are incremented to make them available when generating the output value of the current next consecutive pixel of the output block. Once the entire row of pixels in the output block has been written to the output block, execution proceeds from the inner loop to block 1990 located in the outer loop 1950. The block is in the slow scan direction,
Various parameters, specifically p, pixel_k, pixel_l,
Increment by pixel_u, pixel_v, pixel_x and pixel_y to make it available when generating the output value of the first pixel of the next consecutive row of the current output block. Once processed, the execution process returns to the inner loop 1960 to process all pixels in this row, and so on. When all rows of pixels in the current output block have been written, execution processing exits the outer loop 1950 and pixel processing routines 1770.

The process tile routine 1770 shown in FIG. 31.
A detailed flowchart of is shown in FIG. The individual steps forming block diagrams 1910-1990 of FIG.
Shown in.

As shown, the execution process proceeds to block 1910 as soon as an input is made to step 1770.
Here, the parameter value of the first pixel of the current output block being generated, that is, pixel_k, piexel_l, pixel_u,
Determine pixel_v, pixel_x and pixel_y. After that, the counter p goes through steps 1920-1940
Initialized to 0 or block_size-1, respectively, depending on whether tile mode is used. Once initialized, execution enters outer loop 1950 and inner loop 1960. In the inner loop, execution is performed for all the pixels in each row of the output block, but the execution processing first proceeds to block 1970,
Generate the output value of the current pixel of the row through the process pixel routine (as discussed in detail below) and store the output value in the pixel of the output block. afterwards,
Block 1980 contains parameter values, namely pixel_k, p
ixel_l, pixel_u, pixel_v, pixel_x and pixel
_Y is incremented in the direction of high-speed scan △ pixel _k * fas
t, △ pixel _l _fast, △ pixel _u _fast, △ piexe
l_v _fast, △ pixel _x _fast and △ pixel _y
Increment with _fast so that it can be used later when generating the output value of the next consecutive pixel in the current row of the output block. The current contents of the q counter is also incremented by one so that it points to the next consecutive pixel in the current row of the output block. At this point, there is at least one pixel value generated in the current row of the output block (or raster), the execution process returns to block 1970 to determine the output value for that pixel, and so on. However, when the output values of all pixels in the current row (or raster) are written, the execution process
Exit inner loop 1960 and block outer loop
Proceed to 1990. If there is at least one output value left in the row of pixels that must be written to the output block, the pixel parameter value, specifically pixel_k, pixel_l, pixel
_U, pixel_v, pixel_x and pixel_y are corresponding increments in the slow scan direction, ie, Δpixel_k_slow, Δpixel_l_slo through step 1990.
w, △ pixel _u_slow, △ pixel _v _slow, △ pixel
It is incremented using _x _low and Δpixel _y _low so that it can be used later when generating the output value of the first pixel of the next consecutive row of the output block. The current contents of the p counter are also incremented by one to indicate the next consecutive row of output pixels for the current block. On the other hand, if the output value has been written for all the rows of the output block, the execution process is the outer loop 1950 and the routine 1770.
Get out of.

A high level flowchart of the process pixel routine 1970, which is executed as part of the process tile step 1970 of FIG. 32, is shown in FIG. The routine determines the current addressed pixel data of the output block through sampling clipped on the contone reference plane and the halftone reference plane, as described above, and stores the result at the pixel location of the output block.

Specifically, as shown, as soon as an input is made to the routine 1970, the execution process first proceeds to block 2110. The block is executed to set two masks. Two masks, one for accessing the noise data array and one for accessing the appropriate halftone reference data array, both from RAM717 (see FIGS. 11 and 14). .. Each mask is the pixel_x and pixe used to address each array
Used to separate the appropriate bits within the l_y address. When the mask is set, the execution process is performed as shown in FIG.
3, proceed to block 2115 and when executed, the current pixel address pixel_k, pixel_l, pixel_u and p
Extract the integer part of ixel_v. Then block 2120
Determines the current value of a clipping variable, VALID, to determine if the current pixel being generated for inclusion in the current output block is in the corresponding output tile. As described above, the value of the variable VALID is formed by ANDing only the least significant integer bits of the k and l clipping addresses of the pixel. This bit is a predefined mask, ie "0x0
It is separated by taking the "AND" of the addresses of pixel_y and pixel_y with 001 ". The" 0x "of" 0x0001 "defines the hexadecimal system. Block 2120 is completely executed. If so, execution proceeds to decision block 2125. The decision block is executed to determine if the current sampled pixel of the contone image overlaps the edge of the image at the current integer pixel address. If there is such an overlap, decision block 2125 sends execution processing to execution block 2130 via YES path 2127.
Block 2130 is executed to set the sampled contone value for the pixel to a predefined number associated with color white. On the other hand, if the currently sampled pixel of the contone image is in the image, ie, does not overlap the image edge, decision block 2125 sends execution processing to block 2135 via NO path 2129. A block 2135 stores the sampled contone value of the pixel in question in the tiling RAM 7
I ask from 42. (See FIGS. 11 and 14).

Thereafter, execution processing proceeds to decision block 2140, as shown in FIG. The decision block determines, based on the last user input, whether halftone screening occurs, that is, whether "contone mode" is not currently used. If screening does not occur, the contone, rather than the halftone value, is provided to the output buffer, resulting in a continuous output image rather than the halftone processed output image. The decision block 2140 then sends the execution process to the block 2145 via the YES path 2142. Block 2145 provides the executed and sampled contone value as the output data for the current pixel in the output buffer. The execution process then exits routine 1970. On the other hand, if halftone screening occurs, decision block 2140 sends the execution process to decision block 2150 via NO path 2144. Decision block 2150 directs execution to block 2155 or 2160 based on the current value of the clipping variable VALID if the current addressed bit of the output block is set to 0 or some output value screened, respectively. Send to either. If the current output bit is outside the output tile associated with the output block, then that bit is set to zero. In this case, decision block 2150 causes the execution process to
Send to block 2155 via NO path 2152. Block 2155
Sets the output bit to zero. Then block 21
70 performs the process of writing a zero value to the current bit position of the output block, specifically FIFO 857 (see FIG. 14). When block 2170 is executed, execution processing exits routine 1970, as shown in FIG.

On the other hand, if the current output bit is in the corresponding output tile of the output block, then that bit will have the screened output value. FIG. 33
The decision block 2150, as shown in FIG.
Proceed to block 2160 via 2154. Block 2160 is
When executed, the halftone reference stack is properly sampled and that particular cell is selected by the current contone value associated with that output bit. Furthermore, blocks
The 2160 selects a particular halftone stack (font) and / or uses the addressed noise value to change the halftone sampling address. (Detailed discussion below). Especially, the noise data array of RAM717 is
Addressed using the relevant bits in the pixel_x and pixel_y addresses. The array comprises a seamless pseudo-random array of pre-stored 4-bit noise data used to select one of 16 different halftone reference stacks (fonts). The stack stores different predefined halftone dot patterns. The particular pattern is not important.
However, if a random font is selected, spatially repeating artifacts such as moire patterns that may appear in the output image due to the beating of the spatial sampling frequency on the stored halftone dot pattern, It is disassembled well and does not appear. When a font is selected, the current contone value associated with the current output pixel selects the corresponding halftone reference plane. The selected reference plane is the current subordinate pixel_x and pixel_
Create output bits that are sampled and screened based on the y address. Then block 2160
After completing the creation of the screened output bits of the currently addressed pixel of the output block, execution proceeds to block 2170, where the value is written to the bit position of the output block, specifically FIFO857 (see Figure 14). ). When block 2170 is executed, the execution process exits routine 1970, as shown in FIG.

FIG. 34 shows the process pixel routine of FIG.
19 shows a detailed flowchart of 1970. Block of Figure 33
The steps for forming 2110-2170 are shown in FIG.

Specifically, as shown in the figure, block 2110
Sets two masks. The noise_bit_mask is for accessing the noise data array and the font_bit_mask is for accessing the appropriate halftone reference data array, both from RAM717 (see FIGS. 11 and 14).
The mask is the pixe used to address each array.
Define the appropriate bits in the l_x and pixel_y addresses. In block 2115, pixel_k, pixel_l, p
The current values of ixel_u and pixel_v are shifted right by the appropriate number of bit positions, respectively, to the corresponding integer addresses, namely int_, int_l, int_u and int.
Find _v. Thereafter, block 2120 combines the integer pixel addresses int_k and int_l with the mask "0x0001" to determine the value of the 1-bit clipping variable VALID. The "0x" in the mask "0x0001" defines the hexadecimal system.
Blocks 2125-2135 then determine whether the contone value of the current output bit of the output buffer is a color white value, depending on whether the sampled current pixel of the contone image overlaps the edge of the contone image. Set to the sampled contone value. If contone mode is not used, blocks 2140-2145 return the contone value sampled by the run process before exiting routine 1970. On the other hand, if halftones are performed because contone mode is not being used, blocks 2150-2170 determine the current output bit based on the state of the clipping variable VALID and the variable VALID is false (that is, 0). ) For zero, and if the variable VALID is true (ie, 1), set it to the screened output bit. The process halftone routine, as described above, is the current value of the parameter contone, pixel_x, pixel_y, noise_bit_mask and f.
The ont_bit mask is used to determine the halftone data bit value of the current output bit. Variables pixel_x and pixel
Noise_bit_determined using the upper bits of _y
The value of mask is pseudo-randomly selected using a special halftone reference stack (font) and a variable contone value that selects the special halftone plane of that stack and the lower bits of pixel_x and pixel_y. Sampling, as specified by the value of _mask, determines the particular sampling location of the surface. The single bit value stored at the sampling location of the surface is the screened output data. The bit, whether 0 or the screened output data, is block 2170.
Is written to the next output location in the FIFO 857 (see FIG. 14). After that, as shown in FIG. 34, the execution process is
Exit routine 1970.

E. Tile / Pixel Processor (TPP) 740
Dedicated hardware embodiment of Tile / Pixel Processor (TP
A high-level block diagram of the P) 740 embodiment is shown in FIGS. 35 is the same as FIG. 36 and FIG.
It is composed of.

As shown, the TPP 740 includes a tile register 2310, a tile processor 2320, and a pixel processor 2350.
And formed with control logic 2380. The tile and pixel processor executes a nested loop in batches to process each contone tile and each pixel in the image by each output block of each tile. In effect, the tile processor 2320 executes the process tile routine 1770 as shown in FIGS. 31 and 32. On the other hand, the pixel processor 2350, as shown in FIGS. 33 and 34,
The process pixel routine 1970 is executed. The TPP is preferably implemented using a gate array, ASIC or other readily personalizable large scale integrated circuit device. Control logic 2380 is formed of simple combinatorial logic and / or finite state machines. The particular implementation of the logic can be readily apparent to one skilled in the art and controls the overall operation of the TPP 740. In response to the pulses provided by the "Start Processing" lead 817 and by the microcomputer 713 (see FIG. 14), the control logic 2380 of FIGS.
Next) ”Pulse lead 2384 to issue an instruction to tile processor 2320 to load the register with the value appearing on lead 815 in time with the current clock pulse. Then, on the next clock pulse, it issues a command to start processing the current tile in the contone image.
At the same time, the control logic 2380 asserts a low level on the "Tile Done" lead 2382 located in the status information lead 819 to inform the microcomputer that tiling is being actively performed. . When this process is completed, the tile processor 2320
Pulses the "tiled" lead 2386,
Notify control logic 2380. The control logic 2380 then issues a high level to the "tiled" lead 2382 to cause the microcomputer 713
Notify (see FIG. 14) that the contone tile has been completely processed.

In response to the “start processing” pulse on lead 817 during TPP 740 initialization, tile register 2310 shown in FIGS. 36 and 37 is paralleled by microcomputer 713 to lead 815 (see FIG. 14). Via, the tile information, that is, the current tile to be processed and the parameter values that specify the appropriate increment pixel values are loaded. The parameter value is the block address (block_k, block
_L, block _u block _v, block _x and block _y)
And pixel increments in both fast and slow scan directions (Δ p
ixel_k _fast, △ pixel _l _fast, △ pixel _u _
fast, △ pixel _v _fast, △ pixel _x _fast, △ pix
el _y _fast and △ pixel _k _slow, △ pixel
_L _slow, △ pixel _u _slow, △ pixel _v _slo
w, △ pixel _x _slow and △ pixel _y _slow)
including. As shown in FIGS. 36 and 37, the block address and the tile increment are set in the control logic 23.
The 10 leads via leads 2312, 2314 and 2316 to the appropriate adder or multiplexer 2430 in the tile processor 2320.

The tile processor 2320 has an adder 2322, an adder 2325 and multiplexers 2328 and 2330. The adder and multiplexer are folded back six times, one for each different pixel parameter value, and connected as shown. The tile processor has six separate registers, namely six pixel parameters (pixel_k, pixel_l, pixel_u, pixel_v, p).
ixel_x and pixel_y) and control logic 2340 also has a pixel register 2333 with one register each. The pixel register holds six pixel parameter values to generate an output value for each pixel processor 2350 of the current block in the output buffer.
The control logic 2340 is based on the overall operation of the tile processor 2320, in particular the flowchart 2600 of FIG. To control.

Next, in order to simplify the examination of the tile processor 2320, one of the same six sets of adders, multiplexers and pixel registers, namely pixel_ in the example shown.
A detailed study will be conducted only on the k parameter value. At this point, under control of the control logic 2340, and during initialization of the tile processor, the input I 1 of multiplexer 2330 is blocked on lead 2316.
Receive the start address of _k from tile register 2310. For the first pixel in the first row of the output block,
The control logic 2340 issues the conformance level as a select signal from the lead 2344 to the multiplexer 2330 to advance the starting address to the input of the pixel_k register in the register 2333. Control logic 2340 then issues an appropriate load signal on lead 2345,
The specific register is loaded into the start address as the pixel_k parameter value and the lead line 2335 is advanced. Since the lead wires 2335 and 2326 are connected, this value is also fed back to the inputs of the adders 2322 and 2325. The increments of Δpixel_k_fast and Δpixel_k_slow are applied to the other inputs of adders 2322 and 2325, respectively. The outputs produced by adders 2322 and 2325 are sent to corresponding inputs of multiplexer 2328 via leads 2324 and 2327. Since the contents of the pixel_k register are fed back via lead 2326 to the corresponding inputs of adders 2322 and 2325, the adder
The increments of pixel_k_fast and Δpixel_k_slow are repeatedly added to the previous pixel_k parameter value to point to the contiguous pixel in each row and the first pixel in the contiguous row. p
To increment the ixel_k parameter value to point to the next consecutive pixel in the current row in the output buffer, control logic 2340 issues the appropriate level on leads 2342 and 2344 as the select (S) signal to add. The output of the device 2325 is advanced to the pixel_k register in the pixel register 2333 via multiplexers 2328 and 2330. The control logic then sets the appropriate level to lead 2345.
And loads the accumulated value generated by the adder 2325 into the pixel_k register in the pixel register 2333. In particular,
The adder 2325 is controlled by the logic 2340.
High speed scan pixel_k Incremental △ pixel _k _fast
Is added to the previous pixel_k parameter value with the result value and then loaded into the pixel_k register to point to the next consecutive output pixel position in the current row. When the end of the row is reached, adder 2325 overflows to point to the first pixel location in the row and produces a pulse on the execute (CO) output provided to control logic 2340 via lead 2347. The resulting pixel address is stored in register 2333 via multiplexers 2328 and 2330.
It is sent to the pixel_k register and loaded. In addition, control logic 2340 sets appropriate levels to lead 2342 and lead 2342 to modify the resulting pixel_k parameter value to point to the first pixel in the next consecutive row.
Multiplexer 2328 and select signal via 2344
Issue 2330 and add .DELTA.pixel--k--slow increments via adder 2322 to the current pixel address to produce an address that points to the first pixel of the next consecutive row. The resulting address is registered in the register via multiplexer 2330.
Applied to the input of the pixel_k register in 2333. The control logic 2340 then applies the appropriate level via lead 2345 to load the pixel_k register with the address value and generate the pixel_k parameter values for the consecutive pixels in the row and all subsequent rows. To do. When the last row of output pixel addresses is generated, adder 2322 overflows and generates a pulse on the execute (CO) output applied to control logic 2340 via lead 2323. As a result, the control logic
2340 generates a level change signal on lead 2386 to inform logic 2380 that the current block has been fully processed. Another five pixel parameter values are similarly incremented for each successive pixel in the current output block using the corresponding initial block value and fast, slow scan increments.

To generate the appropriate output data for each pixel in the contone image, six pixel parameters (pi
xel _k, pixel _l, pixel _u, pixel _v, pixel _x and pixel _y) are the current values of leads 2336, 2337 and
Sent to the pixel processor 2350 via 2338.

The processor is based on the contone logic 23.
54, noise address logic 2358, halftone reference (font) address logic 2365 and clipping logic
Has 2370.

During operation, the current value of the pixel parameter pixel_
u and pixel_v specify the current sampling position of the contone reference plane. The Contone Logic 2354
It is determined whether the sampling position overlaps the edge of the contone image. If there is an overlap, the logic provides a predefined contone value to color white via lead 2366. On the other hand, if the current sampling position is within the contone image, the contone logic 2354 will set the corresponding memory address to pixel_u and pixel_u.
It is generated in the tiling RAM 742 based on the _v parameter value. The address is applied to the tiling RAM via lead 2355. Then this tiling RAM
Reads the contone value stored in the addressed memory location and provides the resulting value via data lead 2357. Then, the Contone Logic 2354
Apply that value to lead 2366. Contone logic
At the same time as the operation of 2354, the noise address logic 2358
Based on the 8-bit high-order address contained in the pixel_x and pixel_y addresses appearing on the lead wire 2338, the addresses are combined to the noise data RAM 717.
Form a 16-bit memory address. The two 8-bit upper addresses are adjacent to each other to form a 16-bit address field.

Then, this address field is applied to the noise data RAM via the lead wire 2361. The noise data array stored in the noise data RAM is
Typically, it is a 256 x 256 seamless array of predefined 4-bit pseudo-random values. Each of the pseudo-random values selects a corresponding one of 16 halftone reference (font) stacks. The stack, each having 256 separate 64x64 halftone reference planes,
Halftone reference data Stored in RAM717. Noise data
The resulting noise data read from RAM717, specifically the FONT ID value, is applied to the halftone reference address logic 2365 via lead 2362. Logic 2365 is lower
The FONT ID is used as the upper bit having the pixel_x and pixel_y address bits in succession to form the memory address in the halftone reference data RAM 717. The address is provided via lead 2367 to halftone reference data RAM 717 having an addressed single bit value read from memory applied to clipping logic 2370 from lead 2369. Clipping logic 2370 determines the output pixel of the current output block-this halftoned data is a lead based on the current values of pixel_k and pixel_l appearing on lead 2336.
Determine if the-, which appears through 2369, is in the output tile. If the pixel is in the corresponding output tile, clipping logic 2370 advances the single bit value appearing on lead 2369 to output lead 853 as output data and stores it in FIFO 857. On the other hand, if the pixel is outside the corresponding output tile, the clipping logic uses the zero value as output data for the lead 853
To provide. When the appropriate data value is applied to lead 853, the control logic 2380 applies a level change from lead 2385 to the "valid output data" lead 819 so that the data appearing on output lead 853 is valid. Signal. The level change controls the timing at which the output data is written to the FIFO by a known method.

FIG. 38 shows the TPP 740 of FIGS. 36 and 37.
FIG. 3 is a block diagram of a repeating circuit portion 2410 located within a tile processor 2320 included in FIG. As already discussed,
The part is repeated 6 times, that is, once for each pixel parameter.

Circuit portion 2410 includes adders 2412 and 2416,
It includes a multiplexer 2430 and a pixel register 2450.
To simplify the circuit, portion 2410 is shown in FIGS.
The multiplexers 2328 and 2330 of No. 7 are combined to form a common multiplexer 2430 shown in FIG. Registers 2404, 2406 and 2408 of FIGS. 36 and 37--specifically located in tile register 2310--hold initial values of common pixel parameters and slow and fast incremental coordinate values, respectively. As shown in FIG. 38, the register is connected to the corresponding input "A" of the multiplexer 2430 and the adders 2412 and 24 via the repeating circuit portions 2405, 2407 and 2409.
Connected to 16. Pixel register appearing on lead 2455
The output of 2450 is fed back to the input "D" of multiplexer 2430 and to the input "B" of adders 2412 and 2416 via lead 2417. The execute (C _O ) output produced by the adder is sent to control logic 2340 via leads 2415 and 2421 (see FIGS. 36 and 37). Output of adders 2412 and 2416 (O)
38 is the input "B" of the multiplexer 2430 as shown in FIG.
And sent to "C". Output of the multiplexer (Z)
Is applied to the input of pixel register 2450 via lead 2435.

The truth table 2500 of FIG. 39 is a multiplexer.
The operation of the 2430 is specified by the selection signals "S0" and "S1" applied to the multiplexer.

The state flowchart 2600 of FIG. 40 is the same as that of FIG.
The continuous operation occurring in the repeating circuit portion 2410 shown in FIG. In particular, the first state of the circuit, namely state 1
Is in either a waiting state or a standby state, during which no active operation occurs. The circuit continues to operate 2610 and 2615 until the "start of process" pulse appears on lead 817.
And this state is maintained as shown by continuous looping through NO path 2620 (see FIGS. 36 and 37).
As shown in FIG. 40, in response to this pulse, the circuit part 24
State 10 moves to the next state, State 2, as indicated by YES path 2625 exiting decision operation 2615. State 2
During, all initial and increment values are loaded into the appropriate registers. Once loaded, ie at the next clock pulse, the next state, ie state 3, is entered. While in this state, the multiplexer 24 shown in FIG.
3024 and adder 2416 connected to pixel register 2450
Sequentially increments the pixel parameter stored in register 2450 by the fast scan increment stored in register 2408, producing a series of continuously increasing parameter values. The continuous addition process occurs in state 3 via the loop defined by NO path 2645 exiting decision operation 2640.

The process continues until adder 2416 produces a pulse (fast carry) at the run output.
When this pulse occurs, it indicates that the pixel parameter value has been fully incremented in the fast scan direction. When the increment is fully executed, decision operation 2640 causes circuit portion 24
Change state 10 through YES path 2650 to the next state, state 4. While in this state, adder 2412
Is the multiplexer 2430 and register shown in FIG.
Connected to 2450, increments the pixel parameter value stored in register 2450 by the slow scan increment stored in register 2406. Then, the decision block shown in FIG.
The 2660 determines whether the pixel parameters have been fully incremented in the slow scan direction based on whether the adder 2412 produced a run (slow carry) pulse. If the parameter is not fully incremented, i.e.
If there is another corresponding row to process, decision operation 2660 returns the state of circuit portion 2410 to NO pass.
The state is returned to the state 3 via 2665, and the process is started from this line. On the other hand, if adder 2412 has generated an execute (slow carry) pulse, decision block 2660 directs circuit portion 2410 to YE
Through S path 2670, change to a done state, ie, an operation 2675 that causes state 5. This is a condition that occurs temporarily when control logic 2340 (see FIGS. 36 and 37) returns circuit portion 2410 to state 1 via operation 2610.

FIG. 41 is a block diagram of the contone logic 2354 in the pixel processor 2350 of FIGS. 36 and 37. As shown, the contone logic 2354 includes an address generator 2730, comparators 2740 and 2750,
Includes AND gate 2760 and multiplexer 2770. The address generator 2730 is connected to the outputs of the pixel_u and pisel_v registers 2710 and 2720 contained in the pixel register 2333 of FIGS. 36 and 37, and uses the contents of that register to set the parameter value pixel_u.
And generate the appropriate memory address of the current contone sampling location defined by pixel_v. The address is set via the lead wire 2355 in FIG.
It is applied to the address input of the tiling RAM 742. RA concerned
The contone data value read from M is
It is provided via 57 to the input "A" of the multiplexer 2770. The other input of the multiplexer, namely input "B"
Is connected via lead 2768 to a predefined color white contone value. Based on whether or not the main sampled pixel location is in the contone image, the multiplexer 2770 has a tiling RAM.
Either the sampled contone value read from the or a predefined white value is selected as the sampled contone data 2780. In particular, the parameter values pixel_u and pixel_v contained in registers 2710 and 2720 are also applied to the corresponding inputs of comparators 2740 and 2750. The values corresponding to the width (W) and height (H) of the contone image are the lead wires.
It is applied via 2712 and 2714 to the corresponding separate set of inputs of the comparator. Comparators 2740 and 2750
Produces a high level on each output lead 2745 and 2755 if the current pixel sampling position is in the image both vertically and horizontally. Make sure that leads 2745 and 27 are in place to ensure that the sampling location is within the image.
The output level of 55 is logically connected through AND gate 2760 to provide a select signal applied to the select (SO) input of multiplexer 2770 via lead 2765. Therefore, if the current contone sampling position is within the contone image, the multiplexer 2770 will use the sampled contone data read from the tiling RAM 742 as the sampled contone data 2780. Turn to output. On the other hand, if the location is not in the image, the multiplexer applies the predefined white value applied to the output lead as data 2780.

Truth table 2800 shown in FIG. 42 specifies the operation of multiplexer 2770.

FIG. 43 is a block diagram of clipping logic 2370 contained within pixel processor 2350 of FIGS. 36 and 37. Specifically, as shown in FIG. 43, the logic is pixel_k and pix in pixel_k register 2910 and pixel_l register 2920, respectively in pixel register 2333 (see FIGS. 36 and 37).
It is formed by an AND gate 2930 connected to the 16th bit of the el_l address. The AND combination of the bits is set to the multiplexer 2940 via the lead wire 2935 in FIG.
Connected to the select (SO) input of. Single-bit halftone cell data read from halftone reference RAM 717 is applied to input "A" of multiplexer 2940 via lead 2369. The zero value is applied to the other input "B" of this multiplexer. Output of the multiplexer (Z)
Is connected to output lead 853 and provides screened output data 2950. If the clipping address indicates that the current pixel is in the corresponding output tile, the signal appearing on lead 2935 is high, so multiplexer 2940 outputs the halftone cell output data appearing on lead 2369 to the output data. As output lead 853.

If the current pixel is not in the corresponding output tile, multiplexer 2940 sends a zero value on output lead 853 as the output value.

The truth table 3000 of FIG. 44 is a multiplexer.
Specifies the 2940 operation.

FIG. 45 shows the noise address logic 23 included in the pixel processor 2350 shown in FIGS. 36 and 37.
FIG. 58 is a block diagram of 58. The logic is pixel_x included in the pixel_x register 3110 as shown in FIG.
8 address bits from the address, bits <23:16>,
256 × 25, adjacent to the address bits corresponding to 8 bits included in the pixel_y register 3120, bits <23:16>
A memory address is formed in the noise data RAM717 at the 6th position. Specifically, registers 3110 and 3120 are located in pixel processor 2333 within tile processor 2320 (see FIGS. 36 and 37). pixel_x and pixel
The 32-bit address contained in the _y register is shown in FIG.
AND gate included in the noise address logic 2358 via respective leads 3112 and 3122 as shown in
Sent to 3140 and 3145. Noise_Bit_Mask 3115
Is applied to the other input of each AND gate via lead 3117. noise _bit _mask to pixel_x and pix
Lead 31 by logically connecting to the el_y address
The addresses appearing at 42 and 3146 are 8 bits <23:16> of each address. The bits are adjacent to each other to form a 16-bit address. The resulting 16-bit address selects one of the 4-bit memory locations in noise data RAM 717 via address lead 2361. The 4-bit value read from this location is the FONT ID 31
At 30, this value is applied to halftone reference address logic 2365 via lead 2362 (FIGS. 36 and 37).
reference).

Finally, FIG. 46 is a block diagram of the halftone reference address logic 2365 included in the pixel processor 2350 shown in FIGS. 36 and 37. This logic forms a 24-bit memory address in the halftone reference cell data RAM and includes AND gates 3225 and 3230 as shown in FIG. As mentioned above, the FONT_ID value selects one of 16 halftone stacks (fonts). The sampled contone data values select one of the 256 halftone reference planes that form the stack, pixel_x and pixel
_Y register-each 6-bit is 64 x 64-bit select Collectively selects the current sampling position in the halftone reference plane.

Specifically, the 24-bit memory address is
4-bit FONT ID address appearing on lead 2362, then 8-bit sampled contone value 2780 appearing on lead 2366, plus 6 pre-defined in pixel_x and pixel_y address registers 3110 and 3120 12-bit address based on the lower integer address bits <15:10>. The lower address bits are AND gate 3225 and
Pixel_x held in register 3110 via 3230
And the full current value of pixel_y address to Font_Bi
It is formed by logically combining with the value of t_Mask 3215. Therefore, the pixel_y and pixel_y registers 31
10 and 3120 contents lead 3210 and 32 respectively
Applied via 20 to one input of AND gates 3225 and 3230. The value of Font_Bit_Mask 3215 is applied to another input of each of the gates via lead 3218. The value of font _bit _mask is pixel_x and
By logically combining each of the pixel_y addresses, the address appearing on leads 3228 and 3233 becomes 6 bits <15:10> for each of the addresses. The bit is passed through the address lead 2367 to
It applies to the halftone reference data RAM717 as part of the bit memory address. The data stored at the addressed location in this RAM is the single-bit cell data 23
69, and as described above, via the lead wire 2369, the clipping logic 2370 (FIG. 3) as input data.
6, FIG. 37 and FIG. 43).

As is clear from the above, a person skilled in the art can perform parallel processing by combining a plurality of tile and pixel processors (TPP) 740 with a microcomputer of the invention having a common two-chip structure. It will be appreciated that performance can easily be scaled to increase capacity. By scaling the number of TPPs upwards, the parallelism is increased, which results in increased rotation, scaling and / or throughput of halftoned images.

As will be described in detail below, instead of connecting only one TPP to the microcomputer 713, as shown in FIG.
As shown in FIG. 4, several TPPs can be connected to the microcomputer via a bus and controlled by the microcomputer. Image parameter is all TPP
, But each TPP will process specific non-overlapping portions of the image, horizontal strips, etc., from different starting points, with appropriate instructions from the microcomputer. When the TPP is initialized, the microcomputer causes the TPP to process the image portion independently. During the processing of the TPP, the microcomputer can initialize the next continuous TPP, then issue a command to the TPP to start the processing, and so on. Thus, all TPPs can process corresponding image portions that are essentially parallel, albeit slightly alternating in time. Each TPP may have a microcomputer-loaded tiling RAM with the particular image strip (or another image portion) used by that TPP. In addition, each TPP
It can be configured to write to a separate buffer such as a FIFO and then block transferred to a common output buffer when its contents are appropriate. While each TPP is processing the image portion, the microcomputer calculates the position of the corresponding portion of the output image, and the corresponding portion of the output image is written with the output data currently provided by that TPP. The position of the corresponding part of the output image could be calculated. When the TPP finishes processing, the microcomputer block-transfers the output data to the image portion. Furthermore, the TPP can also be configured to process separate tiles rather than strips. In addition, the TPP can operate in a common tiling RAM where successive contone values are processed by the TPP and data is written to the corresponding output locations in the output image on a time alternating, output interleaved basis. For example, assuming you use 4 TPPs, each TPP writes all 4th output locations. That is, the first TPP writes the output data to the output positions of the first, fifth, ninth ...
The second TPP writes the output data to the second, sixth, tenth ... Output positions, and so on, and so on through the entire output image. The output data is the first TPP
Next, the second, third, and fourth TPPs are repeatedly written in a round-robin manner. Therefore, with the control by the common control microcomputer
By repeating the TPP, the processing capacity is reduced to a single TP.
Significant increase over the use of one P.

Furthermore, although the halftone reference data has already been examined for multiple stacks of multi-plane single-bit halftone data, each stack should be replaced by a single matrix of 8-bit threshold values instead of single-bit halftone dot values. You can In this case, the halftone reference address logic 2365 (see FIGS. 36, 37 and 46) is easily modified to include a comparator that compares each sampled contone value to the corresponding sampled threshold in the threshold matrix. Could be
The single-bit result of the comparison is that, if the contone value is equal to or exceeds the corresponding threshold value, the high-level bit otherwise the zero-bit will form the single-bit halftone output data. Let's It would also be possible to use the noise data in a manner similar to that described above, for example to pseudo-randomly select one of the 16 special threshold matrices available at any one time. Current pixel_x and pix
The el_y parameter value will define the position of the threshold matrix to be read.

Further, the inventive screener could use contone interpolation if the contone sampling times appear too coarse. In this case, for example, in block 2135 (see Figures 33 and 34), the parameters pixel_u and pixel_v select continuous contone values that are interpolated as a whole based on the minority values of the parameters to produce intermediate contone values. The halftone contone value is then sent as output data, but when halftone processing is used, as input to the halftone process to produce halftone output data.

Furthermore, although the present invention has been described using a write engine that produces a bi-level output, it is also possible to use a write engine that produces a multi-bit output. In this example, multiple screeners providing slightly different fonts would be operated in parallel using the same input contone values. One dot font produces halftone dots that are slightly larger than normal,
Other dot fonts appear to produce halftone dots that are slightly smaller than normal. Each screener will work independently of the other screeners. If both screeners produce the same signal, the write engine will produce a write spot. In other words, it seems that the usual method is not taken. But if the screener produces different output signals, the write engine
It will produce a medium density, ie a predefined level of writing spots between perfect black and white. Thus, a tri-state write engine will write halftone dots with relaxed edges, i.e. suppressed "zigzag" edges. Since the dots contain a significantly reduced high frequency content compared to the unsuppressed dots, the so-called automoire pattern is considerably suppressed. This crack pattern also results from the beating that occurs between the spatial distribution of the ideal halftone dot pattern and the writing pattern used by the writing engine.
It is possible to further increase the degree of dot relaxation and auto moire suppression by using the writing engine with the higher number of levels. Unfortunately, the use of multi-level write engines with multiple bi-level screeners, especially increases system complexity and cost. In practicing that approach, there is a design tradeoff between the acceptable amount of automoisture and the acceptable cost and complexity of the image processing system.

While various embodiments of the invention have been described in detail herein, those skilled in the art will readily be able to construct numerous other embodiments incorporating the teachings of the invention. INDUSTRIAL APPLICABILITY AND BENEFITS The present invention relates to digital image processing systems, and more particularly to
It is useful as part of a processing system that implements a page description language. The invention has the advantage that image rotation, scaling and digital halftone screening can be performed very accurately, inexpensively, fast and in a very flexible way. The present invention provides accurate and complex image processing capabilities readily applied to output writers, but is not necessarily limited to relatively inexpensive laser printers.

[Brief description of drawings]

FIG. 1 illustrates image scaling according to the present invention,
1 is a very high level simplified block diagram of a system 5 for implementing a page description language that provides rotation and halftone processing capabilities.

2 diagrammatically illustrates various tile-based operations collectively forming the inventive process for performing image scaling, rotation and halftone processing of the system 5 shown in FIG.

3 diagrammatically illustrates various tile-based operations collectively forming the inventive process for performing image scaling, rotation and halftone processing of the system 5 shown in FIG.

4 diagrammatically illustrates various tile-based operations collectively forming the inventive process for performing image scaling, rotation and halftone processing of the system 5 shown in FIG.

5 diagrammatically illustrates various tile-based operations collectively forming the inventive process for performing image scaling, rotation and halftone processing of the system 5 shown in FIG.

FIG. 6 diagrammatically illustrates various tile-based operations collectively forming the inventive process for performing image scaling, rotation and halftone processing of the system 5 shown in FIG.

FIG. 7 schematically illustrates contone sampling and writing of output data for various spatially corresponding contone boxes and output blocks shown.

FIG. 8 shows a single contone box in detail.

9 shows in detail an output block corresponding to the contone box shown in FIG.

FIG. 10 shows a linear spatial correspondence between output sampling positions in output blocks, halftone sampling positions in corresponding halftone scaling cells, and contone sampling positions in corresponding tiles. The latter two are specified by the output sampling position.

FIG. 11 is an image processing system using the present technique.
A high-level block diagram of the 700 is shown in both figures.

FIG. 12 is an image processing system using the present technique.
A high-level block diagram of the 700 is shown in both figures.

FIG. 13 is an image processing system using the present technique.
A high-level block diagram of the 700 is shown in both figures.

14 is a block diagram showing a two-chip implementation (microcomputer 713 and TPP processor 740) of the inventive technique used in the system 700 shown in FIGS. 12 and 13. FIG.

15 shows a flowchart of a main loop 900 executed in the microcomputer 713 of the TTH circuit 800 shown in FIG.

16 shows a flowchart of a main loop 900 executed in the microcomputer 713 of the TTH circuit 800 shown in FIG. 14 in both figures.

17 shows a flowchart of a main loop 900 executed in the microcomputer 713 of the TTH circuit 800 shown in FIG. 14 in both figures.

FIG. 18 is a main loop 900 shown in FIGS. 16 and 17.
9 is a flow chart of a tile processing routine 1000 formed in steps 925-945 that occurs in step 1.

FIG. 19 is a flowchart of step 1010 for setting a block size and a tile size, which is executed by the tile processing routine 1000 shown in FIG.

20 is a flowchart of step 1020 of calculating the number of tiles executed by the tile processing routine 1000 shown in FIG.

FIG. 21 is a flowchart of step 1030 of changing the set pixel coordinates, which is executed by the tile processing routine 1000 shown in FIG.

22 is a flowchart of step 1040 for changing the set pixel coordinates, which is executed by the tile processing routine 1000 shown in FIG.

FIG. 23 schematically shows the offset position existing between the edge of the output block and the corresponding corner of the tile caused by the rotation of the tile within the block.

FIG. 24 is a step 1050 of calculating a block position offset executed by the tile processing routine 1000 shown in FIG. 18;
The flow chart of is shown in both figures.

FIG. 25 is a step 1050 for calculating a block position offset executed by the tile processing routine 1000 shown in FIG. 18;
The flow chart of is shown in both figures.

FIG. 26 is a step 1050 for calculating a block position offset executed by the tile processing routine 1000 shown in FIG. 18;
The flow chart of is shown in both figures.

27 shows a high level flowchart of tile processing step 1060 executed by the tile processing routine 1000 shown in FIG.

FIG. 28: Step 1060 of processing the tile shown in FIG. 27.
A detailed flowchart of is shown in both figures.

FIG. 29: Step 1060 of processing the tile shown in FIG. 27.
A detailed flowchart of is shown in both figures.

FIG. 30: Step 1060 of processing the tile shown in FIG. 27.
A detailed flowchart of is shown in both figures.

31 shows a high level flowchart of a process tile routine 1770 executed as part of step 1060 of processing tiles shown in FIGS. 29 and 30. FIG.

32 is a detailed flowchart of the process tile routine 1770 shown in FIG.

FIG. 33 is a high level flowchart of a process pixel routine 1970 executed as part of the process tile routine 1770 shown in FIG.

34 is a detailed flowchart of the process pixel routine 1970 shown in FIG.

FIG. 35 illustrates in both figures a high level block diagram of an embodiment of the tile pixel processor (TPP) 740 shown in FIGS. 11 and 14.

FIG. 36 shows in both figures a high level block diagram of an embodiment of the tile pixel processor (TPP) 740 shown in FIGS. 11 and 14.

FIG. 37 illustrates in both figures a high level block diagram of an embodiment of the tile pixel processor (TPP) 740 shown in FIGS. 11 and 14.

38 is a repeating circuit portion present in the tile processor 2320 included in the TPP 740 shown in FIGS. 36 and 37. FIG.
24 is a block diagram of 2410. FIG.

39 is a truth table of the multiplexer 2430 included in the repeating circuit portion 2410 of the tile processor shown in FIG. 38.
2500.

40 is a state flow chart 2600 illustrating sequential operations occurring in the repeating circuit portion 2410 of the tile processor shown in FIG. 38.

FIG. 41 is a pixel processor 23 shown in FIGS. 36 and 37.
FIG. 10 is a block diagram of a contone logic 2354 included in 50.

42 is a truth table 2800 of the multiplexer 2770 included in the contone logic 2354 shown in FIG. 27. FIG.

FIG. 43 is a pixel processor 23 shown in FIGS. 36 and 37.
3 is a block diagram of clip logic 2370 included in 50. FIG.

44 is a truth table 3000 of the multiplexer 2940 included in the clip logic 2370 shown in FIG. 43.

FIG. 45 is a pixel processor 23 shown in FIGS. 36 and 37.
5 is a block diagram of noise address logic 2358 included in 50. FIG.

FIG. 46 is a pixel processor 23 shown in FIGS. 36 and 37.
Halftone scaling address logic included in 50 2365
It is a block diagram of.

[Explanation of symbols]

2 Input contone image 3 Output image (1 bit / pixel) 4 Page description language Command texture data Input contone image data (8 bits / pixel) 5 Text: A, B 6 Page description language (PDL) processing circuit 7 Raster Writing spots 8 Digital marking engine 9 Output buffer 10 Processor 11 Oriented output page 12 Output image

Front Page Continuation (72) Inventor Anthony James Leon III, New York, USA 14534 Pittsford East Park Road 34

Claims (12)

[Claims] 1. An apparatus for producing an output image from an input image, wherein parameter values are continuously specified to identify one block different from each other among a plurality of blocks, and all the blocks collectively form an output image. Then, different individual tiles are respectively identified from the plurality of tiles corresponding to the one block, each of the tiles has a plurality of pixel values of different corresponding portions of the input image, and all the tiles are collectively set. Tiles that form the input image
Block definition means and output pixel data that processes pixel values in individual tiles according to a predetermined procedure corresponding to the above-mentioned parameter values, and uses each pixel as a reference for one block in the output image. And tiling means in which all of the output pixel data in all of the blocks form an output image, and an output image from the input image. 2. The apparatus of claim 1, wherein the tile block defining means is a program processor to produce an output image from an input image. 3. The apparatus according to claim 2, wherein the tile processing means is a dedicated hardware circuit to produce an output image from an input image. 4. The apparatus according to claim 3, wherein the tile processing means comprises a tile processor and a pixel processor, the tile processor depending on the corresponding value of the parameter value and the pixel sampling increment. Generating a pixel sampling address for a pixel in the pixel processor, the pixel processor being in an individual tile to generate corresponding output data in response to the pixel sampling address, and being addressed by the sampling address. An apparatus for producing an output image from an input image, characterized by successively processing each one of a plurality of existing pixel values. 5. The apparatus of claim 4, wherein the tile block defining means comprises means for generating pixel sampling increments and starting addresses of individual tiles as the parameter value, the pixel sampling increments being blocks. An apparatus for producing an output image from an input image, characterized by specifying an increment between successive sampling positions in the input image corresponding to a movement amount between two adjacent positions within one. 6. The apparatus according to claim 5, wherein the tile processor is responsive to the parameter value.
Apparatus for producing an output image from an input image, characterized in that it comprises means for incrementally stepping through individual blocks on a pixel-by-pixel basis to generate a pixel sampling address and a halftone sampling address for each pixel in a block. .. 7. The apparatus according to claim 5, further comprising a first memory storing a continuous tone (contone) value that collectively forms at least individual tiles of the input image. Means for generating a series of continuous tone sampling addresses to sample the tiles in response to corresponding values of the pixel sampling increments, wherein the pixel processor is connected to the first memory and the continuous tone sampling addresses An apparatus for producing an output image from an input image, comprising means for sampling the data stored in the first memory in response to each of the first and producing sampled contone values. 8. The apparatus of claim 7, further comprising a second memory storing a predefined pattern, the tile processor providing a series of intermediate tone sampling addresses in response to corresponding individual pixel sampling increments. The pixel processor is connected to the second memory, and the data stored in the second memory is sampled according to each intermediate tone sampling address, and the corresponding intermediate tone output value is provided. An apparatus for producing an output image from an input image, characterized by comprising means for producing. 9. The apparatus of claim 8, wherein the pattern comprises a plurality of predefined midtone reference planes forming a midtone reference stack.
Also, each of the reference planes stores a different depiction of a midtone dot, and the second memory sampling means further comprises means for selecting one midtone reference plane in response to the sampled contone value; Means for sampling the selected midtone reference plane at a pixel location defined by each of the sampling addresses to produce a corresponding midtone output value, an apparatus for producing an output image from an input image. .. 10. The apparatus of claim 9, wherein the tile processor traverses each sampling line of an individual tile in a fast scan direction in a rasterized fashion in response to the tile and tile sampling increment start pixel. , An input image to an output image, characterized in that it comprises means for generating a series of pixel sampling and halftone addresses that are incremented in the slow scan direction from each sampling line of each tile to the next consecutive sampling line, over the entire tile. Device that produces. 11. The apparatus of claim 8, wherein the pattern comprises a predefined threshold matrix having an array of predefined threshold values, the second memory sampling means further comprising the halftone sampling. Means for sampling the threshold value at the pixel position defined by each of the addresses to create a sampled threshold value, and comparing the sampled threshold value with the sampled contone value and responding according to the result Means for producing halftone output values for producing an output image from the input image. 12. The apparatus of claim 11, wherein the tile processor traverses each sampling line of an individual tile in a fast scan direction in a rasterized fashion in response to the tile and tile sampling increment start pixel. , An input image to an output image, characterized in that it comprises means for generating a series of pixel sampling and halftone addresses that are incremented in the slow scan direction from each sampling line of each tile to the next consecutive sampling line, over the entire tile. Device that produces.