JPH05257964A - Section-variable data processor - Google Patents

Abstract

PURPOSE:To make it possible to execute operation in parallel with the input of a signal by successively setting up different time sections so that a time section allowed to analyze a time sequential signal maintains a prescribed length and then executing the processing of the time sequential signal. CONSTITUTION:A clock signal CLK, a reset signal RESET and a synchronizing analysis-permitted signal w(t) are inputted to a control circuit 1. Signals included within the time sections allowed to execute analysis of time sequential signals A(t) are successively inputted to a delay means such as a shift register 21 to obtain delay signals B(t), an effective difference signal C(t) is found out by a differential operation means in each input of the signal included in the analysis-permitted time section and the difference signals C(t) are accumulated to find out an accumulation signal D(t). Consequently the short-time average value of signals in the analysis-permitted sections of the signals A(t) is found out as the signal D(t) and the signal D(t) can be successively outputted while successively inputting the signals A(t).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a section variable data processing apparatus for calculating a moving average value (or cumulative value), a moving least squares regression coefficient, etc. of data in a variable section which is sequentially changed in time series. As a time series signal analysis device,
For example, there is an ultrasonic diagnostic device. An ultrasonic diagnostic apparatus transmits ultrasonic waves into a heterogeneous medium such as a living body, receives a reflected wave (echo) from the ultrasonic wave, obtains a received signal, analyzes the received signal, and measures the acoustic characteristic value of the medium. It is a device that visualizes. As one of the time-series signal processing in this ultrasonic diagnostic apparatus, in order to measure the acoustic characteristics of the medium, various induction amounts derived from the received signal are processed to obtain the attenuation coefficient gradient of the ultrasonic wave in the medium. A method for obtaining β has been proposed (see Japanese Patent Laid-Open No. 62-109553). Here, the least-squares calculation is performed to regress the induction amount within a time window of width T to a predetermined n-th order function f (t) to obtain the coefficient of the function.

The present invention relates to an interval variable data processing device useful for analyzing such a time series signal.

[0003]

2. Description of the Related Art When analyzing various time-series signals, when the time-series signal to be analyzed (here, this is y (t)) contains unnecessary noise that is an error in analysis. In addition, it is preferable to perform the analysis using only the data other than the time without using the data at the time when the noise is included.

As one of the methods for realizing this, by processing the original time-series signal y (t), the time at which noise is included takes a value of 0, and the time at which noise is not included takes a value. There has been considered a method of obtaining a binary analysis permission signal w (t) which takes 1 (see Japanese Patent Laid-Open No. 63-105742). The analysis is performed by using only the time series signal y (t) at the time when the analysis permission signal w (t) takes the value 1 to remove the influence of noise contained in the time series signal y (t). be able to.

However, in this case, if the analysis section length is kept constant, if the section of w (t) = 0 is long within the analysis section length, the number of data used for the analysis becomes insufficient, which is sufficient. Since analysis of accuracy cannot be performed, the analysis permission signal w
The idea of making the analysis interval length variable so that the number of data used for analysis is always constant without using the data at the time (t) = 0, and a concrete device for realizing this has been proposed. (See JP-A-63-311188 and JP-A-63-316266).

Hereinafter, an example of an operation in which the analysis section length is variable will be described with reference to the drawings. FIG. 7 is a diagram showing an example of the time series signal y (t) to be analyzed and the analysis permission signal w (t) corresponding to the time series signal y (t). Of the time-series signal y (t), the data in the section where the analysis permission signal w (t) = 1 is the data that can be effectively analyzed.
The data in the section of the analysis permission signal w (t) = 0 is data that cannot be used for analysis because noise is superimposed.
Here, when performing analysis, a variable analysis section length is obtained so that the number of data for which w (t) = 1 is constant,
The analysis permission signal w is added to the time series signal y (t) within the analysis section length.
The signal w (t) .y (t) weighted by (t) is used for data analysis.

FIG. 8 shows the above-mentioned Japanese Patent Laid-Open No. 63-10574.
6 is a block diagram showing a method described in Japanese Patent Publication No. 2) for obtaining an analysis permission signal w (t) based on a reception signal (echo signal) of an ultrasonic wave. The echo signal is the envelope detection circuit 40.
To the envelope signal y ₁ (t) that carries only the envelope of the echo signal.
This envelope signal y ₁ (t) is input to the CFAR processing system 41. Here, CFAR is Constant False
e Alarm Rate stands for, when the the envelope signal y ₁ the short-term average of (t) and <y ₁ (t)>, y ₁ (t) -
A method for calculating <y ₁ (t)> (“Statistical properties of echoes from inhomogeneous media” IEICE Technical Report U)
S84-38 Okushima, Otsuki et al.). Therefore, the output signal y ₂ (t) of this CFAR processing system 41 is the envelope signal y.
_The envelope signal y ₁ (t) from which the low frequency components of ₁ (t) have been removed
Is a signal that carries the high frequency component of. This output signal y
₂ (t) is input to the two comparators 42 and 43 and compared with the lower limit setting value and the upper limit setting value, respectively, and the output signal of the comparator 42 remains as it is, and the output signal of the comparator 43 is inverted by the NOT circuit 44. The signals are input to the AND circuit 45, and the AND circuit calculates an AND of the two input signals to generate an analysis permission signal w (t). That is, here, when the envelope signal y ₁ (t) exceeds the upper limit setting value and the lower limit setting value than the short-time average <y ₁ (t)> and jumps upward and downward, noise is mixed. The analysis permission signal w (t) is set to 0, and it is assumed that at least large noise is not mixed when it is within the range between the upper limit setting value and the lower limit setting value. Is set to 1.

Further, the envelope signal y ₁ (t) compensates for the time required for data processing in the CFAR processing system 41 and the like, and makes the delay circuit 4 synchronized with the analysis permission signal w (t).
The signal is input to 6 and delayed for a predetermined time, and output as a time series signal y (t) to be analyzed. A load signal is input to the counter 47, and the counter 47 outputs a time signal t representing the time t of the analysis permission signal w (t) and the time series signal y (t).

FIG. 9 shows the above-mentioned Japanese Patent Laid-Open No. 63-31626.
FIG. 6 is a block diagram showing an example of data processing using a time-series signal y (t) and an analysis permission signal w (t), which is described in Japanese Patent No. 6 publication. Here, the time series signal y as shown in FIG.
The slope (coefficient a ₁ ) is obtained when (t) is regressed to the linear function f (t) = a ₁ t + a ₂ (1) using the method of least squares. This coefficient a ₁ is calculated by the following equation: a ₁ = [TΣw (t) y (t) t− {Σw (t) y (t)} · {Σw (t) t}] / [TΣw (t) t ² -{Σw (t) t} ² ] ... (2)

In FIG. 9, the analysis section calculation circuit 100 is shown.
Is a circuit that inputs the clock CLK, generates the time signal t, and outputs the time signal t. The multiplication / integration circuits 110, 120, and 13
While performing the operations described below at 0 and 140,
The switches 101 and 102 are switched as shown, and during this time, the memories 111 and 112; 121 and 122;
The time signal t is input to 131, 132; 141, 142 as an address signal.

Multiplication / integration arithmetic circuits 110, 120, 13
In 0 and 140, W (t) .t, W (t) .t ² , W (t) .y (t) .t, W (t). y
(t) is calculated, and the calculation results are sequentially accumulated. The accumulated results are stored in memories 111 and 112; memory 1 respectively.
21, 122; memories 131, 132; memories 141,
It is input to 142 as data. In this way, each of the memories 111, 112;
2; 131, 132; 141, 142 each address t
(Time signal t) includes Σ w (t) ・ t, Σ w (t)
・ T ² , Σ W (t) ・ y (t) ・ t, Σ W (t) y (t) is stored.

After that, the switches 101 and 102 are switched to the opposite sides to the states shown in the drawings, and the memory 111 and
The data stored at the address t ₂ is read from 121, 131, and 141, and the memory 112, 1
The data stored at the address t ₁ is read from 22, 132, 142, and the difference calculation circuits 113, 123,
It is input to 133 and 143. Each difference calculation circuit 113, 1
23, 133, 143, the difference between the two input data is calculated, and the calculation results are

[0013]

[Equation 1]

Is output as Here, at the time of this reading
At the point, in the analysis interval calculation circuit 100, the time window T = Σ W (t)
= T₁−t₂Is always constant, that is, used in the analysis
Time signal so that the number of valid data is always constant
t₁, T₂Are sequentially determined and output, and thus each difference
Output from the arithmetic circuits 113, 123, 133, 143
Each signal x₁(t), x ₂(t), x₃(t), x_Four(t) is diagonal to Figure 7.
It is the cumulative value of the data within the variable analysis section length shown by the line.

Each difference calculation circuit 113, 123, 133, 1
The respective signals output from 43 are x ₁ (t), x ₂ (t), x ₃ (t), x ₄
(t) is input to the arithmetic circuit 150, and the arithmetic circuit 15
At 0, the input signals x ₁ (t), x ₂ (t), x ₃ (t), x
_The above-mentioned equation (2) is calculated using ₄ (t), whereby the slope (coefficient a ₁ ) in the regression equation of equation ( ₁ ) is obtained.

[0016]

As described above, for example, the circuit shown in FIG. 9 is used to execute an operation in which the analysis interval length is variable. However, in the conventional circuit, a large amount of calculation is performed as shown in FIG. There is a problem that a memory is required and the size of the entire apparatus increases, resulting in high cost. Further, in the configuration shown in FIG. 9, it is necessary to read the data from the memory after the input of the series of time-series signals y (t) is completed, and until the final output is obtained from the input of the time-series signals y (t). There is also the problem of taking too much time.

In view of the above circumstances, the present invention requires a small amount of memory and therefore can be made compact and low in cost. Moreover, while a signal is being input, an operation can be performed in parallel therewith. It is an object of the present invention to provide a variable section data processing device capable of performing the same.

[0018]

A first section variable data processing apparatus of the present invention for achieving the above object comprises a time series signal A (t) including a time section in which analysis is prohibited, and the time series signal A (t). By using the time-series analysis permission signal W (t) that indicates the inhibition or permission of the analysis of the signal A (t), the time period during which the analysis of the time-series signal A (t) is permitted maintains a predetermined length. The time series signal A (t) within the time interval is set by sequentially setting different time intervals
(A) Time-series signal A (t) in a time section for which analysis is permitted
To sequentially obtain and delay the delayed signal B (t). (B) Time-series signal A (t) within a time period during which analysis is permitted.
And a delay signal B (t) delayed by a time corresponding to the predetermined length from the time series signal A (t), and the time series signal A (t) and the delay signal B (t) are input. Difference calculating means for calculating difference signal C (t) by calculating difference (C) Cumulative signal D by accumulating difference signal C (t)
It is characterized in that each means of accumulating means for obtaining (t) is provided.

Here, the present invention may be configured by combining a plurality of devices having the above-mentioned features, for example, a device for performing one integrated calculation such as the above-mentioned equation (2). That is, the second section variable data processing device of the present invention configured as described above analyzes the time series signal y (t) including the time section in which analysis is prohibited and the time series signal y (t). By using the time-series analysis permission signal w (t) indicating prohibition and permission, different time intervals are sequentially set so that the time interval in which the analysis of the time-series signal y (t) is allowed maintains a predetermined length. hand,
In a section variable data processing device for processing a time series signal y (t) in the time section, a time series signal y (t), a time signal t synchronized with the time series signal y (t), or a time series signal When the signal obtained by calculating the signal y (t) and / or the time signal t is Ai (t) (i = 1, 2, ... n), (D) time interval in which analysis is allowed Each of the signals Ai (t) in the time interval in which a plurality of delay means (E) analysis is possible, which outputs each delayed signal Bi (t) by inputting and delaying each signal Ai (t) in
The delayed signals Bi (t) delayed by a time corresponding to the predetermined length from the respective signals Ai (t) are input, and the respective signals Ai (t) are input.
And a plurality of difference calculating means (F) for calculating the difference signal Ci (t) by calculating the difference between each delay signal Bi (t) and each delay signal Bi (t). A plurality of accumulating means for obtaining (t) (G) A plurality of accumulating signals xi obtained by a plurality of accumulating means
(t) (i = 1, 2, ..., N) is input to perform an arithmetic operation to obtain an arithmetic signal F (t).

Here, in the second section variable data processing device of the present invention, the calculation signal F (t) is, for example, a signal representing a regression coefficient.

[0021]

In the first section variable data processing apparatus of the present invention, the time-series signal A (t) is added to the delay means such as the shift register.
Of the time-series signals A (t) are analyzed by the difference calculation means by sequentially inputting the signals within the time period for which the analysis is allowed to obtain the delayed signal B (t) (above (A)). A valid difference signal C each time a signal within an allowable time period is sequentially input.
(t) is obtained (above (B)), and the difference signal C (t) is accumulated to obtain an accumulated signal D (t) (above (C)). The short-time average value of the section where the analysis of (t) is allowed is obtained as the cumulative signal D (t). Here, although some memory is required as the delay means, a large-capacity memory for storing all intermediate calculation results as in the conventional case (see FIG. 9) is not required, and therefore the size and cost are reduced. In addition, the cumulative signal D (t) can be sequentially output while the time series signal A (t) is sequentially input, and the calculation result can be obtained earlier.

Further, a second section variable data processing device of the present invention is provided with a plurality of configurations of the first section variable data processing device, and therefore the effects of the first section variable data processing device are obtained. After being carried as it is, instead of the circuit shown in FIG. 9, for example, it is possible to perform an operation for obtaining coefficients such as a regression line and a regression curve.

[0023]

EXAMPLES Examples of the present invention will be described below. Figure 1
2 is a circuit block diagram showing an embodiment of the first section variable data processing device of the present invention, and FIGS. 2 to 4 are timing charts showing the operation of the circuit shown in FIG.

For example, the circuit shown in FIG. 8 generates the time series signal y (t) and the analysis permission signal w (t) synchronized with the clock signal CLK (see FIGS. 2A to 2C). The time-series signal y (t) may be subjected to preprocessing such as y (t) · t. Therefore, here, the time-series signal A (t ) (See Fig. 2 (d))
Are input to the circuit shown in FIG. Along with this, the analysis permission signal w (t) is also input to the circuit shown in FIG. 1 after being delayed from the time-series signal y (t) by the amount of deviation in the timing of generating the time-series signal A (t). Alternatively, FIG.
This timing adjustment may be performed by the control circuit 1 shown in FIG.

The control circuit 1 shown in FIG. 1 includes a clock signal CLK, a reset signal RESET, and a time series signal A.
The analysis permission signal w (t) synchronized with (t) is input, and various clock signals, control signals, and the like shown in this figure, which will be described later, are generated. Here, the clock signal CLK input to the control circuit 1 is a clock signal which repeats at a constant cycle as shown in FIG.

The time-series signal A (t) is input to the shift register 21 which is an example of the delay means according to the present invention and the adder circuit 22 (which calculates the difference) which is the difference calculation means according to the present invention. .. In this time-series signal A (t), the shaded portion means unnecessary data. In the control circuit 1, based on the input analysis permission signal w (t), the time series signal A
The shift register 2 is generated by generating the clock signal CLK-SR shown in FIG. 2E so that only valid data of (t) except unnecessary data is taken into the shift register 21.
Output to 1. As a result, only valid data of the time-series signal A (t) is fetched into the shift register 21, and the signal consisting of this valid data is shifted by the shift amount = 5 in this embodiment, and the delayed signal is obtained. B
It is output as (t) (see FIG. 2 (f)). The delayed signal B (t) is input to the adder circuit 22 together with the time series signal A (t).

The operation start signal OP and the clock signal CLK-SUB are input to the adder circuit 22 as control signals. The adder circuit 22 is a circuit that calculates C (t) = A (t) -B (t) and outputs a difference signal C (t). However, in the initial stage when the calculation is started, the shift register 21 Since the delay signal B (t) is not output until is full, the calculation start signal OP is input at the timing when the calculation of C (t) = A (t) -B (t) in the adder circuit 22 is started. It is the one. From the adder circuit 22, the calculation start signal OP
Before is input, the time series signal A (t) input to the adding circuit 22 is output as it is as a signal C (t), and after the calculation start signal OP is input, C (t) = A
(t) -B (t) is output. Here, this adder circuit 22
Is a clock signal CLK-SUB shown in FIG.
That is, the clock signal CL input to the shift register 21
The clock signal of the same timing as K-SR is input,
The time-series signal A is generated by this clock signal CLK-SUB.
The difference calculation is performed only on valid data excluding unnecessary data in (t), and is output as a difference signal C (t) (see FIG. 3 (h)).

The difference signal C (t) is input to the accumulating circuit 23 which is an example of accumulating means according to the present invention. The accumulation circuit 23 has a clock signal CLK-ACC obtained by shifting the clock signals CLK-SR and CLK-SUB input to the shift register 21 and the addition circuit 22 by one basic clock (see FIG. 2A). (See FIG. 3 (i)) is input, and thereby the accumulated signal D (t) (see FIG. 3 (j)) is generated. Here, the accumulated signal D (t) is not a signal obtained by accumulating data from a predetermined initial time, but a signal obtained by accumulating five effective data of the time series signal A (t). For example, the clock signal CLK-A shown in FIG.
At the rising edge of the CC number 1 clock pulse, D (t) = D ₁ = A ₁ + A _-1 + A _-2 + A _-3 + A _-4 , and at the rising edge of the next number 2 clock pulse, D (t) = a _{D 1 + C (t) =} D 1 + a 2 -A -4 = a 2 + a 1 + a -1 + a -2 + a -3. In this way, as the signal D (t), the cumulative value of the five effective data of the time series signal A (t) is obtained, and mathematically dividing this by 5 gives the interval average value. It will be.

FIG. 4 (k) is shown in FIG. 3 for ease of understanding.
The clock signal CLK-ACC and the cumulative signal D (t) shown in (i) and (j) are rewritten. For example, as shown in FIG. 4 (k), the cumulative signal D ₁ becomes D ₁ = A ₁ + A ₋₁ + A ₋₂ + A ₋₃ + A ₋₄ .

This accumulated signal D (t) is input to the FIFO3 which is the expansion / contraction means in the present invention. Clock signals RCLK and WCLK and reset signals RRST and WRST are also input to the FIFO 3. This FIFO3
Input data is captured at each rising timing of the clock signal WCLK after the reset signal WRST is input, and the captured data is captured at each rising timing of the clock signal RCLK after the reset signal RRST is input. It is a first-in first-out memory that is taken out in the order in which As the clock signal WCLK on the write side, the clock signal WC shown in FIG.
LK, that is, a clock signal in which CLK-ACC input to the accumulating circuit 23 is shifted by one clock pulse of the basic clock signal CLK (see FIG. 2A) is generated by the control circuit 1 and input to the FIFO 3. .. Further, the clock signal RCLK on the read side is the clock signal W for convenience of illustration.
Regardless of the timing of CLK shown in FIG. 4, it is a signal obtained by delaying the write-side clock signal WCLK by a time window for cumulative calculation or slightly longer than that.

Although the FIFO 3 is not always necessary, originally, for example, the data corresponding to the time 1 is the time 5,
The cumulative signal D ₅ calculated using the data of 2, 1, -1, and -2 should be output, and this timing adjustment is performed by using the FIFO 3. In this way, the cumulative signal E (t) whose timing has been adjusted is output from the FIFO 3.

FIG. 5 is a circuit block diagram showing another embodiment of the first section variable data processing device of the present invention.
In this embodiment, the shift register 51, the adder circuit 52,
The same basic clock signal C is applied to the accumulation circuit 53 and the FIFO 6.
LK is input, and together with this, enable signals SREN, SUBEN, A generated by the control circuit 4 are applied to the shift register 51, the adder circuit 52, and the accumulator circuit 53.
CCEN is input, and each enable signal REN, WEN for reading and writing is input to the FIFO 6.
Here, for example, when the shift register 51 is taken as an example, the clock signal CLK and the enable signal SREN have the same operation as the clock signal CLK-SR shown in FIG. Thus, instead of generating various clock signals themselves in the control circuit, an enable signal may be generated. Since the circuit operation in this case is obvious from the case of FIG. 1, its explanation is omitted here.

FIG. 6 is a circuit block diagram showing an embodiment of the second section variable data processing device of the present invention. FIG. 6 shows a circuit for performing the same calculation as the conventional example shown in FIG. 9 (equation (2) described above). In this figure,
Each of the section variable accumulators 2A, 2B, 2C, 2D corresponds to the section variable accumulator 2 shown in FIG. 1, and control signals similar to the various control signals shown in FIG. Although input to the means 2A, 2B, 2C, and 2D, these control signals are shown by one signal line here for simplification.

The arithmetic circuits 8 and 9 have y (t) and
t, t are input, and y (t) is input to each of the multiplication circuits 8 and 9.
・ T, t² Are calculated and time-series signals A are calculated respectively.₁ 
(T), A ₂ It is output as (t). Also, y (t),
t is the time series signal A₁ (T), A₂ With (t)
To adjust the timing, the delay circuits 10 and 11 respectively
The time-series signal A is input and delayed by a predetermined amount.₃ 
(T), A_Four It is output as (t). Each of these time series
Column signal A₁ (T), A₂ (T), A₃ (T), A_Four 
(T) is the section variable accumulating means 2A, 2B, 2 respectively.
C and 2D are input to these section variable accumulating means 2A,
2B, 2C, 2D performance to obtain the section average value
Calculation is performed, and these section variable accumulating means 2A, 2B, 2
Cumulative signal X from C and 2D respectively₁ (T), X₂ 
(T), X₃ (T), X_Four It is output as (t). This
These signals X₁ (T), X₂ (T), X₃ (T), X_Four 
(T) is input to the arithmetic circuit 12, and in the arithmetic circuit 12,
Input cumulative signal X₁ (T), X₂ (T), X ₃ 
(T), X_Four Based on (t), the relation of the above-mentioned equation (2)
Number a₁ The signal F (t) representing This signal F
(T) is input to the memory 13. The memory 13 is shown in FIG.
It has the same function as the FIFO3 shown in
The timing of the generated signal F (t) is adjusted.
The coefficient a of equation (2) for which the timing adjustment has been performed₁ Represents
The signal G (t) is output.

Here, the case where the time-series signal y (t) is regressed to the first-order straight line shown in the above equation (1) is described as an example, but the input time-series signal is changed to an arbitrary n. The following function f (t) = a _n t ⁿ + a _n-1 + ... + a ₁ t + a ₀ is regressed, and each coefficient a _n , a _n-1 ... Of this function f (t) is regressed.
..., it is of course possible to apply the present invention is also applicable to the case of obtaining the a _1, a _0.

Further, the section change accumulating means 2A, 2B, 2C and 2D in the above embodiment have been described as having the same structure as the section variable accumulating means 2 shown in FIG.
It goes without saying that the section variable accumulating means 5 shown in FIG. 5 may be provided in plural.

[0037]

As described above, in the section variable data processing device of the present invention, the signals in the time section of the time series signal A (t) in which the analysis is permitted are sequentially input to the delay means and delayed. The signal B (t) is obtained, and the difference calculation means obtains an effective difference signal C (t) every time the signals of the time series signal A (t) within the time period during which analysis is allowed are sequentially input, Since the difference signal C (t) is accumulated to obtain the accumulated signal D (t), or because a plurality of configurations are provided, the interval average value (cumulative value) of the time-series signal, or this interval average It is possible to obtain an operation using values such as a regression coefficient without using a large capacity memory,
Therefore, it is possible to realize the pressure variable data processing device which is reduced in size and cost. Further, in the section variable data processing device of the present invention, the calculation can be performed while inputting the time-series signal, so that the calculation result can be obtained earlier than the conventional one.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of a first section variable data processing device of the present invention.

FIG. 2 is a timing chart (No. 1) showing the operation of the circuit shown in FIG.

FIG. 3 is a timing chart (No. 2) showing the operation of the circuit shown in FIG.

FIG. 4 is a timing chart (No. 3) showing the operation of the circuit shown in FIG.

FIG. 5 is a circuit block diagram showing another embodiment of the first section variable data processing device of the present invention.

FIG. 6 is a circuit block diagram showing an embodiment of a second section variable data processing device of the present invention.

FIG. 7 is a diagram showing an example of a time series signal y (t) and an analysis permission signal w (t) corresponding to the time series signal y (t).

FIG. 8 is a block diagram of a section variable data processing device for obtaining an analysis permission signal w (t) based on a reception signal (echo signal) of an ultrasonic wave.

FIG. 9 is a block diagram showing an example of data processing using a time series signal y (t) and an analysis permission signal w (t).

[Explanation of symbols]

 1, 4, 7 control circuit 2, 2A, 2B, 2C, 2D, 5 interval variable accumulating means 3, 6 FIFO 12 arithmetic circuit 21, 51 shift register 22, 52 adder circuit 23, 53 accumulating circuit

Claims (5)

[Claims] 1. A time series signal A (t) including a time section in which analysis is prohibited, and prohibition of analysis of the time series signal A (t),
Using a time-series analysis permission signal W (t) representing permission,
Different time intervals are sequentially set so that the time interval during which analysis of the time series signal A (t) is permitted maintains a predetermined length, and the time series signal A (t) within the time interval is processed. In the section variable data processing device, the time series signal A (t) within a time section for which analysis is allowed
Delay signals B (t) by sequentially inputting and delaying
A delay means for obtaining the time series signal A (t) in the time period allowed for analysis, and the delay signal B delayed from the time series signal A (t) by a time corresponding to the predetermined length.
(T) is input and the difference signal C (t) is calculated by calculating the difference between these time-series signals A (t) and delayed signals B (t).
A section variable data processing device comprising: a difference calculating means for obtaining the difference signal C (t) and an accumulation means for obtaining the accumulated signal D (t) by accumulating the difference signal C (t). 2. A time-series signal y (t) including a time section in which analysis is prohibited, and a time-series analysis permission signal W (t) indicating prohibition or permission of analysis of the time-series signal y (t). By using, to set different time intervals sequentially so that the time interval in which the analysis of the time-series signal y (t) is permitted maintains a predetermined length,
In a section variable data processing device for processing the time series signal y (t) in the time section, the time series signal y (t), a time signal t synchronized with the time series signal y (t), or When the signal obtained by calculating the time series signal y (t) and / or the time signal t is Ai (t) (i = 1, 2, ..., N), analysis is allowed. A plurality of delay means for obtaining each delayed signal Bi (t) by inputting and delaying each of the signals Ai (t) in the time section, and each of the signals Ai (t) in the time section in which analysis is allowed
And the respective delay signals Bi (t) delayed by a time corresponding to the predetermined length from the respective signals Ai (t), and the respective signals Ai (t) and the delay signals Bi (t). A plurality of difference calculating means for calculating each difference signal Ci (t) by calculating the difference between, and a plurality of accumulating means for calculating each accumulated signal Xi (t) by accumulating each difference signal Ci (t), And the plurality of accumulated signals X obtained by the plurality of accumulating means
A section variable data processing device comprising a calculation means for calculating a calculation signal F (t) by inputting i (t) (i = 1, 2, ..., N) and performing calculation. 3. The section variable data processing device according to claim 2, wherein the calculation signal F (t) is a signal representing a regression coefficient. 4. The expansion / contraction means for expanding / contracting the time axis of the cumulative signal D (t) or the arithmetic processing signal F (t) is provided. The section variable data processing device described. 5. The section variable data processing device according to claim 4, wherein said expansion / contraction means is a FIFO memory or a memory for inputting an address from the outside.