JPH05250884A - Nonvolatile storage device - Google Patents

Abstract

PURPOSE:To process a device at high speed at the time of writing data. CONSTITUTION:A memory part 16 is constituted of a frash EEPROM and when data is written in the memory part 16, after the data is retreated to a buffer part 17, the data of the memory 16 is erased. At this time, since the buffer part 17 is constituted of a memory reading/writing by a prescribed unit amount e.g. by 1 byte, erasure processing at the time of writing the data in the buffer part 17 is facilitated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device using FEEPROM (flash / EEPROM).

[0002]

2. Description of the Related Art A semiconductor disk device is a device that can be accessed at high speed because it can be controlled in the same way as a disk as viewed from the host and has no mechanical operation part. Conventionally, such a semiconductor disk device has been composed of a volatile memory chip and a battery for backing it up. However, since such a configuration is not completely non-volatile, the content of data cannot be guaranteed when the power is turned off for a long period of time.

However, in recent years, a flash EEPROM (hereinafter referred to as FEEPROM) has been used as a nonvolatile memory chip.
Has been put to practical use, and non-volatile semiconductor disk devices using this chip have been actively developed. This FEEPROM is a type of EEPROM (electrically erasable and rewritable read-only memory), which can be electrically erased, can be program-written byte by byte, does not require a power supply, and has memory contents. It has the feature that it can be guaranteed.

On the other hand, contrary to the above advantages, it has the following disadvantages. (1) Since overwriting cannot be performed when writing, it is necessary to erase (write once) (write data) byte by byte. The unit to be erased here differs depending on the chip, but the mainstream is to erase on a chip-by-chip basis. (2) There is a limit due to the number of rewrites. If this limit is exceeded, writing to the chip becomes impossible.

Next, a conventional nonvolatile memory device using FEEPROM will be described. FIG. 2 is a block diagram of a non-volatile semiconductor disk device as a conventional non-volatile memory device. In FIG. 2, reference numeral 1 is a non-volatile memory device (non-volatile semiconductor disk device), and 2 is a system bus for connecting the non-volatile memory device 1 to a host (not shown). The non-volatile storage device 1 includes a host interface unit 3, a processor unit 4, a processor memory unit 5,
It is composed of a memory unit 6, a buffer unit 7, and an internal bus 8.

The host interface section 3 is a section for performing interface control with the host, and the processor section 4
Is a part that interprets a command from the host and controls the non-volatile storage device 1 to appear as a disk device. The processor memory unit 5 is a unit that controls the operation of the processor unit 4. The memory unit 6 and the buffer unit 7 are composed of FEEPROMs, the memory unit 6 stores directories and data, and the buffer unit 7 includes the memory unit 6
On the other hand, this is a memory for temporarily saving the contents of the memory unit 6 before erasing the memory unit 6 when overwriting data. The internal bus 8 is a bus for connecting the constituent elements in the nonvolatile memory device 1.

FIG. 3 is a diagram showing details of the memory unit 6 and the buffer unit 7. That is, in this example, the memory unit 6 is divided into m blocks in the erase unit, and the capacity of one block is used as the capacity of the buffer unit 7. FIG. 4 shows details of the memory unit 6. The memory unit 6 of the non-volatile storage device 1 is made up of a directory area 6a and a data area 6b in the same manner as the disk device so that the host device looks like the disk device. Generally, the ratio of the directory area to the total capacity of the memory unit 6 is about 3 to 5%.

Next, the operation of the nonvolatile memory device will be described. 5, 6 and 7 are flowcharts for explaining the operation. [Read Operation] FIG. 5 is a flowchart of the read operation, which will be described below. First, when a host (not shown) requests a read operation, a read command, the number of read data,
The head address is issued via the system bus 2. As a result, the host interface unit 3 sets the read command, the number of read data, and the start address in a command register, a data number register, and a start address register (not shown) in the host interface unit 3, and interrupts the processor unit 4. increase.

Upon receiving this interrupt, the processor unit 4 reads the command register (step S10).
1) Recognize that the host has issued a read command. Next, the processor unit 4 reads the data number register and the head address register (step S102), and recognizes the area to be read from the memory unit 6. Next, the processor unit 4 reads one word of data from a predetermined area in the memory unit 6 (step S103), and transfers the read data to the host. Therefore, an interrupt is issued to the host via the host interface unit 3. (Step S10
4). When the host accepts this interrupt, it reads 1-word data (step S105). When the required number of data has been transferred to the host (step S106),
Since the processor unit 4 notifies the host of the end,
An interrupt is made to the host interface unit 3 (step S107).

[Write Operation] FIGS. 6 and 7 are flowcharts of the write operation. Also in this case, when a host (not shown) requests a write operation as in the above read operation, the write command, the number of write data, and the start address are issued to the nonvolatile memory device 1. As with the read operation, the host interface section 3 writes these write commands to a command register, a data number register, and a head address register (not shown) in the host interface section 3.
The number of write data and the start address are set, and the processor unit 4 is interrupted. When accepting the interrupt, the processor unit 4 reads the command register (step S
201), recognizing that the host has issued a write command. Next, the processor unit 4 reads the data number register and the head address register (step S202),
Knowing the area to be written in the memory section 6, it is determined whether or not the area in the memory section 6 can be overwritten (step S
203).

If it is impossible to overwrite the memory unit 6 in step S203, it is further determined whether or not the buffer unit 7 can be overwritten (step S204). If the buffer unit 7 can be overwritten, nothing is done, and the process proceeds to step S206. If not, the data in the buffer unit 7 is erased (step S205). Then, the process proceeds to step S206 to transfer the data for one block including the area in the memory unit 6 that needs to be overwritten,
The data is stored in the buffer unit 7. However, once all the data has been transferred, overwrite processing cannot be performed in step S210, which will be described later. Therefore, data transfer is not performed in the area to be written in step S210 based on the start address and the number-of-data information. Absent. After that, one block of data including an area in the memory unit 6 that needs to be overwritten is erased (step S207), and an interrupt is issued to the host via the host interface unit 3 to request the data (step S208). ).

When the host receives the above interrupt,
Data of one word is written (step S209).
Then, the processor unit 4 writes the data sent from the host in a predetermined area in the buffer unit 7 in accordance with the area to be written in the memory unit 6 (step S21).
0). When the write processing for the required number of data is completed from the host (step S211), the processor unit 4 notifies the host of the end, so an interrupt is raised via the host interface unit 3 (step S212). Is transferred and stored in the corresponding block in the memory unit 6 (step S213).

If it is possible to overwrite the memory unit 6 in step S203, the process proceeds to the step shown in FIG. 7, and the processor unit 4 raises an interrupt to the host via the host interface unit 3 to request data. When the write processing of the host is completed (step S214) (step S215), the processor unit 4 writes the data sent from the host directly into the memory unit 6 without passing through the buffer unit 7 (step S216). When the required number of data is written in the memory unit 6 (step S217), the processor unit 4 makes an interrupt to notify the host of the end via the host interface unit 3 (step S21).
8).

Next, the operation when the application program uses the non-volatile storage device 1 via the file system of a general operation system will be described. 8 and 9 are sequence charts for explaining the operation when a file read / write request is made.
FIG. 8 shows an operation when a read request is made, and FIG. 9 shows an operation when a write request is made.

[Read Operation] When the application program reads the data in the non-volatile storage device 1 to the file system, the file system stores the data (the memory section 6) before reading the data. It is necessary to recognize the predetermined location in the), attribute information of the data (access right, etc.), and the like. Generally, storage location information, attribute information, etc. are stored in the directory area 6 in the memory unit 6.
Since it is stored in a, the storage information and the attribute information stored in the directory area 6a are first read, and then the predetermined data is read from the data area 6b.

That is, when the application program makes a read request for the A file to the file system (step), the file system makes a read request for the A file directory to the nonvolatile storage device 1 (step). .. In response to this request, the non-volatile storage device 1 transfers the data in the A file directory (step). Next, the file system makes a read request for the A file to the non-volatile storage device 1 (step), and the non-volatile storage device 1 transfers the data of the A file to the file system (step). As a result, the file system transfers the data of the A file to the application program (step). Incidentally, the read processing C, D of the nonvolatile memory device 1
Is performed according to the read operation of the nonvolatile memory device 1 described above.

[Write Operation] When the application program writes data in the non-volatile storage device 1 via the file system, the data storage location, attribute information, etc. are written in the directory area before writing the data.
Next, data is written in a predetermined area. Since the directory area is in the memory unit 6, if the overwriting process cannot be performed and the overwriting is necessary, the contents of the directory region are temporarily saved in the buffer unit 7 and erased as in the process of overwriting the data area. Need to overwrite from.

That is, when the application program makes a B file write request to the file system (step), the file system makes a B file directory write request to the nonvolatile storage device 1 (step). Then, the data in the B file directory is transferred (step). Next, the file system makes a write request for the B file to the non-volatile storage device 1 (step), and when the data of the B file is transferred from the application program to the file system (step), the file system writes the B file The data is transferred to the non-volatile storage device 1 (step). The write processes E and F of the nonvolatile memory device 1 are performed according to the write operation of the nonvolatile memory device 1 described above.

[0019]

However, the non-volatile memory device configured as described above has the following problems. When overwriting the memory unit 6, once the memory unit 6 is overwritten.
Is transferred to the buffer unit 7 and the memory unit 6 is erased. Here, when data is transferred to the buffer unit 7, if the data has already been written in the buffer unit 7, the buffer unit 7 must be erased at all times, so that the performance of the device deteriorates.

When the application program writes data in the non-volatile memory device 1 via the file system, before writing the data, the data storage location,
It is necessary to write the attribute information and the like in the directory area 6a. Since the directory area 6a uses a part of the memory unit 6, the directory area 6a is also configured by the FEEPROM. When the FEEPROM is overwritten, it is necessary to erase it as described above. Therefore, if the writing to the directory area 6a is concentrated, the data transfer processing and the erasing processing from the memory unit 6 to the buffer unit 7 increase, and the performance of the device is improved. It will fall.

When a write request from the host needs to be overwritten, before the memory section 6 is erased, regardless of the contents of the data stored in the buffer section 7, it is always saved (transferred) to the buffer section 7. However, if the data to be saved and the data stored in the buffer unit 7 are the same, there is a problem that unnecessary processing is performed. .

In the conventional nonvolatile memory device, since the number of times of rewriting is not monitored, there is a fear that writing cannot be performed without any warning. The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a non-volatile memory device capable of improving performance such as speeding up of write processing.

[0023]

A nonvolatile memory device according to a first invention of the present invention comprises a flash EEPROM, a memory section for storing data, and a memory capable of reading / writing in a predetermined unit amount. And a buffer unit for saving the data when the data in the memory unit is erased.

The non-volatile memory device of the second invention comprises a flash EEPROM, a memory section for storing data, and a non-volatile memory capable of reading / writing by a predetermined unit amount. And a directory section for storing the data storage information of.

A nonvolatile memory device according to a third aspect of the present invention comprises a flash EEPROM, a memory section for storing data, a buffer section for saving the data in the memory section when the data is erased, and the memory. Transfer unit for transferring data from the memory unit to the buffer unit, it is determined whether the data stored in the memory unit and the data stored in the buffer unit match, and if they match, the transfer control unit controls not to perform the transfer. It is characterized by having and.

A non-volatile memory device according to a fourth aspect of the present invention comprises a flash EEPROM, and includes a memory section for storing data and a rewriting frequency recognizing section for recognizing the number of times data is rewritten to the memory section. It is what

[0027]

In the non-volatile memory device of the present invention, the memory section is composed of a flash EEPROM, and when writing data to this memory section, the data is saved in the buffer section before the data is erased. Here, since the buffer unit is composed of a memory that can read / write in a predetermined unit amount, for example, in units of 1 byte, erasing processing when writing data in the buffer unit is not necessary. Therefore,
The processing for writing data becomes faster.

[0028]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the nonvolatile memory device of the present invention. In FIG. 1, 11
Is a non-volatile storage device (non-volatile semiconductor disk device),
Reference numeral 2 is a system bus for connecting the nonvolatile memory device 11 to a host (not shown). The non-volatile storage device 11 includes a host interface unit 13 and a processor unit 1.
4, a processor memory unit 15, a memory unit 16, a buffer unit 17, and an internal bus 18.

Here, the host interface unit 13 is
This is a part for performing interface control with the host as in the conventional case, and the processor part 14 is a part for interpreting a command from the host and controlling the non-volatile storage device 11 to appear as a disk device. The processor memory unit 15 is a unit that controls the operation of the processor unit 14. The memory unit 16 is composed of an FEEPROM and stores a directory and data as in the conventional case. The buffer unit 17 has a function of temporarily saving the contents of the memory unit 16 before erasing the memory unit 16 when overwriting data in the memory unit 16. , RAM and other volatile memory chips. The internal bus 18 is a bus for connecting the constituent elements in the non-volatile memory device 11, as in the conventional case.

Next, the operation of the nonvolatile memory device will be described. [Read Operation] Here, the read operation of this embodiment is the same as the conventional operation flow. That is, since the operation is similar to that of the flowchart shown in FIG. 5, description thereof is omitted here.

[Write Operation] FIG. 10 is a flowchart of the write operation. When a host (not shown) requests a write operation, the write command, the number of write data, and the start address are issued to the nonvolatile memory device 11. The host interface unit 13 has a command register (not shown) in the host interface unit 13, as in the read operation.
The write command, the write data number, and the start address are set in the data number register and the start address register, and the processor unit 14 is interrupted. Upon receiving the interrupt, the processor unit 14 reads the command register (step S301) and recognizes that the host has issued the write command. Next, the processor unit 14 reads the data number register and the head address register (step S302), knows the area to write to the memory unit 16, and determines whether or not the area in the memory unit 16 can be overwritten. Yes (step S303).

In step S303, the memory unit 16
If it is impossible to overwrite the data in the buffer section, it is conventionally necessary to check whether or not it is possible to overwrite the data in the buffer section, and if this is not possible, it is necessary to erase the data in the buffer section. The data for one block including the area that needs to be overwritten in the memory unit 16 is transferred as it is and stored in the buffer unit 17 (step S304). After that, one block of data in the memory unit 16 including the area that needs to be overwritten is erased (step S305), and an interrupt is issued to the host via the host interface unit 13 to request the data (step S306). ..

When the host receives the above interrupt,
Data of one word is written (step S307).
Then, the processor unit 14 writes the data sent from the host in a predetermined area in the buffer unit 17 in accordance with the area to be written in the memory unit 16 (step S
308). When the write processing for the required number of data from the host is completed (step S309), the processor unit 14
Transfers the content of the buffer unit 17 and stores it in the corresponding block in the memory unit 16 (step S310). Then, in order to notify the host of the end, an interrupt is raised via the host interface unit 13 (step S3
11). In this way, the write operation end notification to the host is performed after writing the data in the memory unit 16, and thus the non-volatility as the non-volatile storage device can be maintained.

If it is possible to overwrite the memory portion 16 in step S303, the process proceeds to the same step as shown in FIG. 7 as in the conventional case.
The description is omitted.

In the first embodiment, the buffer unit 1
Although 7 is composed of a volatile memory, a memory that can be read / written in a predetermined unit amount, for example, 1 such as an EEPROM.
It may be constituted by a non-volatile memory capable of reading / writing in byte units.

Next, a second embodiment in which the directory portion is composed of a non-volatile memory capable of overwriting data will be described. FIG. 11 shows a block diagram thereof. The nonvolatile storage device 21 shown in the figure includes a host interface unit 23, a processor unit 24, a processor memory unit 25, and a memory unit 2.
6, buffer unit 27, directory unit 28, internal bus 2
It is composed of 9. Further, 2 is a system bus similar to the conventional one. Here, the operational function of each of the above components is similar to that of the first embodiment, but this embodiment is characterized in that the directory unit 28 is composed of an EEPROM.

FIG. 12 is a diagram showing the memory space of the directory unit 28 and the memory unit 26 as seen from the processor unit 24. Here, like the conventional memory space (Fig. 4),
The address A28 of the directory unit 28 and the address A26 of the memory unit 26 are configured so that the processor unit 24 can access them at consecutive addresses. The capacities of the memory unit 26 and the buffer unit 27 are the same as those of the conventional one shown in FIG.

Next, the operation of the nonvolatile memory device will be described. [Read Operation] FIG. 13 is a flowchart of the read operation, which will be described below. When a host (not shown) requests a read operation, it issues a read command, the number of read data, and a start address to the nonvolatile memory device 21 via the system bus 2. As a result, the host interface unit 23 sets the read command, the number of read data, and the start address in the command register, data number register, and start address register (not shown) in the host interface unit 23, and interrupts the processor unit 24. increase.

When the processor section 24 receives this interrupt, it reads the command register (step S40).
1) Recognize that the host has issued a read command. Next, the processor unit 24 reads the data number register and the head address register (step S402) and recognizes whether the directory is requested or the data is requested (step S403). When the host requests the directory in step S403, the processor unit 24 reads one word of data from a predetermined area in the directory unit 28 (step S404), and transfers the read data to the host. An interrupt is sent to the host via the interface unit 23 (step S405). When the host accepts this interrupt, it reads 1-word data (step S40).
6). When the required number of data has been transferred to the host (step S407), the processor unit 24 notifies the host of the end, and therefore an interrupt is issued to the host interface unit 2
3 is performed (step S408).

The operation when the host requests data in step S403 is the same as the operation from step S103 in FIG. 5, and therefore the description thereof is omitted here.

[Write Operation] FIG. 14 is a flowchart of the write operation. Also in this case, when a host (not shown) requests a write operation as in the above read operation, the write command, the number of write data, and the start address are issued to the nonvolatile memory device 21. As with the read operation, the host interface unit 23 writes these write commands to the command register, data count register, and start address register (not shown) in the host interface unit 23.
The number of write data and the start address are set, and the processor 24 is interrupted. Upon receiving the interrupt, the processor unit 24 reads the command register (step S501) and recognizes that the host has issued the write command. Next, the processor unit 24 reads the data number register and the head address register (step S50).
2) Recognize whether a directory write request or a data write request is requested (step S5)
03).

When the host requests writing of the directory, the processor unit 24 raises an interrupt to the host via the host interface unit 23 and writes the directory information (step S504). Upon accepting the above interrupt, the host writes 1-word directory information (step S505). Then, the processor unit 24 writes the directory sent from the host in a predetermined area in the directory unit 28 (step S506). When the write processing for the required number of data from the host is completed (step S507), the processor unit 24
Notifies the host of the end, and raises an interrupt via the host interface unit 23 (step S50).
8).

When the host requests writing to the data section in step S503, the operation is the same as that of step S203 in FIG. 6 of the prior art.
The description here is omitted.

In the second embodiment, the application program is stored in the nonvolatile storage device 21 via the file system of a general operation system.
When using, the sequence chart of the operation is similar to that of the conventional FIG. 8 and FIG. However, in this embodiment, since the directory unit 28 is composed of the EEPROM, rewriting can be performed in 1-byte units, and when the write area is the directory unit 28, the data is temporarily saved in the buffer unit 27. There is no need, and the storage location of data in the data section, attribute information, etc. can be written in the directory section 28 as they are.

In the second embodiment described above, the directory section 28 is composed of the EEPROM, but it is possible to read / write in a predetermined unit amount, for example, in a unit of 1 byte even in the case of a non-volatile memory other than this. The same effect can be obtained as long as it is one.

Next, a third embodiment provided with a storage address section will be described. FIG. 15 shows a block diagram thereof. The non-volatile storage device 31 shown in the figure includes a host interface unit 33, a processor unit 34, a processor memory unit 35, a memory unit 36, a buffer unit 37, a storage address unit 38, and an internal bus 39. Further, 2 is a system bus similar to the conventional one.

The storage address section 38 is a memory for holding information on which block of the memory section 36 the data stored in the buffer section 37 is, and is composed of a non-volatile memory. In addition, the processor unit 34
Includes a transfer control means 34a. When transferring data from the memory section 36 to the buffer section 37, the transfer control means 34a compares the addresses stored in the storage address section 38, and if they match. Has a function of controlling so as not to transfer (save) to the buffer unit 37. The rest of the configuration is the same as that of the first and second embodiments, and the description thereof is omitted here.

Next, the operation of the non-volatile memory device of the third embodiment will be described. [Read Operation] Here, the read operation of this embodiment is the same as the conventional operation flow. That is, since the operation is similar to that of the flowchart shown in FIG. 5, description thereof is omitted here.

[Write Operation] FIG. 16 is a flowchart of the write operation. When a host (not shown) requests a write operation, the write command, the number of write data, and the start address are issued to the nonvolatile storage device 31. As with the read operation, the host interface unit 33 uses a command register (not shown) in the host interface unit 33,
The write command, the write data number, and the start address are set in the data number register and the start address register, and the processor unit 34 is interrupted. Upon accepting the interrupt, the processor unit 34 reads the command register (step S601) and recognizes that the host has issued the write command. Next, the processor unit 34 reads the data number register and the head address register (step S602), knows the area to write to the memory unit 36, and determines whether or not the area in the memory unit 36 can be overwritten. Yes (step S603).

In step S603, the memory unit 36
If the overwriting is impossible, the processor unit 34
The storage address portion 38 is read (step S604),
It is determined whether or not one block of data including an area in the memory section 36 that needs to be overwritten is present in the buffer section 37 (step S605). That is, this determination is made by comparing the start address of one block including the area that needs to be overwritten with the address stored in the storage address. If this matches, the buffer unit 3
If there is corresponding data in 7 and there is a mismatch, the buffer unit 37
It is judged that there is no corresponding data in.

In step S605, the buffer unit 3
If there is corresponding data in No. 7, the data is not transferred to the buffer unit 37, the process proceeds to the interrupt processing to the host in step S611 described later, and if there is no corresponding data in the buffer unit 37, the buffer unit 37 is overwritten. (Step S606). If the buffer unit 37 can be overwritten, nothing is done, and the process proceeds to step S608. If not, the data in the buffer unit 37 is erased (step S607). Then, the process proceeds to step S 608, and the data of one block including the area in the memory unit 36 that needs to be overwritten is transferred and stored in the buffer unit 37. However, if all the data has been transferred, overwrite processing cannot be performed in step S613, which will be described later. Therefore, data transfer is not performed for the area to be written in step S613 based on the start address and the number-of-data information. I don't know. Further, the head address of the transferred block is stored in the storage address section 38 (step S609). afterwards,
One block of data including an area that needs to be overwritten in the memory unit 36 is erased (step S610), and
An interrupt is sent to the host via the host interface unit 33 to request data (step S611).

When the host accepts the above interrupt,
Data of one word is written (step S612).
Then, the processor unit 34 writes the data sent from the host in a predetermined area in the buffer unit 37 in accordance with the area to be written in the memory unit 36 (step S
613). When the write process for the required number of data is completed from the host (step S614), the processor unit 34 notifies the host of the end, so an interrupt is generated via the host interface unit 33 (step S61).
5) The contents of the buffer unit 37 are transferred and stored in the corresponding block in the memory unit 36 (step S616).

Further, in step S603, when the memory section 36 can be overwritten, the operation is the same as the conventional operation shown in FIG. 7, and therefore the description thereof is omitted here.

In the third embodiment, the storage address section 38 is composed of a non-volatile memory. However, when the data is transferred from the memory section 36 to the buffer section 37, the above address can be checked. With the configuration, for example, a volatile memory can be used.

Next, a fourth embodiment provided with a rewriting frequency recognizing section will be described. FIG. 17 shows its block diagram. The nonvolatile storage device 41 shown in the figure includes a host interface unit 43, a processor unit 44, a processor memory unit 45,
Memory unit 46, buffer unit 47, rewrite frequency recognition unit 4
8 and an internal bus 49. Further, 2 is a system bus similar to the conventional one. Rewriting frequency recognition unit 48
Is a memory for storing the number of times of rewriting of the memory section 46, and is composed of an EEPROM. Further, the other structure is similar to that of the third embodiment, and therefore the description thereof is omitted here.

Next, the operation of the nonvolatile memory device according to the fourth embodiment will be described. [Read Operation] Here, the read operation of this embodiment is the same as the conventional operation flow. That is, since the operation is similar to that of the flowchart shown in FIG. 5, description thereof is omitted here.

[Write Operation] FIG. 18 is a flowchart of the write operation. When a host (not shown) requests a write operation, the write command, the number of write data, and the start address are issued to the nonvolatile storage device 41. As with the read operation, the host interface unit 43 uses a command register (not shown) in the host interface unit 43,
The write command, the number of write data, and the start address are set in the data count register and the start address register, and the processor 44 is interrupted. Upon receiving the interrupt, the processor unit 44 reads the command register (step S701) and recognizes that the host has issued the write command. Next, the processor unit 4 reads the data number register and the head address register (step S702), knows the area to be written to the memory unit 46, and determines whether or not the area in the memory unit 46 can be overwritten. Yes (step S703).

In step S703, the memory unit 46
If it is not possible to overwrite the buffer section 47, it is further determined whether or not the buffer section 47 can be overwritten (step S70).
4). If the buffer unit 47 can be overwritten, nothing is done, and the process proceeds to step S706. If not, the data in the buffer unit 47 is erased (step S7).
05). Then, in step S706, the memory unit 4
Data for one block including an area in 6 that needs to be overwritten is transferred and stored in the buffer unit 47. However, if all the data has been transferred, overwrite processing cannot be performed in step S711, which will be described later. Therefore, data transfer is not performed in the area to be written in step S711 based on the start address and the number-of-data information. Absent. After that, one block of data including an area that needs to be overwritten in the memory unit 46 is erased (step S707), and the corresponding word of the rewrite number recognition unit 48 is updated (step S7).
08). Furthermore, an interrupt is sent to the host via the host interface unit 43 to request data (step S7).
09).

When the host receives the above interrupt,
Data of one word is written (step S710).
Then, the processor unit 44 writes the data sent from the host in a predetermined area in the buffer unit 47 in accordance with the area to be written in the memory unit 46 (step S
711). When the write process for the required number of data is completed from the host (step S712), the processor unit 44 notifies the host of the end, so an interrupt is raised via the host interface unit 43 (step S71).
3) The contents of the buffer unit 47 are transferred and stored in the corresponding block in the memory unit 46 (step S714).

If it is possible to overwrite the memory portion 6 in step S703, the operation is the same as the conventional operation shown in FIG.

In the fourth embodiment, the rewriting frequency recognizing unit 48 is composed of a non-volatile memory such as an EEPROM, but in this case also, for example, when the power is off, the rewriting frequency data is stored in another non-volatile memory. It is also possible to use a volatile memory by using a configuration for storing.

[0062]

As described above, according to the non-volatile memory device of the first aspect of the invention, since the buffer portion is composed of the memory capable of reading / writing in a predetermined unit amount, data is written in the buffer portion. In this case, the data erasing process is unnecessary, the data writing can be speeded up, and the performance of the device can be improved.

Further, according to the non-volatile memory device of the second aspect of the invention, since the directory portion is constituted by the non-volatile memory capable of reading / writing in a predetermined unit amount, the erasing process of the directory portion and the data Transfer processing becomes unnecessary, and high-speed processing becomes possible.

According to the nonvolatile memory device of the third invention,
When data is transferred from the memory unit to the buffer unit, it is determined whether the data stored in the memory unit and the data stored in the buffer unit match, and if they match, the transfer is not performed. When data to be saved is stored in the buffer unit at the time of a write request to the device, transfer from the memory unit to the buffer unit is not necessary, and the speed of data writing processing can be increased.

According to the nonvolatile memory device of the fourth invention,
Since the number of times of rewriting of the memory unit is monitored, the number of times of rewriting can be managed, and problems such as unintentional unwriting can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of a nonvolatile memory device according to the present invention.

FIG. 2 is a block diagram of a conventional nonvolatile memory device.

FIG. 3 is a diagram showing a relationship between capacities of a memory unit and a buffer unit.

FIG. 4 is an explanatory diagram of an internal configuration of a conventional memory unit.

FIG. 5 is an operation flowchart at the time of reading in the conventional nonvolatile memory device.

FIG. 6 is an operation flowchart at the time of writing in the conventional nonvolatile memory device.

FIG. 7 is a flow chart in a case where overwriting is possible in the memory unit at the time of writing in the conventional nonvolatile storage device.

FIG. 8 is an operation flowchart when reading a file in the conventional nonvolatile storage device.

FIG. 9 is an operation flowchart at the time of writing a file in the conventional nonvolatile storage device.

FIG. 10 is a write operation flowchart of the first embodiment of the nonvolatile memory device of the present invention.

FIG. 11 is a block diagram of a second embodiment of the nonvolatile memory device of the present invention.

FIG. 12 is an explanatory diagram of a memory space of a second embodiment in the nonvolatile memory device of the present invention.

FIG. 13 is a flowchart at the time of reading in the second embodiment of the nonvolatile memory device of the present invention.

FIG. 14 is a flowchart at the time of writing in the second embodiment of the nonvolatile memory device of the present invention.

FIG. 15 is a block diagram of a third embodiment of the nonvolatile memory device of the present invention.

FIG. 16 is a flowchart at the time of writing in the third embodiment of the nonvolatile memory device of the present invention.

FIG. 17 is a block diagram of a fourth embodiment of the nonvolatile memory device of the present invention.

FIG. 18 is a flowchart at the time of writing in the fourth embodiment of the nonvolatile memory device of the present invention.

[Explanation of symbols]

 11, 21, 31, 41 Non-volatile storage device 14, 24, 34, 44 Processor unit 16, 26, 36, 46 Memory unit 17, 37 Buffer unit 28 Directory unit 34a Transfer control means 38 Directory unit 48 Rewriting number recognition unit

Claims (4)

[Claims] 1. A flash EEPROM, comprising a memory section for storing data and a memory capable of reading / writing in a predetermined unit amount, and saving the data when erasing the data in the memory section. A non-volatile storage device comprising: 2. A directory section configured by a flash EEPROM, which stores data, and a non-volatile memory capable of reading / writing in a predetermined unit amount, and storing data storage information in the memory section. A non-volatile memory device comprising: 3. A memory section configured by a flash EEPROM for storing data, a buffer section for saving the data in the memory section when the data is erased, and a data transfer from the memory section to the buffer section In this case, it is provided with a transfer control unit that determines whether the data stored in the memory unit and the data stored in the buffer unit match, and if they match, controls not to perform the transfer. Non-volatile storage device. 4. A non-volatile storage device comprising a flash EEPROM and a memory section for storing data, and a rewrite number recognition section for recognizing the number of times data is rewritten into the memory section.