JPH05250344A - Monitor and control system - Google Patents

Abstract

PURPOSE:To provide the monitor and control system when respective modules are concentrically monitored and controlled as to a monitor and control system for a system which has plural modules. CONSTITUTION:The function modules and a device monitor and control part which performs centralized monitoring and control operation are connected through a doubled control bus and when the device monitor and control part 1 and respective function modules send and receive commands and responses to perform control so as to consider a correct command or response to be normal, the high-order function module 21 to which the low-order function module 22 is cascaded hierarchically functions as a subordinate control part to improve the efficiency of the control bus; and the device monitor and control part 1 multiplexes and sends out commands to shorten the monitor and control time, the serial control bus is converted into a parallel bus and connected to the low-order modules to decrease the device scale, and the control bus is constituted into two systems of different paths including logical control buses in a target data bus to improve the reliability.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a supervisory control method in a system having a plurality of modules, packages, etc. (hereinafter simply referred to as modules), and particularly to controlling and initializing each module and communicating with each module. The present invention relates to a supervisory control method in a system having a centralized supervisory control unit for exchanging information about its operation, operating state, and the like.

In recent years, in various devices such as a packet switching device, the number of modules in the device tends to increase in order to realize sophisticated and complicated functions by one device. Also, as the sophistication _and miniaturization of the functions of individual constituent factors such as various modules increase the number of obstacle factors, the interface of various information with the device monitoring unit such as initial settings is increasing. The wiring path of the control bus from the control unit to each module is arranged in a complicated manner in the device.

As described above, in the centralized monitoring and control system in a device having a large number of modules, reliability is improved by connecting a device monitoring control unit for centralized monitoring and control and each module with a dual serial interface. At the same time, it is desired to reduce the number of signal lines so that the device scale can be reduced.

[0004]

2. Description of the Related Art Conventionally, a plurality of such modules,
As a supervisory control method with the device supervisory control unit that performs control and initial setting for each module and exchanges information about the operating state and operating state with each module, one between them There is a system that has only a single bus and is used for both sending and receiving information and sending and receiving error countermeasure information.

In such a case, as a coupling method between each module and the device monitoring controller, a parallel processor bus in which an interface from a central processing unit (CPU) in the device monitoring controller is extended is used for each module. However, in such a coupling method, there is a limitation in extending the bus when the device configuration becomes large.

[0006]

As described above, in the conventional centralized supervisory control method for a plurality of modules, since it is a coupling method using only one single bus, even if one signal line is disconnected, There is a drawback that it is not possible to carry out the supervisory control work, and therefore the reliability is poor.

When the supervisory control bus is duplicated by such a coupling method, the number of signal lines is doubled. Therefore, there are problems that the number of components such as drivers and receivers increases as the number of signal lines increases, power consumption increases, and the circuit scale and cost increase cannot be avoided.

Further, in the case of a supervisory control bus in a device requiring extension of the control bus, if this is duplicated, an extension device for extending the control bus is additionally required, so that the circuit scale is expanded and the device is extended. This will cause a problem such as a decrease in reliability.

The present invention is intended to solve such a problem of the prior art, and a dual transfer mechanism is used when the device monitoring control unit performs centralized monitoring and control of a plurality of functional modules. , The transmission and reception are performed independently of each other to control the correct command or response to be normal, so that the reliability can be improved, and by serializing the bus, the circuit scale can be improved. It is an object of the present invention to provide a supervisory control system that can be reduced, and is therefore economically advantageous.

[0010]

[Means for Solving the Problems] (1) FIG. 1 shows a principle configuration of the present invention. According to the present invention, a plurality of function modules and a device monitoring control unit that performs centralized monitoring / control for the plurality of function modules are connected via a duplicated control bus, and each device is controlled according to a command from the device monitoring control unit. In the system in which the functional modules respond, the device monitoring control unit 1 and the upper functional module 2 ₁ exchange commands and responses via the upper control bus 3 ₁ , and the upper functional module 2 ₁ monitors the device monitoring and control. between the lower control module 2 ₂ based on a command part 1, via the lower control bus 3 _2, this response by performing exchange between a command registered in advance in the upper functional modules and response Is sent back to the device monitoring control unit 1.

In this case, according to the present invention, the higher-level functional module is
Jules 2₁ Stores the command from the device monitoring control unit 1.
And a subordinate functional module based on this directive.
Two₂When the response from is abnormal, this stored command
Is the lower functional module 2 ₂Between the above
It retries to send and receive recorded commands and responses.
is there.

According to the present invention, in this case, the upper functional module 2 ₁ is replaced by any _one of the lower functional modules 2 _2.
When a fatal abnormality occurs in the device, it has means for generating a flag to display it, and by adding this flag to the response to the device monitoring control unit 1 to notify it, the device monitoring control unit 1 is urgently notified. Is to interrupt.

(2) Further, according to the present invention, a plurality of functional modules and a device monitoring control unit for performing centralized monitoring / control for the plurality of functional modules are connected via a duplicated serial control bus, and device monitoring control is performed. In a system in which each functional module responds in response to a command from a unit, the device monitoring control unit 1 continuously sends commands to a plurality of functional modules in a command frame without waiting for responses, and each functional module is further downstream. Priority is given to relaying the response from the functional module, and then the response from the own module is sent out.

Further, according to the present invention, in this case, priority information is added to the command from the apparatus monitoring control unit 1 and transmitted, and each functional module monitors the control bus, so that the priority is higher. After the response of the functional module is completed, the response of its own module is made.

Further, according to the present invention, in this case, priority information is added to the command from the apparatus monitoring control unit 1 and transmitted, and each functional module monitors the control bus to determine a predetermined sequence. In addition to responding in ascending order of the numbers, the functional modules with priorities respond with the highest priority.

(3) The present invention further provides a plurality of functional modules.
And centralized monitoring and control of the multiple functional modules
Via the redundant control bus
And connect each function mode according to the command from the device monitoring control section.
In the system in which Joule responds, the device monitoring control unit
1 and higher functional module 2₁ And is from the serial bus
Upper control bus 3₁ Connected through and on
Functional module 2 ₁ Controls the upper control bus in parallel
To convert this parallel bus to a lower level.
Higher functional module 2 as a control bus₁ And lower function
Jules 2₂ And are connected.

(4) Further, according to the present invention, a plurality of function modules and a device monitoring control unit for performing centralized monitoring / control for the plurality of function modules are connected via a duplicated control bus, and a device monitoring control unit is provided. In a system in which each functional module responds in response to a command from, the redundant control bus is composed of two transfer buses having different paths.

In this case, the present invention further provides a data transfer logic control bus in which two control buses form a control bus frame which is logically identical on the serial control transfer bus and the target data transfer bus. It consists of and.

In this case, according to the present invention, the serial control transfer bus and the above-mentioned data transfer logic control bus are selectable, and the data transfer bus between the functional modules is used as a data transfer logic control bus. By providing a diverting means for diverting, a bypass data transfer logic control bus is formed between target modules via a connectable functional module when a failure occurs in the serial control transfer bus.

[0020]

According to the present invention, in a system having a large number of processing units for performing various kinds of processing such as a large-scale switching device, alarms, initial settings, notification of various status information, etc. in each processing unit can be provided. It applies when it is necessary to do so.

FIG. 2 shows an example of the overall configuration of a system to which the present invention is applied. The plurality of accommodating units 71 connect a plurality of transmission lines, terminals and the like to the switching device, perform electrical or physical level matching or perform protocol termination on the terminals and transmission lines, and take in necessary information inside the switching device. The plurality of multiplexing units 72 perform high-speed multiplexing of information from a plurality of terminals, transmission lines, etc. on an internal highway. A plurality of separating parts 73
Separates information from the internal highway into a plurality of terminals, transmission paths, and the like. The exchange processing unit 74 has a function of exchanging information from the input highway with a target transfer destination. The device monitoring control unit 75 monitors and controls each unit such as the multiplex units 72, the multiple separation units 73, and the exchange processing unit 74.

According to the present invention, an apparatus monitoring control section for centrally monitoring _and controlling a plurality of modules constituting such a monitored section is provided to perform control and initial setting for each module. It proposes a supervisory control method in the case of sequentially or irregularly notifying information about the operating state and the operating state of.

3A and 3B show examples of control bus connections in a device to which the present invention is applied. FIG. 3A shows a case of an individual bus type, and FIG. 3B shows a case of a common bus type. ing. 81 is a device control unit for controlling the whole,
, 82-n, ..., 82-i are modules or packages.

Initial setting information is given from a single device control unit 81 to each of a plurality of modules and packages, and operation information and detailed alarm information of a failure portion due to the occurrence of a failure are collected, and further recovery by the failure is performed. Make settings,
A configuration as shown in FIGS. 3A and 3B is conceivable as a configuration of the control bus for setting each unit such as a module and a package for updating the initial information accompanying the device expansion.

In FIG. 3, a plurality of modules, packages, etc. are present to perform the original functions of the apparatus, and among these modules, packages, etc.,
By exchanging necessary information with each other, some functions are realized as a system.

For example, in the case of an exchange device, the module, package, etc. may be each package of the switch part (the part realizing the space switch, the time switch), the subscriber accommodation package, or the subscription. It may be a package that collects lines from people. These processes the original information of the device by the function realized by each package for the information from the subscriber.
In cooperation with other packages (for example, transfer to a target subscriber package by a switch package), communication of original information is realized with the target subscriber. The method of the present invention is applied to such a device when notifying a single control unit of information from each module, package, etc. in order to perform centralized monitoring control of failures of each module, package, etc. It is something.

FIG. 4 shows an example of the basic configuration of the method of the present invention. Reference numeral 100 is a device monitoring control unit for performing device failure monitoring, operation management, startup processing, etc., 200, 3
Reference numeral 00 is a functional module, such as a module or a package, which is connected to the apparatus monitoring control unit 100 by a control bus 500 or the like and performs the original processing of the apparatus. Function module 200
Has a control bus relay function for temporarily terminating the control bus 500 and relaying the bus, which is hereinafter referred to as a higher-level functional module. On the other hand, the functional module 300 having no such function is called a lower functional module.
Further, the device monitoring control unit 100 and the upper functional module 2
The control bus 500 connecting 00 is called an upper control bus, and the upper functional bus 200 and the lower functional module 30 are connected.
The control bus 510 connecting 0 is called a lower control bus.

The device monitoring controller 100 includes a control bus 500.
A transmitting unit 110 and a receiving unit 120 that exchange information with each module or package by using, and provide valid information to these transmitting units and receiving units, or receive the received information and use it for operating the device. Upper control unit 130
It consists of The functional module 200 includes a transmitter 210 and a receiver 220, which are connected to the control bus 500 by a bus.
And a control unit 230 for controlling the inside of this functional module
And have. Further, the functional module 300 includes a transmission unit 310 and a reception unit 32, which are bus-connected to the control bus 510.
0, and a control unit 3 for controlling the inside of this functional module
30 and 30.

[0029] In the basic configuration shown in FIG. 4, as the type of the processing for exchanging information necessary to function module 200 from the device monitoring control unit 100, setting processing each module in the initial setting _information, the package Etc., detection of fault information and its notification processing Control bus normality confirmation processing Maintenance / monitoring information setting / notification processing, etc.

FIG. 5 shows an example of a processing procedure in the method of the present invention, (a) shows a setting processing procedure of initial setting information, and (b) shows a detection notification processing procedure of operation / fault information. ing.

The initial setting information is the device monitoring control unit 10.
This is performed by setting the initial information from 0 to the functional modules 200 and 300 until the functional modules can be brought into the operational state. The processing procedure in this case is performed according to FIG.

In the operation / fault information detection notification process, the first detection is often performed from the functional module 200 or 300. However, in the case of checking the status during operation, there is a procedure in which the device monitoring control unit 100 inquires of the functional module 200 or 300 regularly or irregularly. Therefore, the processing procedure is as shown in FIG.
It becomes like (b). Regarding the processing of control bus faults and maintenance / monitoring information, it is the same as either procedure of, except that the corresponding information is different and the activation timing of the procedure is also different.

In the system of the present invention, such monitoring and
By providing each of the above-mentioned means for performing the control process, it is possible to solve a given problem and to obtain an effect that cannot be obtained by the conventional supervisory control method.

That is, instead of extending the bus of the processor as an interface between each module and the device monitoring control unit, a control bus to which a dedicated transmission interface is applied is provided so that the bus extension accompanying the expansion of the device can be achieved. To be realized. Further, since the serial bus satisfies the throughput of the parallel bus of the processor bus, the number of drive elements of the control bus is reduced and the number of signal lines to be wired is reduced by solving the problem by increasing the clock rate of the serial bus.

Therefore, the physical distance limitation of the control interface between the component elements (module, package, etc.) of the device and the device monitoring control section can be removed, and the reliability can be improved, and the serial interface can be used. Therefore, it is possible to reduce the number of components of the driver and the receiver, which consume a large amount of power, reduce the power consumption of the entire device, and simplify the cooling mechanism of the device.
Furthermore, since the number of signal lines is small, the material cost can be reduced and the device cost can be reduced.

Further, at this time, a duplicated control bus is provided in a system composed of a device monitoring control section for performing centralized monitoring and control, and a plurality of functional modules and the like subject to centralized monitoring and control. Further, in the device monitoring control unit, various commands from the control unit that performs centralized monitoring and control processing to each functional module are transmitted to the bus through the redundant command transmission processing unit, and various functional modules receive various commands. By receiving the response from the bus via the duplicated response reception processing unit and selecting the correct one from the received information and performing the reception process, the reliability in centralized monitoring and control can be improved.

Further, in the present invention, in this case,
The control bus that connects the device monitoring control unit and the functional module is provided in a hierarchical manner, and the intermediate functional module that performs subordinate connection relays the control bus to perform the function as the sub-control unit. It is possible to reduce access frequency and improve bus efficiency. Also, in the event of an abnormality, the upper-level functional module retries the exchange of commands and responses with the lower-level functional module,
It is possible to reduce the processing load on the device monitoring control unit and improve the reliability. Furthermore, when a fatal abnormality occurs in a lower-level functional module, the upper-level functional module adds a flag indicating this to the response to the device monitoring control unit so that an emergency interruption can be made. The configuration can be simplified and the processing speed can be increased.

Further, in the present invention, the device monitoring control section continuously sends commands to a plurality of functional modules without waiting for a response from the functional modules, and
Since the functional module preferentially relays the response from the downstream functional module to sequentially respond, it is possible to shorten the waiting time for transmitting the command from the device monitoring control unit. Further, at this time, the function module responds according to the priority designated by the command, or the predetermined sequence number and the priority based on the command. Can respond flexibly according to importance.

Further, in the present invention, the device monitoring controller and the upper functional module are connected by the serial bus, and the serial bus is converted into the parallel bus in the upper functional module to connect the lower functional module. So, the conversion of serial bus and parallel bus is 1
By carrying out collectively at a location and connecting adjacent functional modules by a parallel bus, the conversion location of the serial bus and the parallel bus can be reduced and the device scale can be reduced.

Further, in the present invention, the reliability of the control bus can be improved by providing the control bus between the device monitoring control section and the functional module as two separate routes. At this time, by making one of the control buses a logical control bus provided in the data bus that achieves the original purpose of the apparatus, it is possible to make the transmission line economical. Further, by allowing the data bus between the functional modules to constitute the bypass line of the control bus, the reliability can be further improved economically.

[0041]

FIG. 6 shows an example of control bus connection logic in a specific system to which the method of the present invention is applied. In FIG. 6, SW-CTL is a control unit that performs overall connection control, SD and PD are packet transfer modules that perform packet transfer processing, and XP and A / C are packets that are modules for temporarily storing packets. It is a storage buffer.

A plurality of control buses are connected from the control section SW-CTL. A plurality of packet transfer modules (SD # 0, SD # 1,
..., SD # m) can be connected to the bus.

Further, from the packet transfer module SD,
Again by bus coupling, multiple packet storage buffers XP
Is connected to the packet transfer module PD, and the packet transfer module PD is further connected to a plurality of packet storage buffers A / C via bus coupling.

FIG. 7 shows an example of entire functional blocks in a concrete system to which the method of the present invention is applied. In FIG. 7, reference numeral 91 is a housing unit that houses terminals, transmission paths, and the like.

In FIG. 7, the solid line indicates the data bus,
The double line indicates the control bus. Also, the dotted lines indicate individual lines, and the accumulation status of the packet transfer buffers XP and C (DFL
W), ACT (ready), IRQ interrupt request line (buffer alarm), etc. to distributor (SDD, P
It is shown to collect on the DD) side.

As shown in FIG. 7, the present system realizes a packet switching device as a whole, and the individual functional modules thereof perform the original processing operations required for packet switching. The packet transfer modules PD and SD are functionally identical in function, act as an arbiter or a distributor for the bus, take out packets from the packet storage buffers A and XP on the packet transfer bus, and are the transfer destinations of the packets. It has a function of transferring to the packet storage buffers C and XP. The packet storage buffers A / C and XP have a function of temporarily storing packets.

In FIG. 7, the accommodating section 91 has packet accumulation buffers A and C, and takes in terminal data from the outside and data input from the transmission path. The packet storage buffer A temporarily stores packets for waiting in order to packetize data from the outside such as a terminal or a transmission line and send it to the exchange part. Also, the packet storage buffer C
Stores the exchanged data from the exchange processing unit in a standby state for transmission to an external terminal or transmission line.

In the accommodating section 91, the PAD is a data converting section, which performs a function of packetizing external data or returning an internal packet to a data format of an external terminal or a transmission line. The packet transfer module PD is
It arbitrates packets from a plurality of packet storage buffers A existing on one bus, and in accordance with the transfer destination address at the beginning of the packet, through a plurality of packet transfer buffers XP on the PDX bus on the output side, the purpose Has the function to transfer the packet to the transfer destination. On the contrary, the packet transfer module SD arbitrates the packet from the XP buffer on the XSD bus and stores the packet in the packet transfer buffer C on the output bus on the input side according to the transfer destination address at the head of the packet. Has the function to transfer.

FIG. 8 shows a frame format (write) in the method of the present invention. In addition, FIG.
3 is a view showing a frame format (read) in the method of the present invention. The relationship between the command and response when reading and the command and response when writing are
The case of reading and the case of writing are distinguished by looking at the command frame when the command is input from the control unit. Further, when a registration command is issued from the control unit, it is realized by expanding this bit. The interval between the command and the response in each figure is determined in consideration of the absorption of the delay between racks and the delay of the response.

In the logic diagram of the control bus shown in FIG. 6, the frame write operation means the control unit SW- in FIG.
From CTL to each functional module (SD, PD, XP, A
/ C), for example, the operation of writing the data XX to be stored in the fixed register in the packet storage buffer XP # 0. A response frame exists as a response from the command frame at that time and this functional module (in this case, the packet accumulation buffer XP # 0) after the command is executed.

In contrast to the write operation, the read operation is an operation for reading the stored data in the register, RAM area, etc., which is the contents of each functional module, from the control section SW-CTL, and is written to the command side at the time of writing. Although data is attached, data is usually attached to the response side when reading.

Therefore, the command is not limited to a simple write operation to the register, so that it is possible to issue a registration command, a multiple command, etc., in addition to the flags indicating the write and read operations in the control bits of the command section. There are flags that indicate registration commands, multiple commands, and the like. With this flag, when it is a registration command, the functional module side that has received recognizes that the information described in the data section is information for the next registration command,
Processing or execution is performed according to this data.

In FIGS. 8 and 9, s and S are
A frame delimiter bit for recognizing the beginning and end of the command line and response line, and s
Is a start bit indicating the start of the frame, and S is a stop bit indicating the end of the frame. The address indicates the transfer destination of the command, and in this embodiment, 24 bits are designated. However, depending on the configuration of the device, it can be made shorter and compact, or conversely, the address space can be made larger. The control unit controls the command function, R
Specifies whether to read (read) or W (write) and the number of transfer bytes.

The data section is a section in which the data to be transferred is described, and a data string of the number of bytes designated by the control section is transferred. As described above, the data section is added to the command at the time of writing and is read at the time of reading. It is added to the response. The FCS section is the check data, and the address section, the control section, and the data section are realized by a sequential circuit, and the result of division by a specific 16th order function is added (this is also defined in standardization. X.25 checksums may be used).

FIG. 10 shows a frame format (write)
3 shows the details (bit assignment) of the W-command address in FIG. FIG. 11 shows the details (bit assignment) of the control byte of the W-command in the frame format (write), and (a) shows the bit assignment. Further, (b) shows the contents of the data byte number part. FIG. 12 shows the details of the status byte (bit assignment) and the details of the interrupt flag of the W-response in the frame format (write). (A) shows the allocation of each bit of the W-response and (b) shows the interrupt. Details of flags 1 and 0, (c) is F
The contents of the CS error part are shown.

In FIG. 10, the first bit 2 of the address
Bits (A23, A22) are broadcast flags BC1 and BC0, and coded to indicate a broadcast pattern, so that broadcast to the entire control bus or broadcast to a specific bus can be realized. It is assigned higher in the address space. Bits A19 to A16 are a BUS-ID indicating an input / output bus number, and by this bus designation, only a specific bus in the above-mentioned broadcast can be designated.

Bits A15 to A13 are MODUL-IDs for identifying the modules, and the IDs are assigned to the functional units of the functional modules. In addition, "0
00 "," 001 "," 111 "are IDs for additional modules. PAGE-ID and PORT-ID are
Ports are shown for the packet storage buffers XP and A / C, and page IDs are shown for the packet transfer modules PD and SD.

The IE bit assigned to the bit A12 or A7 is a flag for identifying access selection of the internal ("0") or external ("1") register, which is an extended address space, and its address space. By using, it is possible to exchange information as an external interface in the functional module. REG-OFF indicated by bits A7 to A0
SET is the register offset (register address)
However, it is used as a RAM address depending on the page ID of the packet transfer modules PD and SD.

In FIG. 11, the control unit of the frame format designates a multiplex command, a registration command, read / write, and the number of transfer bytes, as shown in (a). The transfer byte is coded, and eight kinds of byte numbers can be designated as shown in (b).

In FIG. 12, on the response side, the status byte has an interrupt flag, as shown in FIG.
It consists of a command normality confirmation bit. The interrupt flag has the content shown in (b). For the control bus access error, the result of the W / R check by parity is displayed when the internal register is accessed, and the access timeout is displayed when the external register is accessed. The detection result of bus cycle abnormality is shown.

The FCS error section indicates the FCS error of the control bus, and the logic and judgment of the FCS errors # 0 and # 1 are defined as shown in FIG. 12 (c). The number of data bytes indicates the number of bytes in the data part, and is set to "000" during normal W-access. However, the number of data bytes is added as response data when detailed information accompanies the detection of a failure, and when this number of bytes is described, the data portion exists even at the time of response. For example, in the case of a control bus access error of b5, the alarm register information is returned as the data byte number of the command "010" in the meaning of history.

FIG. 13 shows details of the R-command address in the frame format (read) (bit.
Assignment). FIG. 14 shows the details (bit assignment) of the R-command / control byte in the frame format (read), and (a) shows the bit assignment. (B) shows the contents of the R-transfer byte number part, and shows the request and return byte number at the time of R-access.

FIG. 15 shows the details of the status byte (bit assignment) and the details of the interrupt flag of the R-response in the frame format (read). FIG. 15A shows each bit of the R-response. (B) shows the details of the interrupt flags 1 and 0. FIG. 16 shows details (bit assignment) of the status byte of the R-response in the frame format (read), and (a) shows F.
It shows the contents of the CS error part, showing the logic and judgment of the FCS errors # 0 and # 1 of the control bus, and (b) shows the contents of the data byte number part. Indicates the number of bytes in.

The frame format at the time of reading is different from the frame format at the time of writing described above in that there is no data portion in the command portion and data is added to the response portion, but other Since the points have almost the same configuration, detailed description will be omitted.

FIG. 17 shows a first embodiment of the present invention, in which 100 is an apparatus monitoring control unit, and 200-1 to 200-1.
200-i is a higher-level functional module, 300-i-1 to
300-i-j are lower functional modules. Further, in the apparatus monitoring control unit 100, 110 is a transmission unit that performs information transmission processing, 120 is a reception unit that performs information reception processing,
Reference numeral 130 is a control unit.

Upper functional modules 200-1 to 200
-I, 210-11 to 210-i1 are transmission units that perform transmission processing to the device monitoring control unit 100 via the upper control bus 500, and 210-12 to 210-i2 are lower control buses 510-1 to 510. 220-a transmission unit that performs transmission processing to a lower-level functional module via i
Reference numerals 11 to 220-i1 denote reception units that perform reception processing from the device monitoring control unit 100 via the upper control bus 500.
20-12 to 220-i2 are lower control buses 510-
1 to 510-i is a receiving unit that performs a receiving process from a lower functional module.

In the higher-level functional module 200-i, 250 is a registered command holding unit for holding registered commands, 260 is a command logging table for logging commands, 270 is a command analyzing unit for analyzing commands, Reference numeral 280 denotes a registration command processing unit that processes a registration command. An information storage unit 290 includes a status register 291 that holds a status of processing and completion in the registration command processing unit 280 and an information storage register 292 that stores information.

Lower functional modules 300-i-1 to 300-i connected to the upper functional module 200-i
-J, the 310-1 to 310-j are the upper functional modules 200- via the lower control bus 510-i.
The transmission units 320-1 to 320-j connected to i are reception units that perform reception processing from the upper functional module 200-i via the lower control bus 510-i.

In FIG. 17, the control unit 130 in the device monitoring control unit 100 determines the functional module 200 or 300 according to the intended processing, and further determines the type of information (control command) required in the functional module 200 or 300. ) Is defined and a notification is sent to the transmission unit 110 by sending a command frame to the target functional module 200-i, 300-i via the control bus 500. Transfer notification.

The command frame from the transmitter 110 is
The same notification is sent to a plurality of functional modules 200 or 300. Receiver 22 in the functional module 200
In 0-11 to 220-i1, the received command frame is analyzed by the command analysis unit 270 to determine whether or not the command is addressed to the own module. The reception information is notified to the unit 280. On the other hand, if it is not addressed to the own module, the command frame is ignored. Similar processing is performed also in the reception unit 320 in the functional module 300.

The command analysis section 270 judges the above-mentioned processing procedures 1 to 3 for the command that has been taken in,
Executes processing to edit any hardware information.

FIG. 18 shows an example of the structure of the command analysis section, which is the command analysis section 270 shown in FIG.
270A is a circuit block of FIG.
70B is a command analysis circuit. Command analysis unit 27
At 0, the command analysis circuit 270B performs processing such as editing on each of the illustrated information in the fetched command by the procedure determination circuit 270A while determining the above-described processing procedures from to, and the response information and each part are processed. Create notification information.

When the processing content analyzed by the command analysis unit 270 specifies the execution of processing of a registered command registered in advance, the registered command processing unit 280
The registration command stored in the registration command storage unit 250 is searched in advance and the corresponding command is called. Further, in order to avoid a conflict with a subsequent command from the device monitoring control unit 100, the control bus 510-i downstream of the functional module 200-i is disconnected from the control bus 500 directly connected to the device monitoring control unit 100, and thereafter, The command retrieved from the registered command storage unit 250 is sent to the transmission unit 210-i.
The lower-level functional module 300 is notified via 2.

The command frame from the transmitting unit 210-i2 is received by the receiving unit 320 by the corresponding functional module 3.
Only those destined for 00 will be received. In the corresponding functional module 300, after the target information is edited or processed according to the instruction of the command, the fact is transmitted by the transmission unit 310.
It is returned to the receiving unit 220-i2 via. The reply at this time is a response frame.

The response frame from the transmission unit 310 is received by the reception unit 220-i2, and the contents of the frame are notified to the registration command processing unit 280. The processing in the registration command processing unit 280 differs depending on whether or not there are a plurality of registration commands.

FIG. 19 shows an example of the configuration of the registration command processing unit, illustrating the circuit block of the registration command processing unit 280 in FIG. 17, and 280A latches the frame content notification from the command analysis unit 270. The latch circuit 280B for instructing the registration command holding unit 250 searches for the registration command, receives the registration command from the registration command holding unit 250, and receives the end or continuation notification. The registration command control circuit 280C stores the response information. Response information storage buffer, 28
0D is a state control unit that controls the state of each unit, 280E is an execution command register that holds an execution command, 280F
Is a retry count register for storing the maximum retry count.

The registration command processing unit 280 executes this command when there is one registration command, waits for the response, and immediately outputs the response information.
The process is completed by returning to 00.

If there are two or more registration commands, the next subsequent registration command is executed, the downstream response frame is returned via the receiving section 220, stored in the response information storage buffer 280C, and then stored. When the response of the final command is received by sequentially repeating the process of executing the registration command of 1., the state control unit 2
The 80D extracts the response information for the plurality of commands from the response information storage buffer 280C, assembles the response frame for return, and assembles it into the device monitoring control unit 10.
Return to 0.

When the last response frame in the case of one or more registration commands is received, the functional module 200 restores the disconnection between the upper control bus 500 and the lower control bus 510-i. The registration command processing unit 280 stores the information obtained by the previously executed command / response in a predetermined area (response information storage buffer 280C), and sets the processing in progress flag and the processing completion flag according to the respective states. Set.

In the device monitoring control unit 100, it is determined whether the registration command processing unit 280 is processing or the processing is completed depending on the contents of the status register 291 in the information storage unit 290 in the functional module 200-i. , Monitor by command frame. When the processing is completed, the information storage register 2 in the information storage unit 290
By extracting the information stored in 92, the information of the target functional module 300-i can be collected.

According to this embodiment, the functional module 200
In the information collection period of the function module 300-i in -i, the device monitoring control unit 100 sets the function module 20
Since processes such as 0-1, 200-2, ... Can be executed in parallel, the bus access frequency can be reduced, bus efficiency can be improved, and information collection speed can be increased. Therefore, the device monitoring control unit 100 can detect the occurrence of a failure at an early stage, can prevent the spread of the failure, and can shorten the operation stop time.

As another embodiment of the present invention, once the registration command processing unit 280 processes the registration command,
It is checked whether or not there is an error in the response frame returned from the downstream functional module, and if there is an error, the processing of the registration command is executed again to reduce the load on the device monitoring control unit 100. In addition, the reliability can be further improved.

As the operation in this case, the writing of the response information in the registration command processing unit 280 to the response information storage buffer 280C does not unconditionally store the response frame from the downstream but the reception state of the receiving circuit 220. After confirming the above, if the command is normal, it is stored. If an error is detected, the command stored in the execution command register 280E of the registration command processing unit is reissued. The number of re-issuances can be determined by storing the maximum number of retries in the retry count register 280F in advance.

In a system as shown in FIG. 4,
For each module or printed circuit board unit, as an emergency interrupt notification method for urgently notifying the device monitoring control section of an abnormality due to the occurrence of a severe failure, if the monitoring section constantly polls each section As the number of target parts increases, the monitoring time becomes huge and it becomes impossible to detect an urgent notification. There is also a problem that the processing load on the device monitoring control unit side due to the polling process becomes enormous.

On the other hand, in order to notify the emergency abnormality by interruption from the target section, since each section is dispersed,
There is a problem that the circuit becomes complicated because control is required to avoid collision on the bus.

In order to avoid these problems, in the case of the tree-shaped control bus 500, the polling method and the interrupt control are selectively used according to the hierarchy, thereby making the interrupt notification method relatively fast and highly versatile. Can be realized.

FIG. 20 shows an emergency abnormality notifying system according to still another embodiment of the present invention. The same components as those in FIG.
300-1-j, ..., 300-i-1 to 300-i-k
Is a subordinate functional module.

On the control bus 500 connected from the device monitoring control unit 100, the target module and the printed circuit board are monitored by periodic polling. In this case, during the response to the command, all function modules 30 further downstream of the function module 200 are
The logical sum of the presence or absence of a fault in 0 is inserted, and the presence or absence of a fault is notified to the device monitoring control unit 100.

Fault detection of all the downstream functional modules 300 in the functional module 200 may be performed using a separate line other than the control bus 510 for commands and responses, but it should be performed by an independent command in the functional module 200. You can also For example, the information may be collected by a periodic command and response based on a timer value. In this embodiment, when the function module 200 is notified of the occurrence of a failure by a separate line,
In the functional module 200, the failure information is set in a register, and when the response is made to the command from the device monitoring control unit 100, the contents are notified.

FIG. 21 shows an example of the process flow of the control unit, and illustrates the process flow of the control unit 130 in FIG. 17, where (a) shows a schematic flow and (b) shows an operational process. The flow is shown.

The control section 130 of the apparatus monitoring control section 100 performs the processing in the normal operating state after the initialization processing accompanying the startup of the apparatus. The processing flow in this steady state includes the abnormality detection flow of the present embodiment, and after the operation processing of steady operation shown in (b), which number of abnormality of a certain functional module 200 is detected by the polling value. Ask to confirm (either read or write operation is acceptable).

Next, the polling value is updated. At this time, the updated value is stored again as a polling value so that the registered functional module is repeated in a round robin manner. As a result, it is possible to realize polling in which the registered functional modules are permanently monitored one by one every time.

FIG. 22 shows an example of the configuration of the transmission section in the device monitoring control section, and illustrates the circuit block of the transmission section 110 in FIG. 110A is various registers, 110B is a P / S unit for converting a parallel signal into a serial signal, 110C is an FCS adding unit for adding a frame check sequence, and 110D is an S for adding a start bit s and a stop bit S of a frame. /
s part, 110E is a port specifying part for specifying a port, 11
Reference numeral 0F is a selector (SEL) that performs enable control of a designated port.

From the control unit 130, the determined function module number and the bus number and port number indicating the hardware position to which the function module is connected are set in various registers 110A and formatted as a command frame. It The assembled frame is P /
The parallel signal is converted into a serial signal in the s section 110B, the FCS is added in the FCS adding section 110C, the start bit and the stop bit are added in the S / s section 110D, and the result is transmitted to the port for the target control bus. To be done.

The receiving side determines whether or not there is an abnormality in the corresponding functional module by looking at the response status of this command. If something is wrong,
Search the alarm register of the corresponding function module and inquire for detailed information.

The monitoring command frame from the device monitoring control unit 100 is received by the receiving circuit 22 in the functional module 200.
Received and recognized by 0.

FIG. 23 shows an example of the configuration of the receiving section in the functional module, and illustrates the circuit block of the receiving section 220 in FIG. 220A is an S / that detects the stop bit S and the start bit s.
s detection unit, 220B is a format unit for checking the frame format, 220C is an FCS unit for detecting a frame check sequence, 220D is an S / P unit for converting a serial signal into a parallel signal, and 220E is a register for storing a reception state. Is a reception state section, 220F is an address section that is a register that stores received addresses, 220G is a data section that is a register that stores received data, 220H is a control section that is a register that stores received control information, and 220I is A comparison unit 220J that confirms the information stored in each register, and 220J is an address storage unit that stores information such as the address of its own module.

For the received command frame, S /
The s detector 220A recognizes the start and end of the frame. When the head of the frame is detected, the distribution is notified to the format section 220B, the FCS section 220C, and the S / P section 220D. The FCS section 220C checks the received frame and, if there is no data error, stores the fact in the reception state section 220E. Similarly, the format unit 220B confirms that the transfer data has a specified number of bytes and that the data conforms to a predetermined format, and if there is an abnormality, stores it in the reception state unit 220E.

In the S / P section 220D, the received data is converted into a parallel signal to be used internally, and stored in the address section 220F, the data section 220G, and the control section 220H according to the required format. Comparison unit 2
The 20I confirms the destination of the command by comparing the address of the address section 220F with the address in the address storage section 220J. The comparison unit 220I also checks the transfer destination of the functional module, the module ID, and the command type.

When it is confirmed by the address confirmation that the command is addressed to the own module, the control unit information and the data information following the address are respectively controlled by the control unit 220H.
And stored in the data section 220G. Based on the information in the control unit 220H, the control bus line to the functional module 300 located downstream of the own module is disabled. As a result, it is possible to prevent that the response from the functional module 200 cannot be notified to the device monitoring control unit 100 by the response information from the downstream. The disable timing of the downstream bus does not cause any problem even when sending a response.

When the received command frame has no abnormality in the confirmation so far, the target register is read or written, and the RAM is accessed or the registration command is processed. In the following, a mechanism for notification of an emergency abnormality will be described.

In order to create the response information of the previously received command frame, the transmitter 210 in the functional module 200 is activated.

FIG. 24 shows an example of the configuration of the transmission section in the functional module, and illustrates the circuit block of the transmission section 210 in the functional module 200 of FIG. Reference numeral 210A is a transmission control unit that controls the transmission of a response, 210B is a data unit that stores reply data from the command analysis unit 270, 210C is various alarm information units that are registers that store various alarm information, and 21C.
Reference numeral 0D is a selector for selecting the data of the data section 210B and various alarm information, 210E is a reception status section for storing the reception status, 210F is a frame generation section for generating a frame, and 210G is a self state for storing status information of the own module. An information section, 210H is a downstream status information section for storing downstream status information, 210I is a status section for generating a status, 210J is a P / S section for converting a parallel signal into a serial signal, and 210K is a frame check sequence. The FCS portion 210L has a start bit s and a stop bit S indicating the start and end of the frame.
It is the S / s section for adding and.

When the transmission control section 210A receives the command frame reception notification, it waits for the response information for command confirmation. This response information differs depending on the command, but if it is a normal write command, the data sent to the target register or RAM is written, and the transmission timing of the response frame comes after the completion of the write confirmation. Therefore, if there is no abnormality in the command frame when received, the target data part is returned in the form described in the frame format.

Here, the interrupt bit of the status information in the response frame is used to indicate whether or not there is a fatal error in the own function module. One bit of the logical sum condition of the error (this information is State information section 210
Always stored in G. Since this register is not cleared unless it is read, the state that occurred in the past is stored and saved in this register. Therefore, 0 is cleared by reading at the time of initialization processing), and the functional module 30 connected downstream of its own functional module.
Logical sum condition 1 of the information stored by the register (downstream status information unit 210H) for notification of emergency abnormality of 0
A bit is added to the status and returned as response information to the device monitoring control unit 100.

As described above, according to the present embodiment, the polling control and the interrupt control are selectively used in the hierarchical control bus, so that the circuit structure is simplified and
It is possible to speed up the processing of the emergency interrupt.

FIG. 25 shows a second embodiment of the present invention, in which the same components as those in FIG. 17 are indicated by the same numbers, and in the device monitoring control unit 100, 111 performs the information transmission processing. A transmitter, 121 is a receiver for receiving information, and 131 is a controller.

Upper functional modules 200-1 to 200
-I, 211-11 to 211-i1 are transmission units that perform transmission processing to the device monitoring control unit 100 via the upper control bus 500, and 211-1212 to 211-i2 are lower control buses 510-1 to 510. 221-a transmission unit that performs a transmission process to a lower-level functional module via -i
Reference numerals 11 to 221-i1 denote reception units that perform reception processing from the device monitoring control unit 100 via the upper control bus 500.
21-12 to 221-i2 are the lower control buses 510-
1 to 510-i is a receiving unit that performs a receiving process from a lower functional module.

Lower functional modules 300-i-1 to 300-i connected to the upper functional module 200-i
-J, 311-1 to 311-j are connected to the upper functional module 200- via the lower control bus 510-i.
The transmission units 321-1 to 321-j connected to i are reception units that perform reception processing from the upper functional module 200-i via the lower control bus 510-i.

FIG. 26 shows an example of the configuration of the transmission section in the device monitoring control section, illustrating the circuit block of the transmission section 111 in FIG. 25, and 111B to 111F.
Are similar to the portions indicated by the numbers 110B to 110F in FIG. 22, respectively. 111A is a register for storing the SEQ number, code, etc. and other various registers.

FIG. 27 shows an example of the configuration of the receiving section in the device monitoring control section, illustrating the circuit block of the receiving section 121 in FIG. 25, and 121A-0, 121A-0,
121B-0, 121C-0 and 121A-1, 12
1B-1 and 121C-1 are an S / s unit that detects a stop bit S and a start bit s, and an FCS confirmation unit that confirms a frame check sequence, for a duplicated reception input of a 0-system and a 1-system, respectively. , An S / P unit for converting a serial signal into a parallel signal. 121D is a duplexing confirmation unit that confirms that the received signal is duplicated, 121E is a selector (SEL) that selects one of the duplicated signals, 121F is a reception control unit that controls the reception processing for the received signal, and 121G is A FIFO or buffer for priority information, 121H is a FIFO or buffer for non-priority information, 121I is a SEQ latch for latching SEQ numbers, and 121J is a multiple response table for storing multiple responses.

In the device monitoring control unit 100, the command issued from the control unit 131 is sent to the corresponding functional module via the transmission unit 111. The command is issued corresponding to the read operation and the write operation as described above. For example, the functional module 200-i
If the command is addressed to it, it is received by the reception unit 221-i1 in the functional module, analyzed by the command analysis unit 270, and registered command processing unit 28.
After the corresponding command is executed by 0, the response is returned by the transmission unit 211-i1.

In the series of operations from the command transmission to the response reception, in the device monitoring control unit 100,
After issuing the command, issue the next command without waiting for the response from the functional module. By doing so, the device monitoring control unit 100 can continuously issue commands, so that the monitoring software of the device monitoring control unit 100 can reduce the time loss due to waiting for a response, and can also execute the normal command The command can be immediately executed only by classifying the processing and the operation of the emergency processing into levels.

According to this embodiment, the functional module 2
As a function added to 00-i and 300-i, a control circuit unit for avoiding the collision of the response of the preceding command on the control bus is newly required. In addition, in the device monitoring control unit 100, in order to perform command processing and response processing, a message table for determining which command the response is for and a multiple response table in the receiving circuit unit are required.

28 to 30 show the processing flows (1) to (3) in the control unit. FIG. 28 is a transmitting side flow, FIG. 29 is a receiving side flow, and FIG. 30 is a message. The format of each table is shown.

28 to 30 show an example in which the operation of the control section 131 in the apparatus monitoring control section 100 is realized by software, but such processing may be realized by a hardware sequencer. It's easy. In the following, for convenience of description and easy understanding of processing, description will be made by cooperation of software and hardware.

The processing on the transmitting side shown in FIG. 28 and the processing on the receiving side shown in FIG. 29 are executed asynchronously. The synchronization between these two flows is performed by the message table shown in FIG.

In the transmission process, after the initialization process is executed at the first start-up, the loop state is constantly endlessly processed in the loop state. However, in reality, not only the command processing flow is performed, but also the regular processing of other control units is performed. This also applies to the reception process.

First, in the steady process, when a command is issued in the control unit, it is confirmed that there is a space in the message table, and if there is no space, the process waits until there is space and then another process is executed. , Check the availability again. The fact that there is no space here indicates that the commands for that amount are being executed, and it is necessary to set the table size appropriately at the time of initialization, depending on the degree of nesting of multiple commands. is there. Normally, it is considered sufficient to prepare about 16 to 256 pieces, but this is not the limit depending on the scale of the device to which the device is applied.

If the message table has a space, the table is first reserved. This is performed by describing in the empty / occluded portion in the message table that it is in use (closed state). That is, the vacant state means that the vacancy block is vacant.

Next, a command frame to be transferred to the target functional module is generated, set in the necessary transmission register and transmitted. Then, after confirming that the message has been sent normally, the necessary items are entered in the message table. The contents described in the message table are basically the same as those of the transmitted command frame. Address, ID, command, SEQ (sequence)
Is similar to the command frame format.

In FIG. 30, SEQ is information unique to the multiple command method. This is a number added to the sequence on the transmission side, and is a number that is updated one by one in command units 0 to 511 of modulo 9. The address and ID are address information specified in the frame format section. The number is a convenient logical number for searching the message table, and is used for the timeout process at the time of response together with the time stamp of the transmission time, and also as pointer information for simplifying the table search at the time of reception. Therefore, it is also described in the command frame.

In the reception processing flow shown in FIG. 29, information is written in the message table due to issuance of the transmission command, but at the same time, a timer queue is generated as a guard timer when no response comes. To be done.

FIG. 31 exemplifies the control method of the time-out processing, and shows a timer queue composed of a daisy chain. In the figure, the time is queued in the sequence ascending order, so that the time-out occurs earlier at the beginning of the point. When there is a normal command processing response, the corresponding number of this timer is retrieved from the message table and the queue number at that time is compared to retrieve this data, and the pointers before and after that are directly connected. By disconnecting the chain from this timer queue.

When the send command is executed, it is necessary to write the information in the message table and update the timer queue at the same time. To create a timer queue,
The queue is daisy-chained to the queue in the order that the timeout time is closest to the current time. This chained information includes
The logical number of the message table is described, and the reception processing unit constantly checks the timeout. Since this part can reduce the load of software if it is implemented by another processing flow or hardware, it is usually implemented by hardware, and software is notified by interrupt only when a timeout occurs. The method is adopted.

As the timeout processing in this timer chain, the timeout processing is performed when the current time has passed the timeout time of the data at the top. Note that, normally, before the timeout, the timeout is not generated because the queue is removed from the queue when the response arrives.

When a time-out occurs, the command response entered in the logical number table described in the timer queue has not been received, so it is considered that there is a possibility of failure information, and the device monitoring control is performed. The section 100 is notified of the contents of the table, and this information in the message table is returned to the empty state, whereby the time-out process is completed.

Next, when the response is received, the response information is described in a predetermined multiple response table. In FIG. 27, one of the duplicated systems,
Alternatively, when the reception information is input from both, the S / s unit 12
The 1A, FCS confirmation section 121B, etc. confirm the format of the received information by hardware, and the confirmation notice is notified to the processor via the reception control section 121F. The processor thereby confirms the received frame as shown in FIG.

After that, information of a normal system (if both systems are normal, information of either system) is stored in the multiple response table 121J. At this time, the SEQ in the received response frame is stored as an address as the logical number of the multiple response table 121J. The response table for reception may be of a FIFO format, and the processing may be performed in order from the response frame that arrives first. The required response is prioritized.

The information stored in the multiple response table 121J can flexibly adjust the handling of the received data by, for example, attaching a priority level at the time of command execution according to the degree of urgency from among a plurality of received information. It can be so. This forms a queue of the priority class of the multiple response table 121J with the FIFO, and
This can be realized by configuring a queue with an SEQ number for each priority level in O. In this embodiment, the priority class has two levels, but it is easy to arbitrarily increase the number of levels.

As shown in FIG. 29, when there is a reception response in the multiple command reception flow, the reception frame is confirmed as described above. Next, the SEQ information from the FIFO queues 121G and 121H according to the priority is obtained, the multiple response table 121J is searched from the SEQ information, and the necessary received data and the status for confirming the writing are taken into the processor. .. Then, the message table shown in FIG. 30 is searched from the response information number and the address, command, ID, and SEQ of the received information are confirmed, and then the empty / occluded state in the message table is returned to the empty state. The timeout daisy chain indicated by 31 is removed, and the reception process is completed.

FIG. 32 shows an example of the format of the command and the response, showing an example at the time of writing, (a) shows the command, and (b) shows the response. In the figure, the start bit s in the command
And the addresses are similar to those shown in FIG.
The start bit s and control in the response are the same as in the case of the command, and the address is the same as that shown in FIG. In the frame format of the response, the control unit is arranged so as to be at the head, but this is for use in bus arbitration on the control bus, as will be described later.

FIG. 33 shows an example of the configuration of the receiving section in the functional module, illustrating the circuit block of the receiving section 221 in FIG.
1B, 221C, 221D, 221E, 221F, 22
1G, 221H, 221I and 221J are respectively shown in FIG.
S / s detection unit 220A and format unit 2 in FIG.
20B, FCS section 220D, S / P section 220D, reception status section 220E, address section 220F, data section 220
It corresponds to G, the control unit 220H, and the address storage unit 220J.

The receiver 221 shown in FIG. 33 shows the structure of the receivers in the functional modules 200 and 300.
Same as the receiving unit 220 shown in FIG.
The difference here is that the downstream bus enable control is not performed. This is because when the enable control is performed, the command to the downstream functional module is stopped when the next command is issued during the period until the response is returned. Therefore, in this embodiment, in order to pass the command to the downstream side, the enable control of the downstream bus is not performed here, and the transmission circuit arbitrates at the time of reply.

FIG. 34 shows an example of the configuration of the transmission unit in the higher-level functional module, and illustrates the circuit block of the transmission unit 211 in FIG.
A, 211B, 211C, 211D, 211E, 211
F and 211I are the transmission control unit 210A, the data unit 210B, and the various alarm information units 21 in FIG.
0C, selector 210D, reception status section 210E,
It corresponds to the frame generation unit 210F and the status unit 210I.

The transmitting unit 211 shown in FIG. 34 is basically the same as the transmitting unit shown in FIG. 24, but instead of the circuit block for status notification, in this embodiment, a buffer unit is used. 211M, delay circuit 211N, gate 211
Q, 211R, a frame detection circuit 211P from the downstream, and a selector 211S. However, there is no problem even if the circuit shown in FIG. 24 is used.

In FIG. 34, it is constantly determined whether or not there is a response frame for the data from the downstream side, and if there is a frame, that frame is preferentially transmitted. However, it is not always necessary to give priority. If there is no frame on the bus, if the response information to the command addressed to the own module is in the return state (this can be determined from the temporary storage in the buffer unit 211M after the frame generation unit), the buffer unit 2
The reply frame (response frame) stored in 11M is transmitted. At this time, when the downstream frame detection circuit 211P detects a response frame from the downstream, the frame is temporarily stored in the delay circuit 211N, and after confirming that the transmission of the response frame of the own module is completed, By transmitting the response frames accumulated in the delay circuit 211N, the collision of responses due to multiple commands is avoided.

FIG. 35 shows an example of the structure of the transmission section in the lower-level functional module, and illustrates the circuit block of the reception section 311 in FIG. 25, which is 311 in the figure.
A, 311B, 311C, 311D, 311E, 311
F, 311I and 311M are, respectively, in FIG.
Transmission control unit 211A, data unit 211B, various alarm information unit 211C, selector 211D, reception status unit 211E, frame generation unit 211F, status unit 21
1I, corresponding to the buffer unit 211M.

The transmitter 311 shown in FIG. 35 arbitrates the bus in the functional module 300 located downstream. In this case, as in the case of FIG. 34 described above, by connecting the functional modules 300 by a daisy chain, a circuit similar to that of FIG. 34 can be used,
Buses require slightly different controls. Conversely, FIG.
34 may be applied to the case of FIG. 34, and the control bus in FIG. 34 may also be a complete bus connection.

In FIG. 35, transmission is performed from the other function module to the control bus 510 (0 system, 1 system), and the state on the control bus 510 is monitored by the comparison circuit 311N. Since the bus operates synchronously with the same clock, when there is a frame on the bus, the transmission frame is naturally kept waiting in the buffer unit 311M. At this time, it is assumed that the priority and SEQ number of the control unit at the beginning of the frame in the buffer unit 311M are preread and stored in the register.

Here, it is confirmed that the response frame of the control bus is gone, the frame of the own module is transmitted, and at the same time, the state on the control bus is monitored.
Of course, other functional modules may start transmitting similarly, but if not at the same time, the functional module that has already transmitted a response frame on this control bus will transmit without being disturbed by other modules until the transmission is completed. It can be performed.

When another module simultaneously sends a response frame, the comparison circuit 311N has a value different from the value transmitted by the own module, so that a collision on the bus is detected. In this state, the comparator circuit that has detected a different value controls the output control circuit 311Q to immediately stop the transmission, and again monitors the state of the control bus during the second monitoring time determined by the retransmission timer 311R. The re-monitoring time in this case is determined by the SEQ number, and S
The smaller the EQ number, the more preferentially the transmission becomes possible. At this time, by setting the priority value to the most significant MSB bit, the higher the priority, the faster the retransmission.

The priority / SEQ section 311P sets the priority or SEQ number for the retransmission timer 311R. Further, by defining the condition with a logical OR by hardware, a module with a high priority can continue transmission even if a collision occurs, and the module with a high priority or S
A bus arbitration method in which a module having a smaller EQ number has a higher transmission probability can be realized.

The reason why the SEQ number is used for arbitration on the bus is that the control command from each module has a unique value depending on the SEQ bit, and the same value can be obtained by increasing the modulo value. Because it can be guaranteed that there is no. There is a method of using the absolute address of the functional module instead of the SEQ bit, but this method is not preferable because the priority module is uniquely determined by the value from the functional module.

As described above, according to this embodiment, the command to be sent from the device monitoring control section is continuously sent without waiting for the response from the functional module, so that the waiting time for command sending can be shortened. In this case, the response from the functional module can be flexibly controlled by setting the order of the response of the functional module according to the priority or according to the SEQ number and the priority.

FIG. 36 shows a schematic configuration of the third embodiment of the present invention, showing a method of extending the parallel control bus by the serial control bus. The same parts as those in FIG.
2, ... are parallel control buses and 510-i are serial control buses.

In the exchange device or the like, one system is composed of a plurality of racks (or housings). Further, in the same rack, there are a plurality of sub-housings called a shelf, which are one group. In FIG. 36, the inside of the frame shown by the dotted line represents the sub-housing, and these are connected by one or a plurality of backplanes. Although it may not necessarily be a backplane, a group of buses connected by a similar bus connection is considered here.

In such a group, when the above-mentioned control bus is to be interfaced in the serial state as it is, the serial bus is converted into the parallel bus at the entrance of the functional module, and this conversion is performed. A processing unit that separates and analyzes the command portion, the address portion, and the data portion from the stored information is required. Therefore, only the portion where the distance between the housings becomes longer in the middle is realized by a serial bus like the illustrated serial control buses 500 and 510-i, and the inside of the sub housing is restored to the original parallel bus format. Pseudo processor bus type parallel control bus 511-
By setting them as 1,511-2, ..., The interface of each part in the sub-housing or the functional module can be generalized.

FIG. 37 shows a concrete structure of each part in the third embodiment. In FIG. 37, the same parts as those in FIGS. 17 and 25 are shown by the same numbers, and in the higher-level functional module 200-i, 230 is an internal functional block unit (for example, a control unit), and 240 is a pseudo processor bus control unit. 511-i is a parallel control bus.

In FIG. 37, a frame enclosed by a dotted line indicates, for example, the inside of a sub-housing 600 connected by one back plane, and the parallel control bus 511-i is used.
The internal functional modules 300-i-1, 30
Interfaces with 0-i-2, ..., 300-i-k and with each unit in the internal function module 200-i are realized.

In the present embodiment, the interface performed on the pseudo processor bus is the device monitoring controller 100.
By interfacing as if there is a processor inside, there is an advantage that the interface can be easily realized without a serial control bus when the device is degenerated, and the device monitoring control unit 100 is also provided. Since the external pseudo processor interface basically does not need to be changed by changing the processor inside, it is easy to realize the ideal processor interface.

FIG. 38 shows an example of the configuration of the pseudo processor bus control unit, and illustrates the circuit block of the pseudo processor bus control unit 240 in FIG.
In the pseudo processor bus control unit 240, 241 is a receiver, 242 is a clock phase absorption asynchronous circuit for realizing clock phase absorption, 243 is a bus driver, 2
Reference numeral 45 is a timing generation circuit that generates various control signals for the control line.

The command frame from the device monitoring control section 100 is sent to the receiving section 221-i of the functional module 200-i.
1, the format conversion is performed as described above, and the command analysis unit 270 and the registration command processing unit 2 are received.
At 80, the address information is decomposed into various control lines such as data and bus enable timing, read and write, and the information is notified to the pseudo processor bus control unit 240.

Various kinds of information such as these data, addresses, control lines, etc. are stored in the receiver 241 and the timing generation circuit 24.
5 is recognized and received. The data and address information is transferred to the asynchronous circuit 24 that realizes the phase absorption of the clock.
2 converts into a bidirectional bus and also absorbs the clock phase between the external clock and the internal clock. The bidirectional bus realized here is interfaced with an external bus via the bus driver 243.

Further, the timing generation circuit 245 notifies the clock phase absorption asynchronous circuit 242 of the control signal for phase absorption and the timing for switching the bus in accordance with the information from the control line. The bus driver 243 is notified of the switching timing for switching the bidirectional bus. In addition, the timing generation circuit 24
Reference numeral 5 designates a RAM, a ROM, a register, various switches and LE existing outside (for example, an internal function block 230).
A basic control timing signal required by a hard logic unit such as D is generated.

FIG. 39 shows an example of the configuration of the internal functional block section. FIG. 39 shows a detailed circuit block of the internal functional block section 230 in FIG. 37, and a parallel pseudo processor bus when used internally. Shows the general configuration of. In the internal function block unit 230, the read / write control unit 233 extracts the necessary timing from the control timings notified by the various control lines from the pseudo processor bus control unit 240, and the bus direction switching unit 231 performs both of them. After switching the bus for the destination bus, the decoder 232 decodes the address, and the decoded signal is used to decode the target portion (RAM 23
5-1, Register (reg.) 235-2, R0M235
-3, switch or LE made of hard logic etc.
The read or write operation is performed by enabling the circuit block 235-4) such as D.

Completion of the read or write operation is notified to the pseudo processor bus control unit 240 via the above-mentioned control line. When the timing generation circuit 245 in the pseudo processor bus control unit 240 receives the notification of completion of the read or write operation, it notifies the registration command processing unit 280 of necessary data as response information. The notification route from the registration command processing unit 280 to the device monitoring control unit 100 is the same as in each of the cases described above.

According to the present embodiment, by disassembling the serial bus into the parallel bus in one functional module and connecting the adjacent functional modules with the parallel bus, the serial bus and the parallel bus are separated. The number of conversion circuits can be reduced, and the circuit scale can be reduced.

In addition to the connection between the functional modules described above and between the device monitoring controller and the functional modules,
A data line for exchanging target data and a control line for realizing the function originally intended by the functional module are connected. The connection system related to the original target data is not necessarily the same as the connection system of the control bus described above, but it is more general that it is different.

Further, the control system is wholly connected in a star shape or a bus shape from the device monitoring control unit, but the target data system is not necessarily connected to the device monitoring control unit. Each functional module may be connected by multiple target data systems.

In the following, the target data system will be described by taking as an example the case where all functional modules are always combined.
If they are not combined, prepare a dedicated pseudo-purpose data system between them, or if there are multiple connection systems, select them as needed in the functional module section to use them easily. It is feasible.

FIG. 40 shows the overall structure of the high reliability control bus in the fourth embodiment of the present invention.
01 is a device monitoring controller, 201-1, 201-i, 20
Reference numeral 1-N indicates an upper functional module, and 301-i-1 indicates a lower functional module. Also 500,510-
i is a control bus, 700-1, 700-m, 700-p,
700-r is a target data line.

In the functional module 201 or 301,
Original data line 700 and control bus 500, 510
Are connected as shown in FIG. Figure 4
In the example shown in FIG. 0, the functional module 201 and the device monitoring control unit 101 are connected in a control bus in a bus format and in a tandem connection (a part is a bus connection) to target data lines. Further, the functional module 301-i has a sub-monitoring unit of the control bus as described above, and is located in the lower order of the functional module 201-i, but the target data line is the functional module 201-i. Equivalent bus connection.

Furthermore, in the functional module 201-N,
It has a one-way bus configuration in which target data lines from two functional modules are input. Destination data line 70
0-r does not necessarily have to be a bus configuration, but may be between the functional modules 201-i and 201-N, and the functional modules 301-i-1 and 2
A different bus may be provided between 01 and N.

FIG. 41 shows a functional block configuration example in the device monitoring control section, and illustrates the configuration of each part in the device monitoring control section 101 shown in FIG. One or more destination data lines 700 as shown
The original data is exchanged by the receivers 171-1 to 171-k and the drivers 172-1 to 17-1.
72-k and original functional blocks 150-1 to 150
By -k, the processing of the intended function of the original data is realized.

On the other hand, the original data and the data from the control system are combined and output to the target data line from the combining units 162-1 to 162-k and the combined target data line. Separation units 161-1 to 161-k for separating information into original data and control system data are provided.

Further, a routing circuit 140 is provided so that the control command from the control unit 130 can be transferred to any port. Routing circuit 140
Has a function of performing detour transfer to a predetermined route while avoiding the port when an error occurs or a failure occurs in the transmitted data line. Therefore, it has a function of relaying the control frame from the reception circuit to the transmission port of a different port again instead of the control unit 130.

FIG. 42 shows an example of the functional blocks in the functional module, and illustrates the functional blocks in the functional module 201 and the functional module 301 in FIG. Similar to the device monitoring control unit 101,
A plurality of target data lines 700 are connected, and a separating unit 161 and a combining unit 162 exist before and after the original functional block 150. These internal circuit blocks are the same as those of the device monitoring control unit 101.

In FIG. 42, the same components as those in FIGS. 37 and 41 are designated by the same reference numerals, and they have the same functions. Therefore, the transmitter 211 and the receiver 22
1, the command analysis unit 270, and the registered command processing unit 28
By providing the routing circuit 140 between 0 and 0, a command frame or a response frame is transmitted or received in either direction.

FIG. 43 shows an example of the configuration of the transmission section in the device monitoring control section, and illustrates the circuit block of the transmission section 112 in FIG. 112A, 11
2B, 112C, 112D, 112E, and 112F are registers 111A, P / S unit 111B, FCS addition unit 111C, S / s unit 111D, and S / s unit 111D, which are shown in FIG. 26, respectively.
It corresponds to the port designation unit 111E and the selector (SEL) 111F and has the same function.

In FIG. 43, the routing circuit 140
The part that is connected to and transfers the frame is collectively referred to as the E system. The E system includes a control data line and various enable lines. These enable lines set necessary information in various registers 112A, the frame information of the control data line is transferred to the port to be transferred, which is specified by the port specifying register 112E, and is transmitted to each synthesis circuit connected to the port. Sent.

FIG. 44 shows an example of the configuration of the receiving section in the device monitoring control section, and illustrates the circuit block of the receiving section 122 in FIG. 122A-1 to 122A-1
122A-k is an S / s unit for the separating units 161-1 to 161-k, and 122B-1 to 122B-k are separating units 161.
FCS confirmation section for -1 to 161-k, 122C-1
-122C-k are S / P parts for the separation parts 161-1 to 161-k, and are S / s in FIG. 27, respectively.
Units 121A-0 and 121A-1, FCS confirmation unit 121B
-0,121B-1, S / P section 121C-0,121C
Same as -1. Also 122D, 122E, 122
F, 122G, 122H, 122I, and 122J are the duplication confirmation unit 121D and the selector (S
EL) 121E, reception control unit 121F, FIFO or buffer 121G, 121H, SEQ latch 121I,
This is similar to the multiple response table 121J.

Contrary to the transmitter 112, a plurality of separators 16 are provided.
When the frames from 1-1 to 161-k are received, the received frames are respectively multiplexed response table 122.
Written to J. The received fact is notified to the routing circuit 140 via the FIFO or buffers 122G and 122H for absorbing fluctuations.

FIG. 45 shows an example of the configuration of the separation unit, and illustrates the circuit block of the separation unit 161 in FIG. 41, where 161 is a separation unit for separating control data from target data, and 171 is It is a transmission / reception buffer. In the separation unit 161, 1611 is a delay circuit that delays input data, 1612 is a head detection control circuit that detects the head position of the input data and controls control data extraction, 161
Reference numeral 3 is a control frame generation unit that generates a control frame according to the detected head.

The head detection control circuit 1612 detects the head of the data on the target data line, and when the data on the target line passes through the delay circuit 1611 at the detection timing, recognizes the control portion in the data and extracts it. Then, the target control system data is fetched by enabling the entrance circuit of the control frame generation unit 1613. The control frame generation unit 1613 sends this data to the reception unit 1
Then, the data is reprocessed into a format recognizable in 22 and transmitted.

In the separating unit shown in FIG. 45, when the target data line 700 is used for synchronous transfer by a time slot, one of the time slots is reserved to secure it for the control system. If the target data line 700 has a frame structure, the frame structure according to the original data on the target data line,
It can be reserved for the control system by specializing the transfer code.

FIG. 46 is a diagram for explaining how to secure the control system on the target data line. (A) shows securing of the control system in the synchronization system, and when the time slot CH0 is the frame synchronization data and CH1 and the following are the original data, CHi
Is reserved for the control system. (B)
Indicates that the control system is secured by the frame synchronization method, and that the control system is secured by giving a control code or a special address in the address or control code portion.

FIG. 47 shows an example of the configuration of the synthesizing section, and illustrates the circuit block of the synthesizing section 162 in FIG. 41. 162 is a synthesizing section for synthesizing control data with target data, and 172 is It is a transmission / reception buffer. Synthesis part 1
In 62, 1621 is a timing adjustment circuit that adjusts the timing of input data, 1622 is a transfer transmission encoding unit that encodes the input data into a transfer transmission code, and 1622.
Reference numeral 23 is a control frame disassembly unit that disassembles the control frame
Reference numeral 624 denotes a control system control circuit for controlling the disassembly processing for the control frame according to the presence or absence of original data, and 1625.
Is a frame reorganization unit that reorganizes the control frame.

The synthesizing unit shown in FIG. 47 performs the reverse operation of the separating unit shown in FIG. 45, and the timing adjusting circuit 1 is applied to the original data from the functional module 150.
According to the data presence / absence notification from 621, the control system control circuit 1624 adjusts whether or not the original data exists, and the control frame disassembling unit 1623 disassembles the control frame from the transmitting unit 112 once and reorganizes the frame. Part 162
5, the frame is reorganized to form a format for the target data line, and the transfer transmission encoding unit 1622 encodes the transmission code for transfer and transmits it to the target data line 700.

The synthesizing section is a circuit block for synthesizing the control system data for the target data line on the same target data line while distinguishing it from the original data, and as shown in FIG. The implementation method differs depending on the format or the frame configuration. There is a method of realizing the time slot by a multiframe in time series regardless of the time slot method or the frame format.

FIG. 48 shows a configuration example of the routing circuit, which is the routing circuit 140 in FIG.
, A transmission wait buffer for temporarily holding data from the processor bus, a transmission port selection circuit for selecting a port to be transmitted, and a reference numeral 143.
Is a reception control circuit that controls reception in other functional parts,
Reference numeral 144 is a reception / readout control circuit for controlling the reading of reception information, 145 is a transfer destination table describing the transfer destination path of the transmission frame, and 146 is a detour table describing the detour transfer destination of the command frame.

The routing circuit 140 includes a control unit 130, a command analysis unit 270, and a registration command processing unit 280.
When sending or receiving a command frame from the device or sending or receiving a response frame, it is possible to avoid the route that is currently unavailable due to a failure and notify the target functional module of the required frame. It enables you to do it.

It is assumed that the plurality of transfer destinations and the routing information have been set in advance by the control circuit 130 or have fixed values. The transmission frame requested by the control unit 130 is temporarily transmitted to the transmission waiting buffer 14
No. 1 is stored, the transfer destination table 145 is searched by the ID of the function module that is the transfer destination, and the transfer destination path is selected. The transmission port selection circuit 142 selects a port that is currently available based on the selected information, whereby the transfer port of the transmission frame is determined and transmitted.

If the received frame is a command frame, the reception / readout control circuit 144 searches the function table ID of the transfer destination of the command frame by the detour table 146 and sends it to the transmission port selection circuit 142. By the notification, the received frame is transmitted through the port selected by the transmission port selection circuit 142. This operation is performed by the device monitoring controller 10
Functions other than 1 are realized only in the other functional modules 201 and 301.

According to this embodiment, the reliability of the duplicated control bus can be improved, and the transmission line forming the control bus can be made economical.

[0186]

As described above, according to the present invention, when one device monitoring control unit performs initialization and status monitoring, failure information collection, etc. by a command and response to a plurality of modules, , A control bus connecting the device monitoring control unit and the functional module when performing monitoring and control from the device monitoring control unit by two serial buses having a frame format and performing control to make the correct command or response normal Since the higher-order functional modules that are hierarchically connected and perform the subordinate connection relay the control bus to perform the function as the sub-control unit, the efficiency of the control bus can be improved. Also, in the event of an abnormality, by retrying the command and response with the lower-level functional module, the processing load on the device monitoring control unit is reduced, the reliability is improved, and the fatal level in the lower-level functional module is fatal. When an abnormality occurs,
The higher-level functional module adds a flag indicating this to the response to the device monitoring control unit and issues an emergency interrupt, whereby the processing speed can be increased.

[0187] Further, the device monitoring control section continuously sends commands to a plurality of functional modules without waiting for responses, and the functional modules give priority to relaying the responses of the downstream functional modules and sequentially respond. Thus, it is possible to shorten the waiting time for transmitting the command from the device monitoring control unit. At this time, according to the priority based on the command, or the predetermined sequence number and the priority based on the command,
Since the response from the functional module is made, the response of the functional module to the device monitoring controller can be flexibly made according to the priority.

Further, since the device monitoring controller and the upper functional module are connected by the serial bus, and the upper functional module converts the serial bus into the parallel bus and connects the lower functional module, the serial bus is connected. By simultaneously performing the conversion of the parallel bus and the parallel bus at one location and connecting the adjacent functional modules by the parallel bus, the device scale can be reduced.

Furthermore, the reliability of the control bus can be improved by providing the control bus between the device monitoring control section and the functional module as two separate routes. At this time, one of the control buses is a logical control bus provided in the data bus that achieves the original purpose of the device, and the data bus between the functional modules can be used to configure a bypass for the control bus. It is possible to improve reliability and reliability.

[Brief description of drawings]

FIG. 1 is a diagram showing a principle configuration of the present invention.

FIG. 2 is a diagram showing an example of the overall configuration of a system to which the present invention is applied.

3A and 3B are diagrams illustrating a control bus connection in an apparatus to which the present invention is applied, in which FIG. 3A shows a case of an individual bus type, and FIG. 3B shows a case of a common bus type.

FIG. 4 is a diagram showing a basic configuration example of the system of the present invention.

FIG. 5 is a diagram illustrating a processing procedure in the method of the present invention, in which (a) shows a setting processing procedure of initial setting information,
(B) shows a detection / notification processing procedure of operation / fault information.

FIG. 6 is a diagram showing an example of connection logic of a control bus in a specific system to which the system of the present invention is applied.

FIG. 7 is a diagram showing an example of entire functional blocks in a specific system to which the system of the present invention is applied.

FIG. 8 is a diagram showing a frame format (write) in the system of the present invention.

FIG. 9 is a diagram showing a frame format (read) in the system of the present invention.

FIG. 10: W in frame format (write)
FIG. 7 is a diagram showing details (bit assignment) of a command address.

FIG. 11: W in frame format (write)
-A diagram showing the details (bit assignment) of the command / control byte, (a) showing the bit assignment,
(B) shows the contents of the data byte number part.

FIG. 12: W in frame format (write)
-A diagram showing the details of the response status byte (bit assignment) and the details of the interrupt flag,
(A) shows allocation of each bit of the W-response,
(B) shows the details of the interrupt flags 1 and 0, and (c) shows the contents of the FCS error part.

FIG. 13: R in frame format (read)
FIG. 7 is a diagram showing details (bit assignment) of a command address.

FIG. 14: R in frame format (read)
-A diagram showing the details (bit assignment) of the command / control byte, (a) showing the bit assignment,
(B) shows the contents of the R-transfer byte number part.

FIG. 15: R in frame format (read)
-A diagram showing details of response status byte (bit assignment) and details of interrupt flag,
(A) is allocation of each bit of the R-response, (b)
Indicates details of the interrupt flags 1 and 0.

FIG. 16: R in frame format (read)
-Details (bit assignment) of the status byte of the response, where (a) shows the contents of the FCS error part and (b) shows the contents of the data byte number part.

FIG. 17 is a diagram showing a first embodiment of the present invention.

FIG. 18 is a diagram illustrating a configuration example of a command analysis unit.

FIG. 19 is a diagram illustrating a configuration example of a registration command processing unit.

FIG. 20 is a diagram showing an emergency abnormality notification system according to still another embodiment of the present invention.

FIG. 21 is a diagram showing an example of a processing flow of a control unit,
(A) shows an outline flow, (b) shows an operation processing flow.

FIG. 22 is a diagram illustrating a configuration example of a transmission unit in the device monitoring control unit.

FIG. 23 is a diagram illustrating a configuration example of a receiving unit in a functional module.

FIG. 24 is a diagram illustrating a configuration example of a transmission unit in a functional module.

FIG. 25 is a diagram showing a second embodiment of the present invention.

FIG. 26 is a diagram illustrating a configuration example of a transmission unit in the device monitoring control unit.

FIG. 27 is a diagram illustrating a configuration example of a receiving unit in the device monitoring control unit.

FIG. 28 is a diagram showing a processing flow (1) in the control unit.

FIG. 29 is a diagram showing a processing flow (2) in the control unit.

FIG. 30 is a diagram showing a processing flow (3) in the control unit.

FIG. 31 is a diagram illustrating a control method of timeout processing.

FIG. 32 is a diagram illustrating a format of a command and a response, showing an example at the time of writing, (a) shows a command, and (b) shows a response, respectively.

FIG. 33 is a diagram illustrating a configuration example of a reception unit in a functional module.

[Fig. 34] Fig. 34 is a diagram illustrating a configuration example of a transmission unit in a higher-level functional module.

[Fig. 35] Fig. 35 is a diagram illustrating a configuration example of a transmission unit in a lower-order functional module.

FIG. 36 is a diagram showing a schematic configuration of a third embodiment of the present invention.

FIG. 37 is a diagram showing a specific configuration of each part in the third embodiment.

FIG. 38 is a diagram showing a configuration example of a pseudo processor bus control unit.

FIG. 39 is a diagram illustrating a detailed configuration example of an internal functional block unit.

FIG. 40 is a diagram showing an overall configuration of a high reliability control bus according to a fourth embodiment of the present invention.

[Fig. 41] Fig. 41 is a diagram illustrating a configuration example of functional blocks in the device monitoring control unit.

FIG. 42 is a diagram showing an example of functional blocks in a functional module.

[Fig. 43] Fig. 43 is a diagram illustrating a configuration example of a transmission unit in the device monitoring control unit.

[Fig. 44] Fig. 44 is a diagram illustrating a configuration example of a reception unit in the device monitoring control unit.

FIG. 45 is a diagram illustrating a configuration example of a separation unit.

[Fig. 46] Fig. 46 is a diagram for explaining how to secure the control system on the target data line, in which (a) shows securing the control system in the synchronous system and (b) securing the control system in the frame synchronous system. Show.

[Fig. 47] Fig. 47 is a diagram illustrating a configuration example of a combining unit.

FIG. 48 is a diagram showing a configuration example of a routing circuit.

[Explanation of symbols]

1 Device monitoring control unit 2 ₁ Upper functional module 2 ₂ Lower functional module 3 ₁ Upper control bus 3 ₂ Lower control bus

Claims (10)

[Claims] 1. A plurality of functional modules and the plurality of functions
Device monitoring control for centralized monitoring and control of modules
And control unit via a redundant control bus.
Each functional module responds according to the command from the visual control unit.
In the system, the device monitoring control unit (1) and the upper functional module (2₁ )
And the upper control bus (3₁ Sending and receiving commands and responses via
And the upper functional module (2 ₁ ) Is before
Based on the command from the device monitoring control unit (1)
Jules (2₂) To the lower control bus (3₂ ) Through
Then, the upper functional module (2₁ ) Is registered in advance
Commands and responses are sent and received, and the responses are monitored by the device monitoring system.
A supervisory control method characterized by returning to the control section (1). 2. The upper functional module (2 ₁ ) is
When the response from the subordinate functional module (2 ₂ ) based on the instruction is abnormal, the subordinate functional module ( 2 ₂₎ and the monitor and control system according to claim 1, characterized in that a retry of the command and response exchanges with. 3. The upper functional module (2 ₁ ) is
When a fatal abnormality occurs in any one of the lower-order function modules (2 ₂ ), it has means for generating a flag for displaying it, and adds the flag to the response to the device monitoring control section (1). The supervisory control method according to claim 1, wherein an emergency interruption is performed by notifying. 4. A plurality of functional modules and an apparatus monitoring control unit for performing centralized monitoring / control of the plurality of functional modules are connected via a duplicated serial control bus,
In a system in which each functional module responds in response to a command from the device monitoring control unit, the device monitoring control unit (1) continuously sends commands to a plurality of functional modules in a command frame without waiting for a response, and A supervisory control method characterized in that each functional module preferentially relays the response from a more downstream functional module and then sends the response of its own module. 5. The supervisory control method according to claim 4, wherein priority information is added to the command from the device supervisory control unit (1) and is sent, and each functional module monitors the control bus. , A supervisory control method characterized in that a response is made after the response of a functional module having a higher priority is completed. 6. The supervisory control method according to claim 4, wherein priority information is added to the command from the device supervisory control unit (1) and is sent, and each functional module monitors the control bus. , A supervisory control method characterized in that responses are made in ascending order of a predetermined sequence number, and that functional modules with priorities give the highest priority response. 7. A plurality of functional modules and a device monitoring control unit for performing centralized monitoring and control of the plurality of functional modules are connected via a duplicated control bus, and respond to a command from the device monitoring control unit. In the system in which each functional module responds, the device monitoring controller (1) and the higher functional module (2 ₁ )
Are connected via an upper control bus (3 ₁ ) composed of a serial bus, and the upper functional module (2
₁ ) has means for converting an upper control bus into a parallel bus, and the parallel bus is used as a lower control bus, and the upper functional module (2 ₁ ) and the lower functional module (2 ₂ )
A supervisory control method characterized in that and are connected. 8. A plurality of functional modules and a device monitoring control unit for centrally monitoring and controlling the plurality of functional modules are connected via a duplicated control bus, and a command from the device monitoring control unit is received. In the system in which each functional module responds, the supervisory control method is characterized in that the duplicated control bus is composed of two transfer buses having different paths. 9. The two-system control buses are composed of a serial control transfer bus and a data transfer logic control bus that forms a logically identical control bus frame on the target data transfer bus. The monitoring control method according to claim 8. 10. The detouring means for arranging the serial control transfer bus and the data transfer logic control bus to be selectable, and diverting the data transfer bus between the functional modules as a data transfer logic control bus, 10. The supervisory control method according to claim 9, wherein when the serial control transfer bus fails, a bypass data transfer logic control bus is formed between the target modules via connectable function modules.