JPH05250317A - Data transfer system - Google Patents

Abstract

PURPOSE:To provide a data transfer system capable of constituting a shared bus in an information processing system at low cost with high reliability to a fault. CONSTITUTION:The shared bus of the information processing system is composed of signal lines 11 for which the kinds of sent signals are not determined fixedly. A packet consisting of a 9-bit set of specific word units is employed as the format of the transfer data. Then the respective word units are distributed and transferred to the respective signal lines 11 of the shared bus. The order SLB and MSB for distributing the word units to the signal lines of the common bus are predetermined. In a reception side, the data are reproduced by synchronizing the bits. Consequently, the need for a strobe signal indicating the arrival timing of the data is eliminated. When a signal line 38 being a part of the shared bus is in fault, N/2 signal lines except a predetermined division range including the fault signal line are used as a new common bus to carry on the data transfer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system in which a shared bus in an information processing system has improved reliability against failure without increasing cost.

[0002]

2. Description of the Related Art FIG. 7 is a diagram showing an outline of an information processing system. In FIG. 7, 40 is a system management device, 4
1 is a shared bus, 42 is a CPU (central processing unit), 4
3 is a DMA controller (DMA: Direct Memory Access), 44 is a memory, 45 is a file controller, 4
Reference numeral 6 is an I / O control device.

Data transfer in such an information processing system is carried out via a shared bus 41, but the conventional shared bus 41 comprises a data bus, an address bus and a control bus as shown in FIG. Has been done. Each bus consists of several signal lines 11.

In the conventional shared bus 41, what kind of signal should be sent to each of the signal lines forming the fixed bus 41 is fixedly determined. For example, an address strobe signal is sent to the address strobe line in the control bus and an acknowledge signal is sent to the acknowledge line. And, it was not allowed to flow except for the signals so defined.

FIG. 9 is a diagram for explaining the strobe signal. (A) shows the data appearing on the data line,
(B) indicates a strobe signal. The strobe signal is the signal output on the data line when it is output.
Indicates that the data is truly valid. Conventional shared bus 4
When data is transferred by 1, the signal currently output on the data line must be a valid true data when sending data in order to explicitly indicate that the desired data has been output on multiple data lines. A strobe signal is required to signal that.

[0006]

[Problems to be Solved by the Invention]

(Problem) However, in the above-described conventional data transfer method performed via the shared bus, even if a failure occurs in any of the signal lines, the same operation is required to continue normal operation. Since it is necessary to provide dual shared buses, the cost is high and the device is large.

(Explanation of Problems) In the conventional shared bus, it is defined what kind of signal is to be sent to each signal line. Therefore, if one signal line fails, the other signal line. Can not be replaced by. Therefore, the whole operation has to be stopped. In order to improve the reliability of the operation, even if a failure occurs in any of the signal lines, another shared bus of exactly the same configuration is prepared as a standby system so that the operation can be continued. It was necessary to switch to the standby system as soon as a failure occurred.

However, preparing a spare system having exactly the same configuration in preparation for a failure that rarely occurs causes an increase in cost and also makes the apparatus large. Therefore, it cannot be practically introduced, except for systems that require particularly high reliability, such as bank online systems and air traffic control systems. An object of the present invention is to solve such a problem.

[0009]

In order to solve the above problems, the data transfer system of the present invention comprises a shared bus to which a plurality of devices for exchanging data are connected, and transfer data in predetermined word units. The packet is made up of a set, the shared bus is configured as a bus made up of a plurality of signal lines in which the order of distributing the word units is determined, and data is reproduced on the receiving side in bit synchronization.

Further, in the data transfer system of the preceding paragraph, when a part of the signal lines forming the shared bus fails, a part of the signal line excluding a predetermined division range including the failed signal line is newly shared. Continue the transfer as a bus.

[0011]

[Operation] Configure the shared bus in the information processing system with signal lines for which the types of signals to be sent are not fixed. On the other hand, the format of the transfer data is set to a predetermined word unit (eg,
(9 bits width). And
Each word unit is distributed to each signal line of the shared bus and transferred.
The order in which word units are distributed to the signal lines of the shared bus is predetermined. On the receiving side, data is reproduced with bit synchronization. As a result, it becomes possible to receive data without the need for a strobe signal indicating the arrival timing of data.

Further, when a part of the signal lines of the shared bus fails, the part of the signal lines excluding a predetermined division range including the failed signal line is used as a new shared bus,
Data is transferred using the same protocol as before. This makes it possible to continue data transfer in the event of a failure even if two shared buses having exactly the same configuration are not provided.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a diagram showing a bus structure in the present invention. The shared bus is composed of N signal lines 11, but what kind of signal is sent to which signal line?
Its role is not fixed. From the signal line corresponding to bit 0 to the signal line corresponding to bit N-1, the types of signals to be sent are equal.

All that is specified is the ordering of which signal line of the shared bus to use when transferring data. The signal line on the side to start using is LSB
(Least Significant Bit) and the signal line on the opposite side is MSB (Most Significant Bit). In the example of FIG. 1, since the signal line 11 corresponding to bit 0 is the LSB, a required number of signal lines from this side are used to perform data transfer (the situation will be described later in detail with reference to FIG. 4). ).

The shared bus of the present invention transfers data in the form of packets of variable length. As the protocol (communication procedure) on the shared bus, a well-known protocol suitable for exchanging packets is adopted. One of the features of the present invention is that data is transferred on a shared bus in one information processing system by a method similar to packet communication.

FIG. 2 is a diagram for explaining how to use the shared bus when a failure occurs. The reference numerals correspond to those in FIG. FIG. 2A shows N (64 in this case) signal lines 1
In the shared bus consisting of 1, the signal line 11 corresponding to the bit 38 has failed. In such a case, as shown in FIG. 2B, the shared bus is divided into, for example, halves, and only the half (bit 0 to bit 31) that does not include the failed signal line 11 is used to determine that before the failure. Data transfer is performed using the same protocol (reduced operation in halves).
In that case, the LSB and MSB are also ordered.

When a failure occurs during the degenerate operation in the 1/2 division, the degenerate operation is further performed. For example, in FIG.
When the signal line corresponding to bit 25 fails in (b), the degenerate bus operation is divided into halves, and the other half (bit 0 to bit 15) that does not include the fault signal line is divided. Data transfer is performed using the same protocol as before the failure by using half of N / 4). FIG. 2C shows it.

FIG. 4 is a diagram showing a transfer state when there is no failure in the bus. Here, a shared bus composed of 64 signal lines 11 corresponding to bits 0 to 63 is taken as an example. In FIG. 4, 12,
13 is a header, 14, 15 and 16 are packet length identifiers,
Reference numerals 17, 18, and 19 are C / D identifiers, 20, 21 and 22 are signal content portions, 23 and 24 are end marks, and 25 and 26 are continuation marks.

Data transfer is performed by forming data in the form of packets of variable length. The packet sent during one cycle in the figure will be described. The header 12 represents the beginning of the packet and the end mark 23 represents the end of the packet. The packet length identifier 14 represents the length of the packet (from the header 12 to the end mark 23). The C / D identifier 17 represents whether the content of the signal content section 20 is a control signal (Control) or data (Data). The signal content section 20 stores the data or address to be transferred.

The unit of the word sent to each signal line 11 is, for example, as shown in FIG. 6, a width of 9 bits obtained by adding 1 bit of parity bit to 8 bits of data bit. Therefore, for example, the header 12 which is one word unit is also composed of 9 bits. Variable-length packets are packed and used from the LSB side of the signal line 11 of the shared bus and used.
In FIG. 4, the length of the packet handled in the first cycle transaction (one transfer process) is relatively short, and can be sent by using the signal line 11 corresponding to the bit 30. Therefore, the feeding to the end mark 23 can be completed within one cycle.

However, the packets handled in the transactions from the second cycle are long, and the 6
It cannot be sent even if all four signal lines 11 are used. In such a case, the last 64th signal line 1
At 1, the continuation mark 25 is sent and the cycle is finished.
Then, the remaining data is sent in the next cycle. Next 3
In the second cycle, the continuation mark 26 is sent by the signal line 11 of the LSB bit 0 to clarify that it is a continuation of the previous cycle, and the packet length identifier 1
6. Send C / D identifier 19 and signal content section 22.

FIG. 5 is a diagram showing a transfer state when a bus failure occurs and the bus width is halved for operation. For example,
When a failure occurs in the signal line 11 corresponding to the bit 38 in FIG. 4, the shared bus is divided into halves, and only the half (that is, 32 signal lines corresponding to bits 0 to 31) that does not include the failure signal line. To continue the transfer (Fig. 2 (b))
reference). The operation of reducing the bus width in this way is called degenerate operation. This is shown in FIG. The reference numerals correspond to those in FIG. 4, and 27 to 30 are continuation marks.

The transaction of the first cycle has a short packet length and can be transferred if there are 31 signal lines. Therefore, the transaction is completed in one cycle. The transaction starting from the second cycle has a long packet length, and can be completed until the fourth cycle. A continuation mark is sent each time the cycle is changed to clarify that the data is continuous.

As shown in FIG. 7, the information processing system is equipped with a system management device 40.
FIG. 1 is a diagram showing an example of a system management device in an information processing system to which the present invention is applied. In FIG. 3, 1 is an error recording register, 2 is a bus operation control unit, 3 is a reset switch, 4 is a parity check circuit, 5 is a bit synchronization circuit, 6 is a data buffer, 7 is an operation status register, and 8 is degenerate operation. An instruction packet sending unit, 9 is a changeover switch unit, and 10 is an instruction signal buffer.

The role of the system management device 40 is to inspect whether a failure has occurred in the shared bus 41 and, when a failure has occurred, to instruct whether to operate the shared bus 41 by using its soundness or the like. Is. Therefore, shared bus 4
First, data is taken into the data buffer 6 from each signal line constituting 1 and bit synchronization is performed by the bit synchronization circuit 5 in word units (words consist of, for example, 9 bits).

As the bit synchronization mechanism, a known one can be adopted (as literatures on bit synchronization, for example, Japanese Patent Laid-Open Nos. 1-307335 and 2-30256).
Issue publication). Since the bit synchronization is performed and the data is reproduced according to the position occupied in the word frame, the strobe signal required in the conventional shared bus in which the type of signal to be sent to each signal line is fixed is It becomes useless.

The parity check circuit 4 performs a known parity check on the reproduced data to check whether there is an error. The error is recorded in the error recording register 1. If an error occurs even once, it can be judged as a failure immediately, but since an error may occur accidentally due to external noise, etc., the same signal should be used in order not to be confused by such an error. The failure can be determined only when the error is recorded on the line more than the specified number of times.

When the bus operation control unit 2 is notified of a failure,
The bus operation control unit 2 updates the information in the operation status register 7 and also provides the degeneration operation instruction packet sending unit 8 with information for dividing the shared bus 41. The operation status register 7 holds information about which block of the shared bus 41 is currently in failure, and when a new failure occurs, the information is updated in such a manner that the failure is also added. .. The bus operation control unit 2 uses the operation status register 7
Based on the failure information obtained from the above, it is determined whether the signal lines of the divided blocks can be used to normally continue the data transfer, and the degenerate operation instruction packet sending unit 8
Give instructions to.

The degenerate operation instruction packet transmitting unit 8 sends a control packet instructing usable blocks to the shared bus 41.
To send to. The control packet is transmitted by, for example, selecting the instruction signal buffer 10 corresponding to the usable block by the changeover switch unit 9 and transmitting it to the signal line of the usable block through it.

All the devices connected to the shared bus 41 (CPU 42, DMA control device 43, etc. in FIG. 7) receive this control packet at the same time, and the subsequent data transfer is
It is performed using a newly defined block (degenerate operation). The reset switch 3 is a switch that is pressed when the failure of the shared bus 41 is recovered. When the reset switch 3 is pressed, the record of the failure is erased.

In the above example, the division in the degenerate operation is divided into ½, but it may be ⅓ or ⅕. It goes without saying that the data width in word units and the bus width of the shared bus can be various widths.

In the above example, the degenerate operation performed by dividing the shared bus is performed at the time of failure, but it can also be performed at the time of normal operation. That is, it is a method of using a shared bus having no failure by dividing it into a plurality (eg, two) and using each of the divided shared buses as an independent shared bus. In this case, the information processing system has scalability.
Can have

[0033]

As described above, according to the data transfer system of the present invention, one word unit of packetized data is allocated and transferred without particularly defining the type of signal to be sent to each signal line of the shared bus. Therefore, even if a part of the signal line of the shared bus fails, the signal line of the part excluding the predetermined division range including the failed signal line is used as a new shared bus and the data transfer is continued by the same protocol. I can do it now. Therefore, without taking measures to increase the size and cost of equipping the exact same shared bus as a standby system,
It is possible to obtain a data transfer method with great fault tolerance (fault tolerant).

Further, since the data is reproduced on the receiving side by bit-synchronizing in word units, the strobe signal which is required when data is transferred by the conventional shared bus becomes unnecessary.

Further, even if the signal line of the shared bus is not broken down, it is possible to realize a plurality of independent shared buses in the existing shared bus by dividing and operating in a degenerate manner.

[Brief description of drawings]

FIG. 1 is a diagram showing a bus structure in the present invention.

FIG. 2 is a diagram explaining how to use the shared bus in the event of a failure.

FIG. 3 is a diagram showing an example of a system management device used in the data transfer system of the present invention.

FIG. 4 is a diagram showing a transfer state when there is no failure in the bus.

FIG. 5 is a diagram showing a transfer state when a bus failure occurs and the bus width is halved.

FIG. 6 is a diagram showing an example of the data width.

FIG. 7 is a diagram showing an outline of an information processing system.

FIG. 8 is a diagram showing a configuration of a shared bus.

FIG. 9 is a diagram illustrating a strobe signal.

[Explanation of symbols]

1 ... Error recording register, 2 ... Bus operation control unit, 3 ... Reset switch, 4 ... Parity check circuit, 5 ... Bit synchronization circuit, 6 ... Data buffer, 7 ... Operation status register, 8 ... Degenerate operation instruction packet sending unit , 9 ... Changeover switch section, 10 ... Instruction signal buffer, 11 ... Signal line, 1
2, 13 ... Header, 14, 15, 16 ... Packet length identifier, 17, 18, 19 ... C / D identifier, 20, 21, 2
2 ... Signal content part, 23, 24 ... End mark, 25-30
... Continuation mark, 40 ... System management device, 41 ... Shared bus, 42 ... CPU, 43 ... DMA control device, 44 ... Memory, 45 ... File control device, 46 ... I / O control device

Claims (2)

[Claims] 1. A shared bus to which a plurality of devices for exchanging data are connected, the data to be transferred is a packet made up of a set of predetermined word units, and the configuration of the shared bus is the order in which the word units are distributed. A data transfer system characterized by a bus consisting of a plurality of signal lines that are specified in the above and reproducing data by bit synchronization on the receiving side. 2. When a part of the signal lines forming the shared bus fails, a part of the signal line excluding a predetermined division range including the failed signal line is used as a new shared bus. The data transfer method according to claim 1.