JPH05250308A - Arbitration system of electronic computer - Google Patents

Abstract

PURPOSE:To improve the throughput of a central processing unit in the same unit processing unit by optimizing the timing of the output of a use right request by a DMA controller. CONSTITUTION:There are a latent access request EC and a main access request ED as an access request that the DMA controller 412 outputs. The request timing adjustment part 412a of the DMA controller 412 determines the output timing of the access request. Namely, the request timing adjustment part 412a determines rough output timing according to predicted wait time information EJ until an access permission EI is given to a unit processing unit 41 and detects which stage of pipeline processing the central processing unit 411 currently performs from pipeline operation information (meaning a storage device reference schedule) from the central processing unit 411 to determine timing where there is no conflict with an access request EA from the central processing unit 411.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a central processing unit and DM.
The present invention relates to an arbitration method of an electronic computer when a unit processing device including an A controller acquires a right to use a storage device or a bus common to a plurality of devices.

[0002]

2. Description of the Related Art In an electronic computer, in order to reduce the load on a central processing unit, a DMA controller is independently used in parallel with the central processing unit to control data transfer using one storage device.

Along with the improvement in the degree of integration of semiconductor elements, it has been practiced to mount a DMA controller on the same chip as the central processing unit to form a unit processing unit. In addition, there is a computer in which a plurality of unit processing devices are used in order to increase the speed. In this case, it is necessary to arbitrate the right to use the common storage device or the common bus between the unit processing devices, and the right to use the common storage device or the common bus between the central processing unit and the DMA controller in the unit processing device. Need to arbitrate. By the internal arbitration, the operation information of the central processing unit can be recognized by the DMA controller constituting the same unit processing unit without delay, and the DMA controller can refer to the storage device in a cycle in which the central processing unit does not refer to the main storage device. The above-described configuration has already been realized in an electronic computer having a short mechanical cycle time.

FIG. 2 is a block diagram showing an example of the configuration of such a conventional electronic computer. In this prior art example, arbitration for the common storage device is performed.

In FIG. 2, this electronic computer comprises a plurality of unit processing devices (only one is shown in FIG. 2) 11,
Inter-unit processing device arbitration mechanism 21 and a plurality of unit processing devices 1
1 and a storage device 31 common to all storage devices 1, and any of the unit processing devices to which the arbitration mechanism 21 gives access permission can access the storage device 31 via the common bus G.

Each unit processing unit 11 is a central processing unit 11
1, a storage device 31, and an input / output port (or a local memory, not shown) (not shown) inside the unit processing device 11
DMA controller 112 that independently controls the data transfer to and from the central processing unit 111, and internal arbitration that arbitrates access to the storage unit 31 between the central processing unit 111 and the DMA controller 112 inside the unit processing unit 11. And the mechanism 113.

After the central processing unit 111 requests the DMA controller 112 for data transfer, the central processing unit 111 can perform the following processing, and in this processing, it may be necessary to access the storage device 31. Therefore, access requests may conflict with each other, and thus internal arbitration is necessary.

Next, the arbitration operation in the conventional electronic computer will be described.

The central processing unit 111 gives an access request A to the internal arbitration mechanism 113 when the storage device 31 needs to be accessed, and the DMA controller 112 also has an internal arbitration mechanism 113 when the storage device 31 needs to be accessed.
Access request D to DMA controller 112
Can access the storage device 31 independently of the central processing unit 111, so that these access requests A and D may conflict as described above.

The internal arbitration mechanism 113 includes the central processing unit 11
1 is the logical sum of the access request A from the DMA controller 112 and the access request D from the DMA controller 112.
Access request H is given to the arbitration mechanism 21.

The arbitration mechanism 21 includes a plurality of unit processing devices 11
A unit processing device that can be accessed is determined based on the access request H from the access request H, and an access permission I is given to the determined unit processing device.

The internal arbitration mechanism 113 in the unit processing unit 11 to which the access permission I is given determines which of the central processing unit 111 and the DMA controller 112 is to be referred to (for example, according to the request generation order). The access permission B or E is given to the determined central processing unit 111 or DMA controller 112. Central processing unit 111 or DMA controller 11 that has received access permission B or E
2 accesses the storage device 31 via the bus G.

[0013]

However, in the conventional electronic computer, arbitration is performed by the inter-unit processing device arbitration mechanism 21 and the internal arbitration mechanism 113.
Time (number of cycles) required for each central processing unit 111 to obtain access permission for the storage device 31 (or bus G)
Is indefinite. In an electronic computer in which the number of cycles required to access the storage device 31 is indefinite,
The access timing by the central processing unit 111 cannot be managed by the number of cycles, and the central processing unit 1 can be operated until the access of the storage device 31 by the DMA controller 112 is completed.
There is a drawback in that the access start of the storage device 31 by 11 is suspended and the processing capacity of the central processing unit 111 is reduced. For example, in the case of an electronic computer that causes a plurality of unit processing devices 11 to divide the processing into equal parts, this drawback also causes a drawback that the processing capacity of the entire electronic computer is reduced.

Therefore, although it is conceivable to increase the priority of the access request of the central processing unit 111, in cooperation with the arbitration between the unit processing units 11, the DMA controller 11
Since the control operation according to 2 is hardly executed, the above drawbacks are not always solved.

The present invention has been made in consideration of the above points, and it is an object of the present invention to provide an arbitration system for an electronic computer which can improve the processing capacity of a central processing unit despite the existence of a DMA controller. is there.

[0016]

In order to solve such a problem, according to the present invention, a central processing unit, a DMA controller, and an arbitration of a right to use a common storage device or a common bus between the central processing unit and the DMA controller. Inter-device arbitration for arbitrating the right to use a common storage device or a common bus among a plurality of devices including one or more unit processing devices The arbitration method of an electronic computer with a mechanism,
I did the following:

In other words, the inter-device arbitration mechanism calculates the predicted waiting time until the usage right is granted for the unit processing device which has not issued the usage right permission and has sent the usage right request, and calculates the internal DMA of the unit processing device. The predicted waiting time information is given to the controller, and the DMA controller of the unit processing device to which the predicted waiting time information is given takes precedence over the usage right request from the central processing unit at a timing determined based on this predicted waiting time information. It was decided to give the right of use request to the internal arbitration mechanism.

Here, when the DMA controller tries to request the usage right, it outputs a potential usage right request having a lower priority than the usage right request from the central processing unit to the internal arbitration mechanism so that the device-to-device It is preferable that the arbitration mechanism outputs the predicted waiting time information or the usage right permission.

Further, the central processing unit gives pipeline operation information to the DMA controller, and the DMA controller gives priority to the usage right request from the central processing unit at a timing determined based on the predicted waiting time information and the pipeline operation information. It is preferable to give the usage right request to the internal arbitration mechanism.

Further, when the amount of data per unit time that the DMA controller has controlled to transfer before that time point is smaller than a predetermined value, the right-of-use request and the priority order from the central processing unit are adjusted without timing adjustment. It is preferable to provide the same or higher usage right request to the internal arbitration mechanism.

[0021]

The present invention is intended to improve the processing capability of the central processing unit in the same unit processing device by optimizing the timing at which the DMA controller outputs the usage right request. In order to determine this timing, the inter-device arbitration mechanism calculates the predicted waiting time until the usage permission is given for the unit processing device that has not issued the usage right permission and has sent the usage right request, and calculates the internal waiting time. The expected latency information to the DMA controller of. Then, the DMA controller, to which the predicted waiting time information is given, determines the output timing based on the predicted waiting time information, and gives the internal arbitration mechanism a usage right request prioritizing the usage right request from the central processing unit.

Here, in order to improve the accuracy of the predicted waiting time information and to fetch the predicted waiting time information at the time when the DMA controller needs it, when the DMA controller tries to request the usage right, It is preferable that a potential right-of-use request having a lower priority than the right-of-use request from the central processing unit is output to the internal arbitration mechanism and the predicted waiting time information or the right-of-use permission is output from the inter-device arbitration mechanism.

When a central processing unit which can perform pipeline processing and output pipeline operation information to the outside is applied, the central processing unit gives the pipeline operation information to the DMA controller, and the DMA controller To optimize the output timing by giving the internal arbitration mechanism a right to use request that has priority over the right to use request from the central processing unit at the timing determined based on the predicted waiting time information and the pipeline operation information. Is preferred.

Further, when the amount of data per unit time that the DMA controller has controlled the transfer before that time is smaller than a predetermined value, the request for the right to use and the priority order from the central processing unit are adjusted without timing adjustment. It is preferable that the same or higher usage right request be given to the internal arbitration mechanism, and when the influence on the processing capacity of the central processing unit is small, the arbitration control is simplified as in the conventional case.

[0025]

【Example】

(A) First Embodiment Hereinafter, a first embodiment according to the present invention will be described in detail with reference to the drawings. Here, FIG. 1 is a block diagram showing the configuration of the first embodiment.

In FIG. 1, the electronic computer of this embodiment also includes a plurality of unit processing devices (only one is shown in FIG. 1) 41, a unit processing device arbitration mechanism 51, and a common storage device 61. It is configured so that any of the unit processing devices to which the arbitration mechanism 51 gives access permission can access the storage device 61 via the common bus G1. The arbitration mechanism 51 of this embodiment incorporates an expected waiting time calculation unit 51a described later.

Each unit processing unit 41 is a central processing unit 41.
1 and a DMA controller 412 that controls data transfer between the storage device 61 and an input / output port (or a local memory (not shown)) inside the unit processing device 41 independently in parallel with the central processing device 411. It is composed of a central processing unit 411 inside the unit processing unit 41 and an internal arbitration mechanism 413 which arbitrates access competition of the storage unit 61 with the DMA controller 412. The DMA controller 412 has a request timing determination unit 412a built therein.

The central processing unit 411 issues an access request EA to the internal arbitration mechanism 413 when the storage device 61 needs to be accessed, and when the access permission EB is returned from the internal arbitration mechanism 413, the storage device 61 is returned. Access to. In the case of this embodiment, the central processing unit 411 is the DMA controller 4
12 is provided with pipeline operation information EF.
The pipeline operation information EF is used to determine the timing at which the DMA controller 412 outputs the access request ED, as described later. Although not directly related to the arbitration process, the central processing unit 411 requests the DMA controller 412 to control the data transfer between the storage device 61 and an input / output port (not shown) as necessary.

The DMA controller 412 has been requested by the central processing unit 411 to control data transfer.
When a request is made from an input / output port (not shown), the storage device 61 is accessed, and when the storage device 61 is accessed, an access request (E
C or ED) is given to the internal arbitration mechanism 413. The DMA controller 412 actually accesses the storage device 61 when the access permission EE is returned from the internal arbitration mechanism 413.

In the case of this embodiment, the access requests output from the DMA controller 412 include a latent access request EC and a main access request (hereinafter, simply referred to as an access request) ED. The latent access request EC is output immediately when the DMA controller 412 tries to access the storage device 61 without considering the occurrence of an access request to the central processing unit 411 or another unit processing device. On the other hand, access request ED
Is for estimating and outputting how to generate an access request from the central processing unit 411 or another unit processing unit. That is, the output timing of the access request ED is determined at the timing when the probability of hindering the processing by the central processing unit 411 is low.

The above-mentioned request timing determination unit 412a
Determines the output timing of this access request ED. The request timing determination unit 412a determines the approximate output timing based on the predicted waiting time information EJ given from the arbitration mechanism 51 until the arbitration mechanism 51 gives the access permission EI to the unit processing device 41, and the central processing. An access request EA from the central processing unit 411 is detected by detecting at which stage of the pipeline processing the central processing unit 411 is executing, based on pipeline operation information (meaning a storage device reference schedule) EF from the apparatus 411. Determine the timing that will not conflict with.

The potential access request EC is also output to obtain the predicted waiting time information EJ (in some cases, an access permission EI may be given instead of it), and therefore, the access request ED is preceded. Will be output.

The internal arbitration mechanism 413 is the central processing unit 41.
When the access request EA is given from 1, and / or
When the latent access request EC or the access request ED is given from the DMA controller 412, the access request EH is given to the upper arbitration mechanism 51.
Further, the internal arbitration mechanism 413, when the access permission EI is given from the arbitration mechanism 51, the access permission EB or E to the central processing unit 411 or the DMA controller 412.
It gives E.

In the case of this embodiment, the DMA controller 4
The access request ED from the central processing unit 411 is prioritized over the access request EA from the central processing unit 411, and the access request EA from the central processing unit 411 is prioritized over the potential access request EC from the DMA controller 412. Therefore, the internal arbitration mechanism 413 controls the central processing unit 4
Whether the access permission EB is given to 11 or the access permission EE is given to the DMA controller 412 is determined as shown in FIG. 3 and the following.

(1) When only the access request EA is given, the access permission EB is given to the central processing unit 411. (2) When only the latent access request EC is given, the access permission EE is given to the DMA controller 412. (3) When both the access request EA and the potential access request EC are given, first the access permission EB is given to the central processing unit 411, and then the DMA controller 41 is given.
2 gives access permission EE. (4) If only the access request ED is given,
The access permission EE is given to the DMA controller 412. (5) When both the access request EA and the access request ED are given, first, the DMA controller 412
The access permission EE is given to the central processing unit 411, and then the access permission EB is given to the central processing unit 411.

The arbitration mechanism 51 includes a plurality of unit processing devices 41.
In response to the access request EH from the internal arbitration mechanism 413, for example, one of the unit processing devices is determined according to the round robin method and the access permission EI is returned. For the unit processing device 11 which does not return the access permission EI, the expected waiting time information J is given to the DMA controller 412. In the case of this embodiment, the arbitration mechanism 51 outputs the access request EH and does not give the access permission EI to the DMA controller 412 of the unit processing device 11 only.
give.

Here, the expected waiting time is calculated by the built-in expected waiting time calculating section 51a as follows, for example. It is assumed that the arbitration mechanism 51 determines the access order of the plurality of unit processing devices based on an algorithm such as round robin. It is assumed that a certain unit processing device is determined to be nth at that time. The expected waiting time EJ of the unit processing device is obtained by multiplying the cycle time of the storage device 61 by this n.

Next, the arbitration processing of the electronic computer having the above-mentioned configuration will be described by dividing it into cases based on how access requests are issued.

(1) It is assumed that only the central processing unit 411 outputs the access request EA. In this case, the internal arbitration mechanism 41
3 gives the access request EH to the arbitration mechanism 51. The arbitration mechanism 51 determines an accessible unit processing device based on the access requests EH from the plurality of unit processing devices 41, and gives an access permission EI to the determined unit processing device.
The predicted waiting time information EJ is given to another unit processing device.

The determined internal arbitration mechanism 413 in the unit processing unit 41 allows the central processing unit 411 to access the EB.
give. As a result, the central processing unit 411 causes the bus G1
The storage device 61 is accessed via.

Incidentally, when the central processing unit 411 outputs the access request EA, the DMA controller 412
It recognizes the pipeline operation information EF from the central processing unit 411 and waits for the output of the potential access request EC or the access request ED even when it is desired to access.

(2) It is assumed that only the DMA controller 412 outputs the latent access request EC. Also in this case, the internal arbitration mechanism 413 gives the access request EH to the arbitration mechanism 51. The arbitration mechanism 51 determines a unit processing device that can be accessed based on access requests EH from the plurality of unit processing devices 41, and grants access permission E to the determined unit processing device.
I is given and the predicted waiting time information EJ is given to another unit processing device.

The determined internal arbitration mechanism 413 in the unit processing device 41 gives an access permission EE to the DMA controller 412. As a result, the DMA controller 41
2 accesses the storage device 61 via the bus G1.

On the other hand, D receiving the predicted waiting time information EJ
The MA controller 412 uses the predicted waiting time information EJ.
And pipeline operation information E from the central processing unit 411
Based on F, a timing at which the probability of hindering the processing of the central processing unit 411 is low is determined, and the potential access request EC is switched to the access request ED at that time.

(3) Central processing unit 411 requests access E
It is assumed that the time when A is output and the time when the DMA controller 412 outputs the potential access request EC are almost the same.
Also in this case, the internal arbitration mechanism 413 gives the access request EH to the arbitration mechanism 51. The arbitration mechanism 51 determines an accessible unit processing device based on the access requests EH from the plurality of unit processing devices 41, gives an access permission EI to the determined unit processing device, and waits for prediction to another unit processing device. Give time information EJ.

The internal arbitration mechanism 413 in the unit processing unit 41 thus determined first gives the central processing unit 411 an access permission EB. As a result, the central processing unit 411 accesses the storage device 61 via the bus G1. When this access ends, the access permission EI from the arbitration mechanism 51 disappears. At this time, the operation in the case of (2) above is performed.

There is also an electronic computer having a configuration in which the access permission EI from the arbitration mechanism 51 to the unit processing device 41 continues even when the access to the storage device 61 by the central processing unit 411 ends (however, the access permission is permitted). E
I is lost in many electronic computers). In such an electronic computer, the internal arbitration mechanism 413, when the access request EA disappears due to the completion of the access of the central processing unit 411, the access permission E to the DMA controller 412.
Give E.

On the other hand, D receiving the predicted waiting time information EJ
The MA controller 412 uses the predicted waiting time information EJ.
And pipeline operation information E from the central processing unit 411
Based on F, a timing at which the probability of inhibiting the processing of the central processing unit 411 is extremely low is determined, and the potential access request EC is switched to the access request ED at that time. In this case, since it is understood that the central processing unit 411 is outputting the access request EA from the pipeline operation information EF, the switching time is set to the time at which the access processing by the central processing unit 411 is estimated to be completed. ..

(4) It is assumed that only the DMA controller 412 outputs the access request ED. This happens after the processing in case (2) above. Also in this case, the internal arbitration mechanism 413 gives the access request EH to the arbitration mechanism 51. The arbitration mechanism 51 determines a unit processing device that can be accessed based on the access requests EH from the plurality of unit processing devices 41, and grants access permission EI to the determined unit processing device.
And the estimated waiting time information EJ to other unit processing devices.

The determined internal arbitration mechanism 413 in the unit processing device 41 gives an access permission EE to the DMA controller 412. As a result, the DMA controller 41
2 accesses the storage device 61 via the bus G1.

On the other hand, D receiving the predicted waiting time information EJ
The MA controller 412 continues the access request ED. At this time, since the timing adjustment is being performed, access permission E to the unit processing device 41 will be issued soon.
I is given.

(5) The central processing unit 411 requests access E
It is assumed that the time when A is output and the time when the DMA controller 412 outputs the access request ED are almost the same. It is considered that such a thing hardly occurs because the request timing adjusting unit 412a adjusts the output timing of the access request ED, but it may occur. Also in this case, the internal arbitration mechanism 413 gives the access request EH to the arbitration mechanism 51. The arbitration mechanism 51 determines an accessible unit processing device based on the access requests EH from the plurality of unit processing devices 41, gives an access permission EI to the determined unit processing device, and waits for prediction to another unit processing device. Give time information EJ.

The determined internal arbitration mechanism 413 in the unit processing device 41 first gives an access permission EE to the DMA controller 412. As a result, the DMA controller 412 accesses the storage device 61 via the bus G1. When this access ends, the access permission EI from the arbitration mechanism 51 disappears. At this time,
It becomes the operation in case of (1).

On the other hand, D which has received the estimated waiting time information EJ
The MA controller 412 continues the access request ED. Even at this time, since the timing adjustment is performed, the access permission E to the unit processing device 41 will be issued soon.
I is given.

Therefore, according to the first embodiment described above, D
The probability that the MA controller 412 inhibits the operation of the central processing unit 411 is reduced, and the central processing unit 411 can operate efficiently.

As a result, even when a plurality of unit processing devices 41 perform distributed processing, the processing capacity of the entire electronic computer can be improved.

(B) Second Embodiment Next, a second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 4 shows the configuration of the electronic computer according to the second embodiment, and the same or corresponding parts as in FIG. 1 are designated by the same reference numerals.

As is apparent from FIG. 4, in the second embodiment, the DMA controller 412 is provided with the transfer capability monitoring unit 4.
12b is provided, and the DMA controller 412 controls the generation of an access request based on the monitoring result of the transfer capability monitoring unit 412b, which is different from the first embodiment.

The transfer capability monitor 412b monitors the transfer operation information EK of the DMA controller 412. Based on the transfer operation information EK, the transfer capability monitoring unit 412b determines whether or not the data transfer amount per unit time (that is, the transfer speed) up to immediately before is lower than a predetermined threshold value. If it is determined to be low, the operation mode instruction EL is generated.

When the DMA controller 412 attempts to access the storage device 61 during the period when the operation mode instruction EL is generated, the expected waiting time information EJ given from the arbitration mechanism 51 and the central processing unit 411. An access request EA from the central processing unit 411 similar to the conventional one, regardless of the pipeline operation information EF, and without generating the potential access request EC or the access request ED.
The access request EM having the same priority as that of the internal arbitration mechanism 413
Output to.

In this way, when the data transfer amount per unit time by the DMA controller 412 is small, the central processing unit 411 is affected by the access permission even if the DMA controller 412 is granted access. This is because there is almost no

Therefore, according to the second embodiment as well, the first
The same effect as that of the embodiment can be obtained, and the DMA
The effect that the transfer is often executed smoothly is obtained.

(C) Other Embodiments In the above embodiment, the access right to the storage device 61 is arbitrated. However, it is naturally applicable to the arbitration of the usage right of the bus G. In the claims, the right to be arbitrated is called a right of use.

It is not a requirement of the present invention that all unit processing devices have a DMA controller.

Further, the DMA controller may determine the timing of the access request ED based only on the estimated waiting time information. For example, this is done when the central processing unit does not execute pipeline processing or does not have a configuration for outputting pipeline operation information. Even in this case, the DMA controller can output the original access request with good timing, so that the processing capability of the central processing unit and the entire electronic computer can be improved.

Furthermore, the inter-unit-processing-unit arbitration mechanism may also provide the predicted waiting time information (the set maximum time) to the DMA controller of the unit processing device which has not output the access request.

[0067]

As described above, according to the present invention, the DMA
The probability that the controller interferes with the operation of the central processing unit can be reduced, and the processing capacity of the central processing unit can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an electronic computer according to a first embodiment.

FIG. 2 is a block diagram showing a configuration of a conventional electronic computer.

FIG. 3 is an explanatory diagram showing arbitration contents by an internal arbitration mechanism.

FIG. 4 is a block diagram showing a configuration of an electronic computer according to a second embodiment.

[Explanation of symbols]

41 ... Unit processing unit, 411 ... Central processing unit, 412 ...
DMA controller 413 ... Internal arbitration mechanism, 412a ...
Request timing adjusting unit, 412b ... Transfer capability monitoring unit, 5
1 ... Unit processing device arbitration mechanism, 51a ... Predicted waiting time calculation unit, 61 ... Storage device.

Claims (4)

[Claims] 1. At least one unit processing device comprising a central processing unit, a DMA controller, and an internal arbitration mechanism for arbitrating a right to use a common storage device or a common bus between the central processing unit and the DMA controller. In the arbitration method for an electronic computer, which has an inter-device arbitration mechanism for arbitrating the right to use the common storage device or the common bus among a plurality of devices including the one or more unit processing devices, the inter-device arbitration is provided. Regarding the above-mentioned unit processing device that the mechanism has sent the usage right request, which does not grant the usage right permission at that time,
The predicted waiting time until the usage right is granted is calculated, the predicted waiting time information is given to the internal DMA controller, and the DM of the unit processing device to which the predicted waiting time information is given.
An arbitration system for an electronic computer, wherein the A controller gives a right to use request to the internal arbitration mechanism prioritizing a right to use request from the central processing unit at a timing determined based on the predicted waiting time information. 2. When the DMA controller tries to request a usage right, it outputs a potential usage right request having a lower priority than the usage right request from the central processing unit to the internal arbitration mechanism, 2. The arbitration system for an electronic computer according to claim 1, wherein the inter-device arbitration mechanism outputs predicted waiting time information or a usage right permission. 3. The central processing unit provides pipeline operation information to the DMA controller, and the DMA controller uses it from the central processing unit at a timing determined based on predicted waiting time information and pipeline operation information. 3. The arbitration system for an electronic computer according to claim 1, wherein a request for the right to use is given to the internal arbitration mechanism prior to the right request. 4. When the DMA controller controls transfer before the time point and the amount of data per unit time is smaller than a predetermined value, a right-of-use request and priority order from the central processing unit without timing adjustment. The arbitration method for an electronic computer according to any one of claims 1 to 3, characterized in that the same or higher usage right request is given to the internal arbitration mechanism.